From 4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Sat, 27 Jan 2018 14:37:51 +0100
Subject: bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file.  Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

* bsps/shared/cache

* bsps/@RTEMS_CPU@/shared/cache

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.
---
 bsps/i386/shared/cache/cache.c | 93 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 bsps/i386/shared/cache/cache.c

(limited to 'bsps/i386/shared/cache/cache.c')

diff --git a/bsps/i386/shared/cache/cache.c b/bsps/i386/shared/cache/cache.c
new file mode 100644
index 0000000000..df7909489d
--- /dev/null
+++ b/bsps/i386/shared/cache/cache.c
@@ -0,0 +1,93 @@
+/*
+ *  Cache Management Support Routines for the i386
+ */
+
+#include <rtems.h>
+#include <rtems/score/cpu.h>
+#include <libcpu/page.h>
+
+#define I386_CACHE_ALIGNMENT 16
+#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
+#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
+
+void _CPU_disable_cache(void)
+{
+  unsigned int regCr0;
+
+  regCr0 = i386_get_cr0();
+  regCr0 |= CR0_PAGE_LEVEL_CACHE_DISABLE;
+  regCr0 |= CR0_NO_WRITE_THROUGH;
+  i386_set_cr0( regCr0 );
+  rtems_cache_flush_entire_data();
+}
+
+/*
+ * Enable the entire cache
+ */
+
+void _CPU_enable_cache(void)
+{
+  unsigned int regCr0;
+
+  regCr0 = i386_get_cr0();
+  regCr0 &= ~(CR0_PAGE_LEVEL_CACHE_DISABLE);
+  regCr0 &= ~(CR0_NO_WRITE_THROUGH);
+  i386_set_cr0( regCr0 );
+  /*rtems_cache_flush_entire_data();*/
+}
+
+/*
+ * CACHE MANAGER: The following functions are CPU-specific.
+ * They provide the basic implementation for the rtems_* cache
+ * management routines. If a given function has no meaning for the CPU,
+ * it does nothing by default.
+ *
+ * FIXME: The routines below should be implemented per CPU,
+ *        to accomodate the capabilities of each.
+ */
+
+#if defined(I386_CACHE_ALIGNMENT)
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
+static void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
+static void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
+
+static void _CPU_cache_flush_entire_data(void)
+{
+  __asm__ volatile ("wbinvd");
+}
+static void _CPU_cache_invalidate_entire_data(void)
+{
+  __asm__ volatile ("invd");
+}
+
+static void _CPU_cache_enable_data(void)
+{
+        _CPU_enable_cache();
+}
+
+static void _CPU_cache_disable_data(void)
+{
+        _CPU_disable_cache();
+}
+
+static void _CPU_cache_invalidate_entire_instruction(void)
+{
+  __asm__ volatile ("invd");
+}
+
+static void _CPU_cache_enable_instruction(void)
+{
+  _CPU_enable_cache();
+}
+
+static void _CPU_cache_disable_instruction( void )
+{
+  _CPU_disable_cache();
+}
+#endif
+
+#include "../../../shared/cache/cacheimpl.h"
-- 
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