From a3db5001e5c8b6a0f744185e45a059db1242d805 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 28 Feb 2019 11:21:40 +0100 Subject: bsp/altera-cyclone-v: Enable FIQ for group 0 irqs --- bsps/arm/altera-cyclone-v/include/bsp.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'bsps/arm') diff --git a/bsps/arm/altera-cyclone-v/include/bsp.h b/bsps/arm/altera-cyclone-v/include/bsp.h index 523f667142..e3fdbab233 100644 --- a/bsps/arm/altera-cyclone-v/include/bsp.h +++ b/bsps/arm/altera-cyclone-v/include/bsp.h @@ -39,18 +39,20 @@ extern "C" { #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 +#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) +#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) + #ifndef BSP_ARM_A9MPCORE_PERIPHCLK extern uint32_t altera_cyclone_v_a9mpcore_periphclk; #define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk #define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK #endif -#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) - #define BSP_ARM_L2C_310_BASE 0xfffef000 #define BSP_ARM_L2C_310_ID 0x410000c9 -- cgit v1.2.3