From c37807e97ca8371e90be41b24c8801800c591cc3 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 21 Dec 2018 11:57:26 +0100
Subject: bsps/arm: Add cache size support for CP15

---
 bsps/arm/shared/cache/cache-cp15.c | 41 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

(limited to 'bsps/arm/shared')

diff --git a/bsps/arm/shared/cache/cache-cp15.c b/bsps/arm/shared/cache/cache-cp15.c
index 148d78d1fe..cdce02425f 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -29,6 +29,8 @@
 
 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
+#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
+
 #if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
 #define CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA
 #endif
@@ -180,4 +182,43 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_local_enable(level);
 }
 
+static inline size_t arm_cp15_get_cache_size(
+  uint32_t level,
+  uint32_t which
+)
+{
+  uint32_t clidr;
+  uint32_t loc;
+  uint32_t ccsidr;
+
+  clidr = arm_cp15_get_cache_level_id();
+  loc = arm_clidr_get_level_of_coherency(clidr);
+
+  if (level >= loc) {
+    return 0;
+  }
+
+  if (level == 0) {
+    level = loc - 1;
+  }
+
+  ccsidr = arm_cp15_get_cache_size_id_for_level(
+    ARM_CP15_CACHE_CSS_LEVEL(level) | which
+  );
+
+  return (1U << arm_ccsidr_get_line_power(ccsidr))
+    * arm_ccsidr_get_associativity(ccsidr)
+    * arm_ccsidr_get_num_sets(ccsidr);
+}
+
+static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
+{
+  return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_DATA);
+}
+
+static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
+{
+  return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_INSTRUCTION);
+}
+
 #include "../../shared/cache/cacheimpl.h"
-- 
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