From 8f8ccee0d9e1c3adfb1de484f26f6d9f6ff08708 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Mon, 23 Apr 2018 09:50:39 +0200
Subject: bsps: Move interrupt controller support to bsps

This patch is a part of the BSP source reorganization.

Update #3285.
---
 bsps/arm/lpc24xx/irq/irq-dispatch.c |  50 +++++++++++++++
 bsps/arm/lpc24xx/irq/irq.c          | 120 ++++++++++++++++++++++++++++++++++++
 2 files changed, 170 insertions(+)
 create mode 100644 bsps/arm/lpc24xx/irq/irq-dispatch.c
 create mode 100644 bsps/arm/lpc24xx/irq/irq.c

(limited to 'bsps/arm/lpc24xx')

diff --git a/bsps/arm/lpc24xx/irq/irq-dispatch.c b/bsps/arm/lpc24xx/irq/irq-dispatch.c
new file mode 100644
index 0000000000..66d05fdf9d
--- /dev/null
+++ b/bsps/arm/lpc24xx/irq/irq-dispatch.c
@@ -0,0 +1,50 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief LPC24XX interrupt support.
+ */
+
+/*
+ * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/score/armv4.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <bsp/lpc24xx.h>
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+void bsp_interrupt_dispatch(void)
+{
+  /* Read current vector number */
+  rtems_vector_number vector = VICVectAddr;
+
+  /* Enable interrupts in program status register */
+  uint32_t psr = _ARMV4_Status_irq_enable();
+
+  /* Dispatch interrupt handlers */
+  bsp_interrupt_handler_dispatch(vector);
+
+  /* Restore program status register */
+  _ARMV4_Status_restore(psr);
+
+  /* Acknowledge interrupt */
+  VICVectAddr = 0;
+}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/bsps/arm/lpc24xx/irq/irq.c b/bsps/arm/lpc24xx/irq/irq.c
new file mode 100644
index 0000000000..7801c37843
--- /dev/null
+++ b/bsps/arm/lpc24xx/irq/irq.c
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief LPC24XX interrupt support.
+ */
+
+/*
+ * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/score/armv4.h>
+#include <rtems/score/armv7m.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <bsp/lpc24xx.h>
+#include <bsp/linker-symbols.h>
+
+static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector)
+{
+  return vector <= BSP_INTERRUPT_VECTOR_MAX;
+}
+
+void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority)
+{
+  if (lpc24xx_irq_is_valid(vector)) {
+    if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) {
+      priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
+    }
+
+    #ifdef ARM_MULTILIB_ARCH_V4
+      VICVectPriorityBase [vector] = priority;
+    #else
+      _ARMV7M_NVIC_Set_priority((int) vector, (int) (priority << 3));
+    #endif
+  }
+}
+
+unsigned lpc24xx_irq_get_priority(rtems_vector_number vector)
+{
+  if (lpc24xx_irq_is_valid(vector)) {
+    #ifdef ARM_MULTILIB_ARCH_V4
+      return VICVectPriorityBase [vector];
+    #else
+      return (unsigned) (_ARMV7M_NVIC_Get_priority((int) vector) >> 3);
+    #endif
+  } else {
+    return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U;
+  }
+}
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+void bsp_interrupt_vector_enable(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  VICIntEnable = 1U << vector;
+}
+
+void bsp_interrupt_vector_disable(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  VICIntEnClear = 1U << vector;
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
+{
+  volatile uint32_t *addr = VICVectAddrBase;
+  volatile uint32_t *prio = VICVectPriorityBase;
+  rtems_vector_number i = 0;
+
+  /* Disable all interrupts */
+  VICIntEnClear = 0xffffffff;
+
+  /* Clear all software interrupts */
+  VICSoftIntClear = 0xffffffff;
+
+  /* Use IRQ category */
+  VICIntSelect = 0;
+
+  for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
+    /* Use the vector address register to store the vector number */
+    addr [i] = i;
+
+    /* Give vector lowest priority */
+    prio [i] = 15;
+  }
+
+  /* Reset priority mask register */
+  VICSWPrioMask = 0xffff;
+
+  /* Acknowledge interrupts for all priorities */
+  for (
+    i = LPC24XX_IRQ_PRIORITY_VALUE_MIN;
+    i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX;
+    ++i
+  ) {
+    VICVectAddr = 0;
+  }
+
+  /* Install the IRQ exception handler */
+  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
+
+  return RTEMS_SUCCESSFUL;
+}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
-- 
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