From ecf62845d4840f8a99c1f9beca5d98b46066fdb4 Mon Sep 17 00:00:00 2001 From: Pierre-Louis Garnier Date: Mon, 25 Feb 2019 22:30:09 +0000 Subject: arm/beagle: SPI driver --- bsps/arm/include/libcpu/am335x.h | 93 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) (limited to 'bsps/arm/include/libcpu') diff --git a/bsps/arm/include/libcpu/am335x.h b/bsps/arm/include/libcpu/am335x.h index 367e97cae9..a78cbd028d 100644 --- a/bsps/arm/include/libcpu/am335x.h +++ b/bsps/arm/include/libcpu/am335x.h @@ -19,6 +19,9 @@ #if !defined(_AM335X_H_) #define _AM335X_H_ +#define AM335X_MASK(Shift, Width) (((1 << (Width)) - 1) << (Shift)) + + /* Interrupt controller memory map */ #define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ @@ -649,6 +652,9 @@ #define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u) #define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u) #define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u) +#define AM335X_CM_PER_SPI0_CLKCTRL (0x4c) +#define AM335X_CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE (0x2u) +#define AM335X_CM_PER_SPI0_CLKCTRL_MODULEMODE (0x00000003u) #define AM335X_I2C_CON_XSA (0x00000100u) #define AM335X_I2C_CFG_10BIT_SLAVE_ADDR AM335X_I2C_CON_XSA #define AM335X_I2C_CON_XSA_SHIFT (0x00000008u) @@ -660,7 +666,6 @@ #define AM335X_I2C_SYSC_AUTOIDLE (0x00000001u) /*I2C0 module clock registers*/ - #define AM335X_CM_WKUP_CONTROL_CLKCTRL (0x4) #define AM335X_CM_WKUP_CLKSTCTRL (0x0) #define AM335X_CM_WKUP_I2C0_CLKCTRL (0xb8) @@ -675,6 +680,12 @@ #define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST (0x00030000u) #define AM335X_SOC_CM_WKUP_REGS (AM335X_CM_PER_ADDR + 0x400) +/* SPI0 module clock registers */ +#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST_FUNC (0x0u) +#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST_SHIFT (0x00000010u) +#define AM335X_CM_PER_CONTROL_CLKCTRL_IDLEST (0x00030000u) + + /* I2C status Register */ #define AM335X_I2C_IRQSTATUS_NACK (1 << 1) #define AM335X_I2C_IRQSTATUS_ROVR (1 << 11) @@ -701,4 +712,84 @@ #define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u) #define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF + +/* SPI registers */ +#define AM335X_SPI0_BASE 0x48030000 + /* SPI0 base address */ +#define AM335X_SPI1_BASE 0x481A0000 + /* SPI1 base address */ + +#define AM335X_SPI_REVISION 0x000 +#define AM335X_SPI_SYSCONFIG 0x110 +#define AM335X_SPI_SYSSTATUS 0x114 +#define AM335X_SPI_IRQSTATUS 0x118 +#define AM335X_SPI_IRQENABLE 0x11c +#define AM335X_SPI_WAKEUPENABLE 0x120 +#define AM335X_SPI_SYST 0x124 +#define AM335X_SPI_MODULCTRL 0x128 +#define AM335X_SPI_CH0CONF 0x12c +#define AM335X_SPI_CH0STAT 0x130 +#define AM335X_SPI_CH0CTRL 0x134 +#define AM335X_SPI_TX0 0x138 +#define AM335X_SPI_RX0 0x13C +#define AM335X_SPI_XFERLEVEL 0x17c + +/* SPI sysconfig Register */ +#define AM335X_SPI_SYSCONFIG_SOFTRESET (1 << 1) + +/* SPI sysstatus Register */ +#define AM335X_SPI_SYSSTATUS_RESETDONE (1 << 0) + +/* SPI interrupt status Register */ +#define AM335X_SPI_IRQSTATUS_TX0_EMPTY (1 << 0) +#define AM335X_SPI_IRQSTATUS_RX0_FULL (1 << 2) + +/* SPI interrupt enable Register */ +#define AM335X_SPI_IRQENABLE_TX0_EMPTY (1 << 0) +#define AM335X_SPI_IRQENABLE_RX0_FULL (1 << 2) + +/* SPI system Register */ +#define AM335X_SPI_SYST_SPIEN_0 (1 << 0) +#define AM335X_SPI_SYST_SPIDAT_0 (1 << 4) +#define AM335X_SPI_SYST_SPIDAT_1 (1 << 5) +#define AM335X_SPI_SYST_SPIDATDIR0 (1 << 8) +#define AM335X_SPI_SYST_SPIDATDIR1 (1 << 9) +#define AM335X_SPI_SYST_SSB (1 << 11) + +/* SPI modulctrl Register */ +#define AM335X_SPI_MODULCTRL_SINGLE (1 << 0) +#define AM335X_SPI_MODULCTRL_PIN34 (1 << 1) +#define AM335X_SPI_MODULCTRL_MS (1 << 2) + +/* SPI Channel 0 Configuration Register */ +#define AM335X_SPI_CH0CONF_PHA (1 << 0) +#define AM335X_SPI_CH0CONF_POL (1 << 1) +#define AM335X_SPI_CH0CONF_CLKD_SHIFT 2 +#define AM335X_SPI_CH0CONF_CLKD_WIDTH 4 +#define AM335X_SPI_CH0CONF_CLKD_MASK AM335X_MASK(AM335X_SPI_CH0CONF_CLKD_SHIFT, AM335X_SPI_CH0CONF_CLKD_WIDTH) +#define AM335X_SPI_CH0CONF_CLKD(X) (((X) << AM335X_SPI_CH0CONF_CLKD_SHIFT) & AM335X_SPI_CH0CONF_CLKD_MASK) +#define AM335X_SPI_CH0CONF_EPOL (1 << 6) +#define AM335X_SPI_CH0CONF_WL_SHIFT 7 +#define AM335X_SPI_CH0CONF_WL_WIDTH 5 +#define AM335X_SPI_CH0CONF_WL_MASK AM335X_MASK(AM335X_SPI_CH0CONF_WL_SHIFT, AM335X_SPI_CH0CONF_WL_WIDTH) +#define AM335X_SPI_CH0CONF_WL(X) (((X) << AM335X_SPI_CH0CONF_WL_SHIFT) & AM335X_SPI_CH0CONF_WL_MASK) +#define AM335X_SPI_CH0CONF_TRM_SHIFT 12 +#define AM335X_SPI_CH0CONF_TRM_WIDTH 2 +#define AM335X_SPI_CH0CONF_TRM_MASK AM335X_MASK(AM335X_SPI_CH0CONF_TRM_SHIFT, AM335X_SPI_CH0CONF_TRM_WIDTH) +#define AM335X_SPI_CH0CONF_TRM(X) (((X) << AM335X_SPI_CH0CONF_TRM_SHIFT) & AM335X_SPI_CH0CONF_TRM_MASK) +#define AM335X_SPI_CH0CONF_DPE0 (1 << 16) +#define AM335X_SPI_CH0CONF_DPE1 (1 << 17) +#define AM335X_SPI_CH0CONF_IS (1 << 18) +#define AM335X_SPI_CH0CONF_FORCE (1 << 20) +#define AM335X_SPI_CH0CONF_SBPOL (1 << 27) +#define AM335X_SPI_CH0CONF_FFEW (1 << 27) +#define AM335X_SPI_CH0CONF_FFER (1 << 28) + +/* SPI Channel 0 Status Register */ +#define AM335X_SPI_CH0STAT_RXS (1 << 0) +#define AM335X_SPI_CH0STAT_TXS (1 << 1) + +/* SPI Channel 0 Control Register */ +#define AM335X_SPI_CH0CTRL_EN (1 << 0) + #endif -- cgit v1.2.3