From 7141afbb0ea41675ef8cf7e60f398aaf900defd9 Mon Sep 17 00:00:00 2001 From: Christian Mauderer Date: Fri, 9 Oct 2020 15:55:35 +0200 Subject: bsp/imxrt: Add new BSP Update #4180 --- bsps/arm/imxrt/start/bspstart.c | 141 +++++++++++++++++++++++++++++++++ bsps/arm/imxrt/start/bspstarthooks.c | 51 ++++++++++++ bsps/arm/imxrt/start/flash-boot-data.c | 37 +++++++++ bsps/arm/imxrt/start/flash-config.c | 60 ++++++++++++++ bsps/arm/imxrt/start/flash-dcd.c | 38 +-------- bsps/arm/imxrt/start/flash-ivt.c | 39 +++++++++ bsps/arm/imxrt/start/imxrt-ffec-init.c | 86 ++++++++++++++++++++ bsps/arm/imxrt/start/linkcmds.flexspi | 35 ++++++++ bsps/arm/imxrt/start/linkcmds.sdram | 23 ++++++ bsps/arm/imxrt/start/mpu-config.c | 75 ++++++++++++++++++ 10 files changed, 550 insertions(+), 35 deletions(-) create mode 100644 bsps/arm/imxrt/start/bspstart.c create mode 100644 bsps/arm/imxrt/start/bspstarthooks.c create mode 100644 bsps/arm/imxrt/start/flash-boot-data.c create mode 100644 bsps/arm/imxrt/start/flash-config.c create mode 100644 bsps/arm/imxrt/start/flash-ivt.c create mode 100644 bsps/arm/imxrt/start/imxrt-ffec-init.c create mode 100644 bsps/arm/imxrt/start/linkcmds.flexspi create mode 100644 bsps/arm/imxrt/start/linkcmds.sdram create mode 100644 bsps/arm/imxrt/start/mpu-config.c (limited to 'bsps/arm/imxrt/start') diff --git a/bsps/arm/imxrt/start/bspstart.c b/bsps/arm/imxrt/start/bspstart.c new file mode 100644 index 0000000000..884f0aaf92 --- /dev/null +++ b/bsps/arm/imxrt/start/bspstart.c @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +uint32_t imxrt_systick_frequency(void) +{ + return CLOCK_GetCpuClkFreq(); +} + +static void imxrt_disable_wait_mode(void) +{ + /* + * Prevent processor from entering WAIT or SLEEP mode when a WFI is executed. + * This would switch off the normal interrupt controller and activate an + * alternative one. See "i.MX RT1050 Reference Manual, Rev. 4, 12/2019" + * chapter 14.6.3.2.1 "Entering WAIT mode". + * + * FIXME: For saving energy it would be a better solution to support the + * alternative interrupt controller. But that makes a bit of work necessary on + * every WFI. + */ + CLOCK_SetMode(kCLOCK_ModeRun); +} + +void bsp_start(void) +{ + imxrt_disable_wait_mode(); + + bsp_interrupt_initialize(); + rtems_cache_coherent_add_area( + bsp_section_nocacheheap_begin, + (uintptr_t) bsp_section_nocacheheap_size + ); +} + +const void *bsp_fdt_get(void) +{ + return imxrt_dtb; +} + +bool imxrt_fdt_node_is_enabled(const void *fdt, int node) +{ + int len; + const uint32_t *val; + + val = fdt_getprop(fdt, node, "status", &len); + if (val != NULL && + (strcmp((char*)val, "ok") == 0 || strcmp((char*)val, "okay") == 0)) { + return true; + } + + return false; +} + +void *imx_get_reg_of_node(const void *fdt, int node) +{ + int len; + const uint32_t *val; + + val = fdt_getprop(fdt, node, "reg", &len); + if (val == NULL || len < 4) { + return NULL; + } + + return (void *) fdt32_to_cpu(val[0]); +} + +rtems_vector_number imx_get_irq_of_node( + const void *fdt, + int node, + size_t index +) +{ + int len; + const uint32_t *val; + + val = fdt_getprop(fdt, node, "interrupts", &len); + if (val == NULL || len < (int) ((index) * 4)) { + return BSP_INTERRUPT_VECTOR_INVALID; + } + + return fdt32_to_cpu(val[index]); +} + +uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) +{ + return intr[0]; +} + +/* Make sure to pull in the flash headers */ +__attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data; +__attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table; +__attribute__((used)) static const void *hdr_btd = &imxrt_boot_data; +__attribute__((used)) static const void *hdr_fsc = &imxrt_flexspi_config; + +/* pull in some drivers */ +__attribute__((used)) static const void *drv_iomux = &imx_iomux_configure_pins; + +RTEMS_SYSINIT_ITEM(imxrt_lpspi_init, RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_MIDDLE); +RTEMS_SYSINIT_ITEM(imxrt_lpi2c_init, RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_MIDDLE); +RTEMS_SYSINIT_ITEM(imxrt_ffec_init, RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_MIDDLE); diff --git a/bsps/arm/imxrt/start/bspstarthooks.c b/bsps/arm/imxrt/start/bspstarthooks.c new file mode 100644 index 0000000000..2b6b59f66b --- /dev/null +++ b/bsps/arm/imxrt/start/bspstarthooks.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include + +#include +#include +#include + +BSP_START_TEXT_SECTION void bsp_start_hook_0(void) +{ + /* FIXME: Initializing SDRAM is currently done by DCD. It would be more user + * friendly if that would be done here with a readable structure. */ + if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) { + SCB_EnableICache(); + } + + if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) { + SCB_EnableDCache(); + } + + _ARMV7M_MPU_Setup(imxrt_config_mpu_region, imxrt_config_mpu_region_count); +} + +BSP_START_TEXT_SECTION void bsp_start_hook_1(void) +{ + bsp_start_copy_sections_compact(); + SCB_CleanDCache(); + SCB_InvalidateICache(); + bsp_start_clear_bss(); + + BOARD_BootClockRUN(); + BOARD_InitDEBUG_UARTPins(); + + /* Reduce frequency for I2C */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); +} diff --git a/bsps/arm/imxrt/start/flash-boot-data.c b/bsps/arm/imxrt/start/flash-boot-data.c new file mode 100644 index 0000000000..cf0430af72 --- /dev/null +++ b/bsps/arm/imxrt/start/flash-boot-data.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +const BOOT_DATA_T imxrt_boot_data = { + .start = (uint32_t) imxrt_memory_flexspi_config_begin, + .size = IMXRT_MEMORY_FLEXSPI_FLASH_SIZE, + .plugin = PLUGIN_FLAG, + .placeholder = 0xFFFFFFFF, +}; diff --git a/bsps/arm/imxrt/start/flash-config.c b/bsps/arm/imxrt/start/flash-config.c new file mode 100644 index 0000000000..07324f1330 --- /dev/null +++ b/bsps/arm/imxrt/start/flash-config.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +const flexspi_nor_config_t imxrt_flexspi_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + .controllerMiscOption = (1 << kFlexSpiMiscOffset_DdrModeEnable) | + (1 << kFlexSpiMiscOffset_WordAddressableEnable) | + (1 << kFlexSpiMiscOffset_SafeConfigFreqEnable) | + (1 << kFlexSpiMiscOffset_DiffClkEnable), + .deviceType = kFlexSpiDeviceType_SerialRAM, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = IMXRT_MEMORY_FLEXSPI_FLASH_SIZE, + .dataValidTime = {16u, 16u}, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + .lutCustomSeq = {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, + {0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}, + }, + .pageSize = 0x200, + .sectorSize = 0x40000, + .blockSize = 0x40000, + .isUniformBlockSize = 1, +}; diff --git a/bsps/arm/imxrt/start/flash-dcd.c b/bsps/arm/imxrt/start/flash-dcd.c index 6dced830b9..a53e5bda39 100644 --- a/bsps/arm/imxrt/start/flash-dcd.c +++ b/bsps/arm/imxrt/start/flash-dcd.c @@ -5,38 +5,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ +#include +#include -#include "dcd.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) __attribute__((section(".boot_hdr.dcd_data"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.dcd_data" -#endif - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: DCDx V2.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 0.0.0 -board: IMXRT1050-EVKB -output_format: c_array - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ -const uint8_t dcd_data[] = { +const uint8_t imxrt_dcd_data[] = { /* HEADER */ /* Tag */ 0xD2, @@ -308,8 +281,3 @@ const uint8_t dcd_data[] = { 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 }; /* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ - -#else -const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/bsps/arm/imxrt/start/flash-ivt.c b/bsps/arm/imxrt/start/flash-ivt.c new file mode 100644 index 0000000000..fd396d5e1a --- /dev/null +++ b/bsps/arm/imxrt/start/flash-ivt.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void _start(void); + +const ivt imxrt_image_vector_table = { + .hdr = IVT_HEADER, + .entry = (uint32_t) _start - 1, /* remove thumb mode flag! */ + .dcd = (uint32_t) &imxrt_dcd_data, + .boot_data = (uint32_t) &imxrt_boot_data, + .self = (uint32_t) &imxrt_image_vector_table, +}; diff --git a/bsps/arm/imxrt/start/imxrt-ffec-init.c b/bsps/arm/imxrt/start/imxrt-ffec-init.c new file mode 100644 index 0000000000..4b71944c00 --- /dev/null +++ b/bsps/arm/imxrt/start/imxrt-ffec-init.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +void imxrt_ffec_init(void) +{ + volatile IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR; + const void *fdt; + int node; + + fdt = bsp_fdt_get(); + + const clock_enet_pll_config_t config = { + .enableClkOutput = true, + .enableClkOutput25M = false, + .loopDivider = 1 + }; + + CLOCK_InitEnetPll(&config); + + iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + + node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec"); + if (node >= 0) { + struct imx_gpio_pin reset; + struct imx_gpio_pin interrupt; + rtems_status_code sc; + + sc = imx_gpio_init_from_fdt_property( + &reset, node, "phy-reset-gpios", + IMX_GPIO_MODE_OUTPUT, 0); + + if (sc == RTEMS_SUCCESSFUL) { + sc = imx_gpio_init_from_fdt_property( + &interrupt, node, "rtems,phy-interrupt-gpios", + IMX_GPIO_MODE_INPUT, 0); + + imx_gpio_set_output(&reset, 0); + if (sc == RTEMS_SUCCESSFUL) { + /* Force interrupt GPIO to high. Otherwise we + * get NAND_TREE mode of the PHY. */ + interrupt.mode = IMX_GPIO_MODE_OUTPUT; + imx_gpio_init(&interrupt); + imx_gpio_set_output(&interrupt, 1); + } + rtems_counter_delay_nanoseconds(100000); + imx_gpio_set_output(&reset, 1); + rtems_counter_delay_nanoseconds(5); + if (sc == RTEMS_SUCCESSFUL) { + interrupt.mode = IMX_GPIO_MODE_INPUT; + imx_gpio_init(&interrupt); + } + } + } +} diff --git a/bsps/arm/imxrt/start/linkcmds.flexspi b/bsps/arm/imxrt/start/linkcmds.flexspi new file mode 100644 index 0000000000..4196bb33e5 --- /dev/null +++ b/bsps/arm/imxrt/start/linkcmds.flexspi @@ -0,0 +1,35 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", FLEXSPI); +REGION_ALIAS ("REGION_VECTOR", FLEXSPI); +REGION_ALIAS ("REGION_TEXT", FLEXSPI); +REGION_ALIAS ("REGION_TEXT_LOAD", FLEXSPI); +REGION_ALIAS ("REGION_RODATA", FLEXSPI); +REGION_ALIAS ("REGION_RODATA_LOAD", FLEXSPI); +REGION_ALIAS ("REGION_DATA", SDRAM); +REGION_ALIAS ("REGION_DATA_LOAD", FLEXSPI); +REGION_ALIAS ("REGION_FAST_TEXT", FLEXSPI); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", FLEXSPI); +REGION_ALIAS ("REGION_FAST_DATA", SDRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", FLEXSPI); +REGION_ALIAS ("REGION_BSS", SDRAM); +REGION_ALIAS ("REGION_WORK", SDRAM); +REGION_ALIAS ("REGION_STACK", SDRAM); +REGION_ALIAS ("REGION_NOCACHE", SDRAM_NOCACHE); +REGION_ALIAS ("REGION_NOCACHE_LOAD", FLEXSPI); + +bsp_vector_table_in_start_section = 1; + +SECTIONS { + . = imxrt_memory_flexspi_begin; + .flash_config : ALIGN_WITH_INPUT { + KEEP(*(.boot_hdr.conf)) + } > FLEXSPI_CONFIG AT > FLEXSPI_CONFIG + .flash_ivt : ALIGN_WITH_INPUT { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > FLEXSPI_IVT AT > FLEXSPI_IVT +} + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/imxrt/start/linkcmds.sdram b/bsps/arm/imxrt/start/linkcmds.sdram new file mode 100644 index 0000000000..87d1dffa53 --- /dev/null +++ b/bsps/arm/imxrt/start/linkcmds.sdram @@ -0,0 +1,23 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", SDRAM); +REGION_ALIAS ("REGION_VECTOR", SDRAM); +REGION_ALIAS ("REGION_TEXT", SDRAM); +REGION_ALIAS ("REGION_TEXT_LOAD", SDRAM); +REGION_ALIAS ("REGION_RODATA", SDRAM); +REGION_ALIAS ("REGION_RODATA_LOAD", SDRAM); +REGION_ALIAS ("REGION_DATA", SDRAM); +REGION_ALIAS ("REGION_DATA_LOAD", SDRAM); +REGION_ALIAS ("REGION_FAST_TEXT", SDRAM); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", SDRAM); +REGION_ALIAS ("REGION_FAST_DATA", SDRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", SDRAM); +REGION_ALIAS ("REGION_BSS", SDRAM); +REGION_ALIAS ("REGION_WORK", SDRAM); +REGION_ALIAS ("REGION_STACK", SDRAM); +REGION_ALIAS ("REGION_NOCACHE", SDRAM_NOCACHE); +REGION_ALIAS ("REGION_NOCACHE_LOAD", SDRAM); + +bsp_vector_table_in_start_section = 1; + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/imxrt/start/mpu-config.c b/bsps/arm/imxrt/start/mpu-config.c new file mode 100644 index 0000000000..31c39bc16f --- /dev/null +++ b/bsps/arm/imxrt/start/mpu-config.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config + imxrt_config_mpu_region [] = { + { + .begin = imxrt_memory_sdram_begin, + .end = imxrt_memory_sdram_end, + .rasr = ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + }, { + .begin = imxrt_memory_ocram_begin, + .end = imxrt_memory_ocram_end, + .rasr = ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + }, { + .begin = imxrt_memory_flexspi_config_begin, + .end = imxrt_memory_flexspi_end, + .rasr = ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B + | ARMV7M_MPU_RASR_ENABLE, + }, { + .begin = imxrt_memory_sdram_nocache_begin, + .end = imxrt_memory_sdram_nocache_end, + .rasr = ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x2) + | ARMV7M_MPU_RASR_ENABLE, + }, { + .begin = imxrt_memory_peripheral_begin, + .end = imxrt_memory_peripheral_end, + .rasr = ARMV7M_MPU_RASR_XN + | ARMV7M_MPU_RASR_AP(0x3) + | ARMV7M_MPU_RASR_TEX(0x2) + | ARMV7M_MPU_RASR_ENABLE, + }, { + .begin = imxrt_memory_null_begin, + .end = imxrt_memory_null_end, + .rasr = ARMV7M_MPU_RASR_XN + | ARMV7M_MPU_RASR_AP(0x0) + | ARMV7M_MPU_RASR_ENABLE, + } + }; + +BSP_START_DATA_SECTION const size_t imxrt_config_mpu_region_count = + RTEMS_ARRAY_SIZE(imxrt_config_mpu_region); -- cgit v1.2.3