From 81c7f5be92803f96c39b5325006071771709125b Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 3 Dec 2020 15:31:40 +0100 Subject: arm/fvp: New BSP This BSP supports the Arm Fixed Virtual Platform. Only the Cortex-R52 processor configuration is supported by the BSP. It should be easy to add support for other variants if needed. Update #4202. --- bsps/arm/fvp/include/bsp/irq.h | 47 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 bsps/arm/fvp/include/bsp/irq.h (limited to 'bsps/arm/fvp/include/bsp/irq.h') diff --git a/bsps/arm/fvp/include/bsp/irq.h b/bsps/arm/fvp/include/bsp/irq.h new file mode 100644 index 0000000000..7b4450ffec --- /dev/null +++ b/bsps/arm/fvp/include/bsp/irq.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_FVP_IRQ_H +#define LIBBSP_ARM_FVP_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#include + +#endif /* ASM */ + +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX (32 + BSP_ARM_SHARED_PERIPHERAL_INTERRUPT_COUNT) + +#endif /* LIBBSP_ARM_FVP_IRQ_H */ -- cgit v1.2.3