From f9a597950b1d61c9c1283dc85ae2a4c579d96263 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 23 Jul 2015 08:36:30 +0200 Subject: doc: Add SMP section to CPU Arch Supplement --- doc/cpu_supplement/arm.t | 5 +++++ doc/cpu_supplement/avr.t | 4 ++++ doc/cpu_supplement/bfin.t | 4 ++++ doc/cpu_supplement/epiphany.t | 4 ++++ doc/cpu_supplement/general.t | 5 +++++ doc/cpu_supplement/h8300.t | 4 ++++ doc/cpu_supplement/i386.t | 4 ++++ doc/cpu_supplement/lm32.t | 4 ++++ doc/cpu_supplement/m32c.t | 4 ++++ doc/cpu_supplement/m32r.t | 4 ++++ doc/cpu_supplement/m68k.t | 4 ++++ doc/cpu_supplement/microblaze.t | 4 ++++ doc/cpu_supplement/mips.t | 4 ++++ doc/cpu_supplement/nios2.t | 4 ++++ doc/cpu_supplement/or1k.t | 4 ++++ doc/cpu_supplement/powerpc.t | 5 +++++ doc/cpu_supplement/sh.t | 4 ++++ doc/cpu_supplement/sparc.t | 5 +++++ doc/cpu_supplement/sparc64.t | 4 ++++ doc/cpu_supplement/v850.t | 4 ++++ 20 files changed, 84 insertions(+) diff --git a/doc/cpu_supplement/arm.t b/doc/cpu_supplement/arm.t index 304e1e1f0a..e24ca00ca8 100644 --- a/doc/cpu_supplement/arm.t +++ b/doc/cpu_supplement/arm.t @@ -172,6 +172,11 @@ following actions: @item executes an infinite loop to simulate a halt processor instruction. @end itemize +@section Symmetric Multiprocessing + +SMP is supported on ARMv7-A. Available platforms are the Altera Cyclone V and +the Xilinx Zynq. + @section Thread-Local Storage Thread-local storage is supported. diff --git a/doc/cpu_supplement/avr.t b/doc/cpu_supplement/avr.t index 233e0525f6..9ad4d2ef2c 100644 --- a/doc/cpu_supplement/avr.t +++ b/doc/cpu_supplement/avr.t @@ -117,6 +117,10 @@ actions: simulate a halt processor instruction. @end itemize +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not supported due to a broken tool chain. diff --git a/doc/cpu_supplement/bfin.t b/doc/cpu_supplement/bfin.t index 320061aa87..3beed677e4 100644 --- a/doc/cpu_supplement/bfin.t +++ b/doc/cpu_supplement/bfin.t @@ -130,6 +130,10 @@ actions: simulate a halt processor instruction. @end itemize +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/epiphany.t b/doc/cpu_supplement/epiphany.t index a0976cf3b6..87f74c324f 100644 --- a/doc/cpu_supplement/epiphany.t +++ b/doc/cpu_supplement/epiphany.t @@ -73,3 +73,7 @@ following actions: @item places the error code in @code{r0}, and @item executes an infinite loop to simulate a halt processor instruction. @end itemize + +@section Symmetric Multiprocessing + +SMP is not supported. diff --git a/doc/cpu_supplement/general.t b/doc/cpu_supplement/general.t index 82b8dcbbd4..43f91e1d14 100644 --- a/doc/cpu_supplement/general.t +++ b/doc/cpu_supplement/general.t @@ -344,6 +344,11 @@ interrupts and halts the processor. In each of the architecture specific chapters, this describes the precise operations of the default CPU specific fatal error handler. +@section Symmetric Multiprocessing + +This section contains information about the Symmetric Multiprocessing (SMP) +status of a particular architecture. + @section Thread-Local Storage In order to support thread-local storage (TLS) the CPU port must implement the diff --git a/doc/cpu_supplement/h8300.t b/doc/cpu_supplement/h8300.t index 8120a31e30..8c50ffb614 100644 --- a/doc/cpu_supplement/h8300.t +++ b/doc/cpu_supplement/h8300.t @@ -2,6 +2,10 @@ @chapter Renesas H8/300 Specific Information +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/i386.t b/doc/cpu_supplement/i386.t index 716cf9bc11..77acacefc2 100644 --- a/doc/cpu_supplement/i386.t +++ b/doc/cpu_supplement/i386.t @@ -266,6 +266,10 @@ The default fatal error handler for this architecture disables processor interrupts, places the error code in EAX, and executes a HLT instruction to halt the processor. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/lm32.t b/doc/cpu_supplement/lm32.t index a81e0b57ba..6aab8e30f8 100644 --- a/doc/cpu_supplement/lm32.t +++ b/doc/cpu_supplement/lm32.t @@ -163,6 +163,10 @@ interrupts and halts the processor. In each of the architecture specific chapters, this describes the precise operations of the default CPU specific fatal error handler. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/m32c.t b/doc/cpu_supplement/m32c.t index ce738fe0a7..98d86c1cf2 100644 --- a/doc/cpu_supplement/m32c.t +++ b/doc/cpu_supplement/m32c.t @@ -2,6 +2,10 @@ @chapter Renesas M32C Specific Information +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/m32r.t b/doc/cpu_supplement/m32r.t index f70c185f27..951bf94ec9 100644 --- a/doc/cpu_supplement/m32r.t +++ b/doc/cpu_supplement/m32r.t @@ -2,6 +2,10 @@ @chapter Renesas M32R Specific Information +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/m68k.t b/doc/cpu_supplement/m68k.t index a3ddc88db3..7201571541 100644 --- a/doc/cpu_supplement/m68k.t +++ b/doc/cpu_supplement/m68k.t @@ -357,6 +357,10 @@ The default fatal error handler for this architecture disables processor interrupts to level 7, places the error code in D0, and executes a @code{stop} instruction to simulate a halt processor instruction. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is supported. diff --git a/doc/cpu_supplement/microblaze.t b/doc/cpu_supplement/microblaze.t index b641d4314f..ff52d2e4ee 100644 --- a/doc/cpu_supplement/microblaze.t +++ b/doc/cpu_supplement/microblaze.t @@ -2,6 +2,10 @@ @chapter Xilinx MicroBlaze Specific Information +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/mips.t b/doc/cpu_supplement/mips.t index 7d6fcb3527..c966bf5e9c 100644 --- a/doc/cpu_supplement/mips.t +++ b/doc/cpu_supplement/mips.t @@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables processor interrupts, places the error code in @b{XXX}, and executes a @code{XXX} instruction to simulate a halt processor instruction. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/nios2.t b/doc/cpu_supplement/nios2.t index 9013f15790..2d423c7e3b 100644 --- a/doc/cpu_supplement/nios2.t +++ b/doc/cpu_supplement/nios2.t @@ -2,6 +2,10 @@ @chapter Altera Nios II Specific Information +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t index cce55fd9ab..4d14f74ede 100644 --- a/doc/cpu_supplement/or1k.t +++ b/doc/cpu_supplement/or1k.t @@ -74,3 +74,7 @@ following actions: @item places the error code in @code{r0}, and @item executes an infinite loop to simulate a halt processor instruction. @end itemize + +@section Symmetric Multiprocessing + +SMP is not supported. diff --git a/doc/cpu_supplement/powerpc.t b/doc/cpu_supplement/powerpc.t index abf02e07d9..4e7af1f958 100644 --- a/doc/cpu_supplement/powerpc.t +++ b/doc/cpu_supplement/powerpc.t @@ -657,6 +657,11 @@ If the Program Exception returns, then the following actions are performed: @end itemize +@section Symmetric Multiprocessing + +SMP is supported. Available platforms are the Freescale QorIQ P series (e.g. +P1020) and T series (e.g. T2080, T4240). + @section Thread-Local Storage Thread-local storage is supported. diff --git a/doc/cpu_supplement/sh.t b/doc/cpu_supplement/sh.t index 763c31e96d..fb2d3c25c2 100644 --- a/doc/cpu_supplement/sh.t +++ b/doc/cpu_supplement/sh.t @@ -139,6 +139,10 @@ The default fatal error handler for this architecture disables processor interrupts, places the error code in @b{XXX}, and executes a @code{XXX} instruction to simulate a halt processor instruction. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t index 740643a4d3..749c1fd2de 100644 --- a/doc/cpu_supplement/sparc.t +++ b/doc/cpu_supplement/sparc.t @@ -969,6 +969,11 @@ error source in register @code{g2}, and the error code in register @code{g3}. It will then generate a system error which will hand over control to the debugger, simulator, etc. +@section Symmetric Multiprocessing + +SMP is supported. Available platforms are the Cobham Gaisler GR712RC and +GR740. + @section Thread-Local Storage Thread-local storage is supported. diff --git a/doc/cpu_supplement/sparc64.t b/doc/cpu_supplement/sparc64.t index f93000893a..5c07989467 100644 --- a/doc/cpu_supplement/sparc64.t +++ b/doc/cpu_supplement/sparc64.t @@ -773,6 +773,10 @@ default fatal error handler disables processor interrupts to level 15, places the error code in g1, and goes into an infinite loop to simulate a halt processor instruction. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is supported. diff --git a/doc/cpu_supplement/v850.t b/doc/cpu_supplement/v850.t index e8ef05ee10..ab844614f5 100644 --- a/doc/cpu_supplement/v850.t +++ b/doc/cpu_supplement/v850.t @@ -103,6 +103,10 @@ following actions: @item executes a halt processor instruction. @end itemize +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. -- cgit v1.2.3