From ece97542257442681b3acd05d2206034c0adf8bd Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 11 Feb 2014 14:48:35 +0100 Subject: sparc: Increase CPU_STRUCTURE_ALIGNMENT to 32 Recent LEON4 systems use a cache line size of 32 bytes. --- cpukit/score/cpu/sparc/rtems/score/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 9706e45668..7e54d2257f 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -211,7 +211,7 @@ extern "C" { * The SPARC does not appear to have particularly strict alignment * requirements. This value was chosen to take advantages of caches. */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE -- cgit v1.2.3