From ece004d72a6ef2968c56fb32295606642fd0b4c5 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 16 Jan 2006 15:12:44 +0000 Subject: 2006-01-16 Joel Sherrill * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. As a side-effect, grammar and spelling errors were corrected, spacing errors were address, and some variable names were improved. --- cpukit/score/cpu/avr/ChangeLog | 6 ++++++ cpukit/score/cpu/avr/rtems/score/cpu.h | 11 +++++------ cpukit/score/cpu/c4x/ChangeLog | 6 ++++++ cpukit/score/cpu/c4x/rtems/score/cpu.h | 9 ++++----- cpukit/score/cpu/h8300/ChangeLog | 6 ++++++ cpukit/score/cpu/h8300/rtems/score/cpu.h | 9 ++++----- cpukit/score/cpu/m68k/ChangeLog | 6 ++++++ cpukit/score/cpu/m68k/rtems/score/cpu.h | 4 ++-- cpukit/score/cpu/mips/ChangeLog | 6 ++++++ cpukit/score/cpu/mips/rtems/score/cpu.h | 9 ++++----- cpukit/score/cpu/sh/ChangeLog | 6 ++++++ cpukit/score/cpu/sh/rtems/score/cpu.h | 4 ++-- cpukit/score/cpu/sparc/ChangeLog | 6 ++++++ cpukit/score/cpu/sparc/rtems/score/cpu.h | 4 ++-- cpukit/score/cpu/unix/ChangeLog | 6 ++++++ cpukit/score/cpu/unix/rtems/score/cpu.h | 14 ++++++++++---- 16 files changed, 81 insertions(+), 31 deletions(-) diff --git a/cpukit/score/cpu/avr/ChangeLog b/cpukit/score/cpu/avr/ChangeLog index dd80f2008d..e57a655e4e 100644 --- a/cpukit/score/cpu/avr/ChangeLog +++ b/cpukit/score/cpu/avr/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-08 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16, unsigned32. diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h index fc3bc39df8..c614ea8342 100644 --- a/cpukit/score/cpu/avr/rtems/score/cpu.h +++ b/cpukit/score/cpu/avr/rtems/score/cpu.h @@ -3,10 +3,10 @@ */ /* - * This include file contains information pertaining to the XXX + * This include file contains information pertaining to the AVR * processor. * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -134,8 +134,7 @@ extern "C" { * If TRUE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization. * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. * * AVR Specific Information: * @@ -568,7 +567,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE /* - * Should be large enough to run all RTEMS tests. This insures + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. * * AVR Specific Information: @@ -1106,7 +1105,7 @@ void _CPU_Context_restore_fp( * Some CPUs have special instructions which swap a 32-bit quantity in * a single instruction (e.g. i486). It is probably best to avoid * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that + * that interrupts would probably have to be disabled to ensure that * an interrupt does not try to access the same "chunk" with the wrong * endian. Another good reason is that on some CPUs, the endian bit * endianness for ALL fetches -- both code and data -- so the code diff --git a/cpukit/score/cpu/c4x/ChangeLog b/cpukit/score/cpu/c4x/ChangeLog index 565fe493a6..9d93922440 100644 --- a/cpukit/score/cpu/c4x/ChangeLog +++ b/cpukit/score/cpu/c4x/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-08 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16, unsigned32. diff --git a/cpukit/score/cpu/c4x/rtems/score/cpu.h b/cpukit/score/cpu/c4x/rtems/score/cpu.h index b557c4d727..b268a44499 100644 --- a/cpukit/score/cpu/c4x/rtems/score/cpu.h +++ b/cpukit/score/cpu/c4x/rtems/score/cpu.h @@ -6,7 +6,7 @@ * This include file contains information pertaining to the C4x * processor. * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -138,8 +138,7 @@ extern "C" { * If TRUE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization. * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. * * C4x Specific Information: * @@ -678,7 +677,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE /* - * Should be large enough to run all RTEMS tests. This insures + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. * * C4x Specific Information: @@ -1225,7 +1224,7 @@ void _CPU_Context_restore_fp( * Some CPUs have special instructions which swap a 32-bit quantity in * a single instruction (e.g. i486). It is probably best to avoid * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that + * that interrupts would probably have to be disabled to ensure that * an interrupt does not try to access the same "chunk" with the wrong * endian. Another good reason is that on some CPUs, the endian bit * endianness for ALL fetches -- both code and data -- so the code diff --git a/cpukit/score/cpu/h8300/ChangeLog b/cpukit/score/cpu/h8300/ChangeLog index b9f0b20963..2ab126b563 100644 --- a/cpukit/score/cpu/h8300/ChangeLog +++ b/cpukit/score/cpu/h8300/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-08 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16, unsigned32. diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h index 735ff448b9..c7f3b3c77b 100644 --- a/cpukit/score/cpu/h8300/rtems/score/cpu.h +++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h @@ -6,7 +6,7 @@ * This include file contains information pertaining to the H8300 * processor. * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -136,8 +136,7 @@ extern "C" { * If TRUE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization. * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. * * H8300 Specific Information: * @@ -531,7 +530,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE /* - * Should be large enough to run all RTEMS tests. This insures + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. * * H8300 Specific Information: @@ -1147,7 +1146,7 @@ void _CPU_Context_restore_fp( * Some CPUs have special instructions which swap a 32-bit quantity in * a single instruction (e.g. i486). It is probably best to avoid * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that + * that interrupts would probably have to be disabled to ensure that * an interrupt does not try to access the same "chunk" with the wrong * endian. Another good reason is that on some CPUs, the endian bit * endianness for ALL fetches -- both code and data -- so the code diff --git a/cpukit/score/cpu/m68k/ChangeLog b/cpukit/score/cpu/m68k/ChangeLog index ee7d03f635..72d7fbcd6b 100644 --- a/cpukit/score/cpu/m68k/ChangeLog +++ b/cpukit/score/cpu/m68k/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-08 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16, unsigned32. diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h index 5857a772aa..4ae760d5af 100644 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h @@ -6,7 +6,7 @@ * This include file contains information pertaining to the Motorola * m68xxx processor family. * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -672,7 +672,7 @@ void _CPU_Context_restore_fp( * compliant with IEEE floating-point standards." * * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and - * is invoked early in the application code to insure that proper FP + * is invoked early in the application code to ensure that proper FP * behavior is installed. This is not left to the BSP to call, since * this would force all applications using that BSP to use FPSP which * is not necessarily desirable. diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index 841af237d8..09f6d4331d 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-18 Joel Sherrill * rtems/score/cpu.h: Eliminate use of unsigned32. diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index ad40cbaf4f..219047a098 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -26,7 +26,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * COPYRIGHT (c) 1989-2001. + * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -146,8 +146,7 @@ extern "C" { * If TRUE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization. * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. */ #define CPU_ALLOCATE_INTERRUPT_STACK FALSE @@ -695,7 +694,7 @@ extern unsigned int mips_interrupt_number_of_vectors; #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) /* - * Should be large enough to run all RTEMS tests. This insures + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. */ @@ -1174,7 +1173,7 @@ void _CPU_Context_restore_fp( * Some CPUs have special instructions which swap a 32-bit quantity in * a single instruction (e.g. i486). It is probably best to avoid * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that + * that interrupts would probably have to be disabled to ensure that * an interrupt does not try to access the same "chunk" with the wrong * endian. Another good reason is that on some CPUs, the endian bit * endianness for ALL fetches -- both code and data -- so the code diff --git a/cpukit/score/cpu/sh/ChangeLog b/cpukit/score/cpu/sh/ChangeLog index 425ec1d643..2f04171755 100644 --- a/cpukit/score/cpu/sh/ChangeLog +++ b/cpukit/score/cpu/sh/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2006-01-11 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16. diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h index 3f49e5791c..b3da785134 100644 --- a/cpukit/score/cpu/sh/rtems/score/cpu.h +++ b/cpukit/score/cpu/sh/rtems/score/cpu.h @@ -16,7 +16,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * * - * COPYRIGHT (c) 1998-2001. + * COPYRIGHT (c) 1998-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -499,7 +499,7 @@ SCORE_EXTERN void CPU_delay( uint32_t microseconds ); #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE /* - * Should be large enough to run all RTEMS tests. This insures + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. * * We have been able to run the sptests with this value, but have not diff --git a/cpukit/score/cpu/sparc/ChangeLog b/cpukit/score/cpu/sparc/ChangeLog index a12d83e02a..3cad2c9cfa 100644 --- a/cpukit/score/cpu/sparc/ChangeLog +++ b/cpukit/score/cpu/sparc/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-08 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16, unsigned32. diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index cf2cfcebd8..27ea69f0b1 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -6,7 +6,7 @@ * This include file contains information pertaining to the port of * the executive to the SPARC processor. * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -638,7 +638,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template; #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE /* - * Should be large enough to run all tests. This insures + * Should be large enough to run all tests. This ensures * that a "reasonable" small application should not have any problems. * * This appears to be a fairly generous number for the SPARC since diff --git a/cpukit/score/cpu/unix/ChangeLog b/cpukit/score/cpu/unix/ChangeLog index b41d0ba0e9..e975f30fa6 100644 --- a/cpukit/score/cpu/unix/ChangeLog +++ b/cpukit/score/cpu/unix/ChangeLog @@ -1,3 +1,9 @@ +2006-01-16 Joel Sherrill + + * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. + As a side-effect, grammar and spelling errors were corrected, spacing + errors were address, and some variable names were improved. + 2005-11-08 Ralf Corsepius * rtems/score/types.h: Eliminate unsigned16, unsigned32. diff --git a/cpukit/score/cpu/unix/rtems/score/cpu.h b/cpukit/score/cpu/unix/rtems/score/cpu.h index ff45eec8bc..f2058fc655 100644 --- a/cpukit/score/cpu/unix/rtems/score/cpu.h +++ b/cpukit/score/cpu/unix/rtems/score/cpu.h @@ -12,6 +12,13 @@ * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * + * COPYRIGHT (c) 1989-2006. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * * $Id$ */ @@ -121,8 +128,7 @@ extern "C" { * If TRUE, then the memory is allocated during initialization. * If FALSE, then the memory is allocated during initialization. * - * This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. */ #define CPU_ALLOCATE_INTERRUPT_STACK FALSE @@ -608,7 +614,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE /* - * Should be large enough to run all RTEMS tests. This insures + * Should be large enough to run all RTEMS tests. This ensures * that a "reasonable" small application should not have any problems. */ @@ -1008,7 +1014,7 @@ void _CPU_Fatal_error( * Some CPUs have special instructions which swap a 32-bit quantity in * a single instruction (e.g. i486). It is probably best to avoid * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that + * that interrupts would probably have to be disabled to ensure that * an interrupt does not try to access the same "chunk" with the wrong * endian. Another good reason is that on some CPUs, the endian bit * endianness for ALL fetches -- both code and data -- so the code -- cgit v1.2.3