From de62e5d861f41f7f8898ed7c8fbe9ee1201af880 Mon Sep 17 00:00:00 2001 From: Hesham ALMatary Date: Mon, 18 Aug 2014 16:06:46 -0500 Subject: Add or1k tick timer register definitions --- cpukit/score/cpu/or1k/rtems/score/or1k-utility.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h index 74c14d7fd9..6b238b1641 100644 --- a/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h +++ b/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @@ -258,7 +258,21 @@ /*Context ID (Fast Context Switching) */ #define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) +/* Tick timer configuration bits */ +#define CPU_OR1K_SPR_TTMR_SHAMT_IP 28 +#define CPU_OR1K_SPR_TTMR_SHAMT_IE 29 +#define CPU_OR1K_SPR_TTMR_SHAMT_MODE 30 + +#define CPU_OR1K_SPR_TTMR_TP_MASK (0x0FFFFFFF) +#define CPU_OR1K_SPR_TTMR_IP (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP) +#define CPU_OR1K_SPR_TTMR_IE (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE) +#define CPU_OR1K_SPR_TTMR_MODE_RESTART (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) +#define CPU_OR1K_SPR_TTMR_MODE_CONT (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) + /* Power management register bits */ + +/* Shift amount macros for bit positions in Power Management register */ #define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 #define CPU_OR1K_SPR_PMR_SHAMT_DME 4 #define CPU_OR1K_SPR_PMR_SHAMT_SME 5 @@ -271,8 +285,6 @@ #define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) #define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) -/* Shift amount macros for bit positions in Power Management register */ - #ifndef ASM #include -- cgit v1.2.3