From cb2b8f02dd701389084a23188705ef393ef609db Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 26 Jun 2015 21:39:16 +0200 Subject: doc: Fix interrupt level ARM documentation --- doc/cpu_supplement/arm.t | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/doc/cpu_supplement/arm.t b/doc/cpu_supplement/arm.t index 88693aa213..304e1e1f0a 100644 --- a/doc/cpu_supplement/arm.t +++ b/doc/cpu_supplement/arm.t @@ -152,10 +152,9 @@ confusion. @subsection Interrupt Levels -The RTEMS interrupt level mapping scheme for the ARM is not a numeric level as -on most RTEMS ports. It is a bit mapping that corresponds the enable bit -postions in the Current Program Status Register (CPSR). There are only two -levels: IRQ enabled and IRQ disabled. +There are exactly two interrupt levels on ARM with respect to RTEMS. Level +zero corresponds to interrupts enabled. Level one corresponds to interrupts +disabled. @subsection Interrupt Stack -- cgit v1.2.3