From c4905d8d314f4325b18e4dbbd6cbfc5b0f75f313 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Sat, 10 Mar 2018 10:17:35 +0100 Subject: bsps/arm: Move libcpu content to bsps This patch is a part of the BSP source reorganization. Update #3285. --- bsps/arm/shared/cp15/arm920-mmu.c | 137 +++++++++++++++++++++ c/src/lib/libbsp/arm/csb336/Makefile.am | 2 +- c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg | 1 - c/src/lib/libbsp/arm/csb337/Makefile.am | 2 +- c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg | 1 - .../lib/libbsp/arm/edb7312/make/custom/edb7312.cfg | 3 +- c/src/lib/libbsp/arm/gdbarmsim/Makefile.am | 5 - .../arm/gdbarmsim/make/custom/arm1136jfs.cfg | 1 - .../libbsp/arm/gdbarmsim/make/custom/arm1136js.cfg | 1 - .../libbsp/arm/gdbarmsim/make/custom/arm7tdmi.cfg | 1 - .../libbsp/arm/gdbarmsim/make/custom/arm920.cfg | 1 - .../arm/gdbarmsim/make/custom/armcortexa9.cfg | 1 - c/src/lib/libbsp/arm/gumstix/Makefile.am | 2 +- .../lib/libbsp/arm/gumstix/make/custom/gumstix.cfg | 1 - c/src/lib/libbsp/arm/smdk2410/Makefile.am | 2 +- .../libbsp/arm/smdk2410/make/custom/smdk2410.cfg | 1 - c/src/lib/libcpu/arm/Makefile.am | 19 --- c/src/lib/libcpu/arm/configure.ac | 32 ----- c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S | 57 --------- c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c | 65 ---------- c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S | 31 ----- c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c | 40 ------ c/src/lib/libcpu/arm/shared/arm920/mmu.c | 137 --------------------- 23 files changed, 142 insertions(+), 401 deletions(-) create mode 100644 bsps/arm/shared/cp15/arm920-mmu.c delete mode 100644 c/src/lib/libcpu/arm/Makefile.am delete mode 100644 c/src/lib/libcpu/arm/configure.ac delete mode 100644 c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S delete mode 100644 c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c delete mode 100644 c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S delete mode 100644 c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c delete mode 100644 c/src/lib/libcpu/arm/shared/arm920/mmu.c diff --git a/bsps/arm/shared/cp15/arm920-mmu.c b/bsps/arm/shared/cp15/arm920-mmu.c new file mode 100644 index 0000000000..b76daa6c7a --- /dev/null +++ b/bsps/arm/shared/cp15/arm920-mmu.c @@ -0,0 +1,137 @@ +/* + * ARM920 MMU functions + */ + +/* + * Copyright (c) 2004 by Cogent Computer Systems + * Written by Jay Monkman + */ + +#include +#include + +typedef uint32_t mmu_lvl1_t; + +extern uint32_t _ttbl_base; + +static void mmu_set_map_inval(mmu_lvl1_t *base); + +#define MMU_CTRL_MMU_EN (1 << 0) +#define MMU_CTRL_ALIGN_FAULT_EN (1 << 1) +#define MMU_CTRL_D_CACHE_EN (1 << 2) +#define MMU_CTRL_DEFAULT (0xf << 3) +#define MMU_CTRL_LITTLE_ENDIAN (0 << 7) +#define MMU_CTRL_BIG_ENDIAN (1 << 7) +#define MMU_CTRL_SYS_PROT (1 << 8) +#define MMU_CTRL_ROM_PROT (1 << 9) +#define MMU_CTRL_I_CACHE_EN (1 << 12) +#define MMU_CTRL_LOW_VECT (0 << 13) +#define MMU_CTRL_HIGH_VECT (1 << 13) + + +#define MMU_SET_LVL1_SECT(addr, ap, dom, ce, be) \ + (((addr) & 0xfff00000) | \ + (ap) | \ + (dom) | \ + ((ce) << 3) | \ + ((be) << 2) | \ + 0x12) + +#define MMU_SET_LVL1_INVAL (0x0) + +#define MMU_SECT_AP_ALL (0x3 << 10) + +void mmu_init(mmu_sect_map_t *map) +{ + mmu_lvl1_t *lvl1_base; + int i; + + /* flush the cache and TLB */ + arm_cp15_cache_invalidate(); + arm_cp15_tlb_invalidate(); + + /* set manage mode access for all domains */ + arm_cp15_set_domain_access_control(0xffffffff); + + lvl1_base = (mmu_lvl1_t *)&_ttbl_base; + + /* set up the trans table */ + mmu_set_map_inval(lvl1_base); + arm_cp15_set_translation_table_base(lvl1_base); + + /* create a 1:1 mapping of the entire address space */ + i = 0; + while(map[i].size != 0) { + int c = 0; /* to avoid uninitialized warnings */ + int b = 0; /* to avoid uninitialized warnings */ + int pbase; + int vbase; + int sects; + + switch (map[i].cache_flags) { + case MMU_CACHE_NONE: + c = 0; + b = 0; + break; + case MMU_CACHE_BUFFERED: + c = 0; + b = 1; + break; + case MMU_CACHE_WTHROUGH: + c = 1; + b = 0; + break; + case MMU_CACHE_WBACK: + c = 1; + b = 1; + break; + } + + pbase = (map[i].paddr & 0xfff00000) >> 20; + vbase = (map[i].vaddr & 0xfff00000) >> 20; + sects = map[i].size; + + while (sects > 0) { + lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20, + MMU_SECT_AP_ALL, + 0, + c, + b); + pbase++; + vbase++; + sects--; + } + i++; + } + + /* flush the cache and TLB */ + arm_cp15_cache_invalidate(); + arm_cp15_tlb_invalidate(); + + /* I & D caches turned on */ + arm_cp15_set_control(MMU_CTRL_DEFAULT | + MMU_CTRL_D_CACHE_EN | + MMU_CTRL_I_CACHE_EN | + MMU_CTRL_ALIGN_FAULT_EN | + MMU_CTRL_LITTLE_ENDIAN | + MMU_CTRL_MMU_EN); + + return; +} + +/* set all the level 1 entrys to be invalid descriptors */ +static void mmu_set_map_inval(mmu_lvl1_t *base) +{ + int i; + for (i = 0; i < (0x4000 / 4); i++) { + base[i] = MMU_SET_LVL1_INVAL; + } +} + +void mmu_set_cpu_async_mode(void) +{ + uint32_t reg; + reg = arm_cp15_get_control(); + reg |= 0xc0000000; + arm_cp15_set_control(reg); +} diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am b/c/src/lib/libbsp/arm/csb336/Makefile.am index 8bc5a44f23..6f65d36398 100644 --- a/c/src/lib/libbsp/arm/csb336/Makefile.am +++ b/c/src/lib/libbsp/arm/csb336/Makefile.am @@ -50,7 +50,7 @@ libbsp_a_SOURCES += network/lan91c11x.c libbsp_a_SOURCES += network/network.c endif -libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel +libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cp15/arm920-mmu.c include $(top_srcdir)/../../../../automake/local.am include $(srcdir)/../../../../../../bsps/arm/csb336/headers.am diff --git a/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg b/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg index bc2f65cc9c..d38e2e10b8 100644 --- a/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg +++ b/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=shared # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/csb337/Makefile.am b/c/src/lib/libbsp/arm/csb337/Makefile.am index 69780d18a5..d7527a0a36 100644 --- a/c/src/lib/libbsp/arm/csb337/Makefile.am +++ b/c/src/lib/libbsp/arm/csb337/Makefile.am @@ -80,7 +80,7 @@ if HAS_NETWORKING libbsp_a_SOURCES += network/network.c endif -libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel +libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cp15/arm920-mmu.c include $(top_srcdir)/../../../../automake/local.am include $(srcdir)/../../../../../../bsps/arm/csb337/headers.am diff --git a/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg b/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg index 56e2d7a116..97d9685c3d 100644 --- a/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg +++ b/c/src/lib/libbsp/arm/csb337/make/custom/csb337.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=shared # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/edb7312/make/custom/edb7312.cfg b/c/src/lib/libbsp/arm/edb7312/make/custom/edb7312.cfg index 832f47bdde..32dd537872 100644 --- a/c/src/lib/libbsp/arm/edb7312/make/custom/edb7312.cfg +++ b/c/src/lib/libbsp/arm/edb7312/make/custom/edb7312.cfg @@ -5,12 +5,11 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=arm7tdmi # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. # -CPU_CFLAGS = -mcpu=$(RTEMS_CPU_MODEL) +CPU_CFLAGS = -mcpu=arm7tdmi # optimize flag: typically -O2 CFLAGS_OPTIMIZE_V = -O2 -g diff --git a/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am b/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am index 62cbdccb8b..f9a47f4b23 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am +++ b/c/src/lib/libbsp/arm/gdbarmsim/Makefile.am @@ -52,11 +52,6 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c # Cache libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c -#libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \ -# ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/clock.rel \ -# ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel \ -# ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq.rel - # Shared if shared libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs.cfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs.cfg index a802a8ffdc..be4d5a6484 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs.cfg +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136jfs.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=arm1136 # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js.cfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js.cfg index 7ae3e6bb71..83308c39b0 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js.cfg +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm1136js.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=arm1136 # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi.cfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi.cfg index 28a2e76460..e992733864 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi.cfg +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm7tdmi.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=arm7tdmi # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg index 72478f8d95..b246d5bb20 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/arm920.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=arm920 # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9.cfg b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9.cfg index 693eb9f762..6eecf70615 100644 --- a/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9.cfg +++ b/c/src/lib/libbsp/arm/gdbarmsim/make/custom/armcortexa9.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=arm1136 # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/gumstix/Makefile.am b/c/src/lib/libbsp/arm/gumstix/Makefile.am index cff8663382..2c282e798a 100644 --- a/c/src/lib/libbsp/arm/gumstix/Makefile.am +++ b/c/src/lib/libbsp/arm/gumstix/Makefile.am @@ -55,7 +55,7 @@ libbsp_a_SOURCES += rtl8019/rtl8019.c rtl8019/wd80x3.h endif endif -libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel +libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cp15/arm920-mmu.c include $(top_srcdir)/../../../../automake/local.am include $(srcdir)/../../../../../../bsps/arm/gumstix/headers.am diff --git a/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg b/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg index d42b44695b..664e42b365 100644 --- a/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg +++ b/c/src/lib/libbsp/arm/gumstix/make/custom/gumstix.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=shared # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libbsp/arm/smdk2410/Makefile.am b/c/src/lib/libbsp/arm/smdk2410/Makefile.am index a0922bd77f..01cddc925b 100644 --- a/c/src/lib/libbsp/arm/smdk2410/Makefile.am +++ b/c/src/lib/libbsp/arm/smdk2410/Makefile.am @@ -58,7 +58,7 @@ libbsp_a_SOURCES += smc/smc.h # Cache libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c -libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel +libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cp15/arm920-mmu.c include $(top_srcdir)/../../../../automake/local.am include $(srcdir)/../../../../../../bsps/arm/smdk2410/headers.am diff --git a/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg b/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg index fe532ceb4f..b5720cae3f 100644 --- a/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg +++ b/c/src/lib/libbsp/arm/smdk2410/make/custom/smdk2410.cfg @@ -5,7 +5,6 @@ include $(RTEMS_ROOT)/make/custom/default.cfg RTEMS_CPU=arm -RTEMS_CPU_MODEL=shared # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. diff --git a/c/src/lib/libcpu/arm/Makefile.am b/c/src/lib/libcpu/arm/Makefile.am deleted file mode 100644 index 35b08e2495..0000000000 --- a/c/src/lib/libcpu/arm/Makefile.am +++ /dev/null @@ -1,19 +0,0 @@ -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/compile.am - -EXTRA_DIST = - -noinst_PROGRAMS = - -## shared/include -if shared - -## shared/arm920 -noinst_PROGRAMS += shared/arm920.rel -shared_arm920_rel_SOURCES = shared/arm920/mmu.c -shared_arm920_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/src -shared_arm920_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -endif - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/lib/libcpu/arm/configure.ac b/c/src/lib/libcpu/arm/configure.ac deleted file mode 100644 index a5e3e1cc88..0000000000 --- a/c/src/lib/libcpu/arm/configure.ac +++ /dev/null @@ -1,32 +0,0 @@ -## Process this file with autoconf to produce a configure script. - -AC_PREREQ([2.69]) -AC_INIT([rtems-c-src-lib-libcpu-arm],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) -AC_CONFIG_SRCDIR([shared]) -RTEMS_TOP([../../../../..],[../../..]) -RTEMS_SOURCE_TOP -RTEMS_BUILD_TOP - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSBSP - -RTEMS_PROJECT_ROOT - -RTEMS_PROG_CC_FOR_TARGET -AM_PROG_CC_C_O -RTEMS_CANONICALIZE_TOOLS -RTEMS_PROG_CCAS - -AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "arm1136" || \ - test "$RTEMS_CPU_MODEL" = "shared") - -RTEMS_AMPOLISH3 - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile -]) -AC_OUTPUT diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S b/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S deleted file mode 100644 index 4aa7ea4698..0000000000 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S +++ /dev/null @@ -1,57 +0,0 @@ -/* - * LPC22XX/LPC21xx Intererrupt handler - * - * Modified by Ray 2006 from Jay Monkman's code - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#define __asm__ - -/* - * BSP specific interrupt handler for INT or FIQ. In here - * you do determine which interrupt happened and call its - * handler. - * Called from ISR_Handler, It is better to write in C function - */ - .globl bsp_interrupt_dispatch -bsp_interrupt_dispatch : -#ifdef __thumb__ - .code 16 -#endif - -/* - * Look at interrupt status register to determine source. - * From source, determine offset into expanded vector table - * and load handler address into r0. - */ - - ldr r0, =0xFFFFF030 /* Read the vector number */ - ldr r0, [r0] -#ifdef __thumb__ - push {lr} - ldr r2, =IRQ_return /* prepare the return from handler */ - mov lr, r2 -#else - stmdb sp!,{lr} - ldr lr, =IRQ_return /* prepare the return from handler */ -#endif - - - /*C code will be called*/ - mov pc, r0 /* EXECUTE INT HANDLER */ - - /* - * C code may come back from Thumb if --thumb-interwork flag is False - * Add some veneer to make sure that code back to ARM - */ -IRQ_return: -#ifdef __thumb__ - pop {r1} - bx r1 -#else - ldmia sp!,{r1} - mov pc, r1 -#endif - diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c deleted file mode 100644 index ae933f76d2..0000000000 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * NXP/Philips LPC22XX/LPC21xx Interrupt handler - * Ray 2007 to support LPC ARM - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#include -#include -#include - - -/* - * Interrupt system initialization. Disable interrupts, clear - * any that are pending. - */ -void BSP_rtems_irq_mngt_init(void) -{ - long *vectorTable; - int i; - - /* disable all interrupts */ - VICIntEnClr = 0xFFFFFFFF; - - vectorTable = (long *) VECTOR_TABLE; - /* Initialize the vector table contents with default handler */ - for (i=0; i - * Copyright (c) 2004 by Jay Monkman - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#define __asm__ - - .globl bsp_interrupt_dispatch -bsp_interrupt_dispatch : -/* - * Look at interrupt status register to determine source. - * From source, determine offset into expanded vector table - * and load vector into r0 and handler address into r1. - */ - ldr r0,=0x40d00000 - ldr r1,[r0] - clz r0,r1 - cmp r0,#32 - moveq pc,lr /*All zeros*/ - mov r2,#31 - sub r0,r2,r0 - ldr r2,=IRQ_table - add r2,r2,r0,LSL #2 - ldr r1,[r2] - mov pc,r1 - - diff --git a/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c b/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c deleted file mode 100644 index aeabc1f145..0000000000 --- a/c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * PXA255 interrupt controller by Yang Xi - * Copyright (c) 2004 by Jay Monkman - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include - -void dummy_handler(rtems_irq_hdl_param unused) -{ - printk("I am dummy handler\n"); -} - -void (*IRQ_table[PRIMARY_IRQS])(rtems_irq_hdl_param param); - -/* - * Interrupt system initialization. Disable interrupts, clear - * any that are pending. - */ -void BSP_rtems_irq_mngt_init(void) -{ - int i; - - /* Initialize the vector table contents with default handler */ - for (i=0; i - */ - -#include -#include - -typedef uint32_t mmu_lvl1_t; - -extern uint32_t _ttbl_base; - -static void mmu_set_map_inval(mmu_lvl1_t *base); - -#define MMU_CTRL_MMU_EN (1 << 0) -#define MMU_CTRL_ALIGN_FAULT_EN (1 << 1) -#define MMU_CTRL_D_CACHE_EN (1 << 2) -#define MMU_CTRL_DEFAULT (0xf << 3) -#define MMU_CTRL_LITTLE_ENDIAN (0 << 7) -#define MMU_CTRL_BIG_ENDIAN (1 << 7) -#define MMU_CTRL_SYS_PROT (1 << 8) -#define MMU_CTRL_ROM_PROT (1 << 9) -#define MMU_CTRL_I_CACHE_EN (1 << 12) -#define MMU_CTRL_LOW_VECT (0 << 13) -#define MMU_CTRL_HIGH_VECT (1 << 13) - - -#define MMU_SET_LVL1_SECT(addr, ap, dom, ce, be) \ - (((addr) & 0xfff00000) | \ - (ap) | \ - (dom) | \ - ((ce) << 3) | \ - ((be) << 2) | \ - 0x12) - -#define MMU_SET_LVL1_INVAL (0x0) - -#define MMU_SECT_AP_ALL (0x3 << 10) - -void mmu_init(mmu_sect_map_t *map) -{ - mmu_lvl1_t *lvl1_base; - int i; - - /* flush the cache and TLB */ - arm_cp15_cache_invalidate(); - arm_cp15_tlb_invalidate(); - - /* set manage mode access for all domains */ - arm_cp15_set_domain_access_control(0xffffffff); - - lvl1_base = (mmu_lvl1_t *)&_ttbl_base; - - /* set up the trans table */ - mmu_set_map_inval(lvl1_base); - arm_cp15_set_translation_table_base(lvl1_base); - - /* create a 1:1 mapping of the entire address space */ - i = 0; - while(map[i].size != 0) { - int c = 0; /* to avoid uninitialized warnings */ - int b = 0; /* to avoid uninitialized warnings */ - int pbase; - int vbase; - int sects; - - switch (map[i].cache_flags) { - case MMU_CACHE_NONE: - c = 0; - b = 0; - break; - case MMU_CACHE_BUFFERED: - c = 0; - b = 1; - break; - case MMU_CACHE_WTHROUGH: - c = 1; - b = 0; - break; - case MMU_CACHE_WBACK: - c = 1; - b = 1; - break; - } - - pbase = (map[i].paddr & 0xfff00000) >> 20; - vbase = (map[i].vaddr & 0xfff00000) >> 20; - sects = map[i].size; - - while (sects > 0) { - lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20, - MMU_SECT_AP_ALL, - 0, - c, - b); - pbase++; - vbase++; - sects--; - } - i++; - } - - /* flush the cache and TLB */ - arm_cp15_cache_invalidate(); - arm_cp15_tlb_invalidate(); - - /* I & D caches turned on */ - arm_cp15_set_control(MMU_CTRL_DEFAULT | - MMU_CTRL_D_CACHE_EN | - MMU_CTRL_I_CACHE_EN | - MMU_CTRL_ALIGN_FAULT_EN | - MMU_CTRL_LITTLE_ENDIAN | - MMU_CTRL_MMU_EN); - - return; -} - -/* set all the level 1 entrys to be invalid descriptors */ -static void mmu_set_map_inval(mmu_lvl1_t *base) -{ - int i; - for (i = 0; i < (0x4000 / 4); i++) { - base[i] = MMU_SET_LVL1_INVAL; - } -} - -void mmu_set_cpu_async_mode(void) -{ - uint32_t reg; - reg = arm_cp15_get_control(); - reg |= 0xc0000000; - arm_cp15_set_control(reg); -} -- cgit v1.2.3