From affc8de85f951768b2fa6fb46f154f738f5a0150 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 4 Jan 2021 18:58:24 +0100 Subject: bsp/stm32h7: Split start configuration This allows applications to individually provide configuration structures. Update #4209. --- bsps/arm/stm32h7/start/stm32h7-config-clk.c | 45 +++++++++++++ bsps/arm/stm32h7/start/stm32h7-config-fls.c | 34 ++++++++++ bsps/arm/stm32h7/start/stm32h7-config-osc.c | 52 +++++++++++++++ bsps/arm/stm32h7/start/stm32h7-config-per.c | 62 +++++++++++++++++ bsps/arm/stm32h7/start/stm32h7-config-pwr.c | 35 ++++++++++ bsps/arm/stm32h7/start/stm32h7-config.c | 100 ---------------------------- spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 6 +- 7 files changed, 233 insertions(+), 101 deletions(-) create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-clk.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-fls.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-osc.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-per.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-pwr.c delete mode 100644 bsps/arm/stm32h7/start/stm32h7-config.c diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c new file mode 100644 index 0000000000..3e7c930201 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-clk.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const RCC_ClkInitTypeDef stm32h7_config_clocks = { + .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, + .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, + .SYSCLKDivider = RCC_SYSCLK_DIV1, + .AHBCLKDivider = RCC_HCLK_DIV2, + .APB3CLKDivider = RCC_APB3_DIV2, + .APB1CLKDivider = RCC_APB1_DIV2, + .APB2CLKDivider = RCC_APB2_DIV2, + .APB4CLKDivider = RCC_APB4_DIV2 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-fls.c b/bsps/arm/stm32h7/start/stm32h7-config-fls.c new file mode 100644 index 0000000000..f2d10d2410 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-fls.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-osc.c b/bsps/arm/stm32h7/start/stm32h7-config-osc.c new file mode 100644 index 0000000000..b639c7ca36 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-osc.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const RCC_OscInitTypeDef stm32h7_config_oscillator = { + .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, + .HSEState = RCC_HSE_ON, + .LSEState = RCC_LSE_ON, + .HSIState = RCC_HSI_DIV1, + .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT, + .HSI48State = RCC_HSI48_ON, + .PLL.PLLState = RCC_PLL_ON, + .PLL.PLLSource = RCC_PLLSOURCE_HSE, + .PLL.PLLM = 5, + .PLL.PLLN = 192, + .PLL.PLLP = 2, + .PLL.PLLQ = 12, + .PLL.PLLR = 2, + .PLL.PLLRGE = RCC_PLL1VCIRANGE_2, + .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, + .PLL.PLLFRACN = 0 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-per.c b/bsps/arm/stm32h7/start/stm32h7-config-per.c new file mode 100644 index 0000000000..79aa1494dd --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-per.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { + .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 + | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, + .PLL2.PLL2M = 3, + .PLL2.PLL2N = 48, + .PLL2.PLL2P = 1, + .PLL2.PLL2Q = 2, + .PLL2.PLL2R = 2, + .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, + .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, + .PLL2.PLL2FRACN = 0, + .PLL3.PLL3M = 25, + .PLL3.PLL3N = 192, + .PLL3.PLL3P = 2, + .PLL3.PLL3Q = 4, + .PLL3.PLL3R = 2, + .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, + .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, + .PLL3.PLL3FRACN = 0, + .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, + .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, + .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, + .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, + .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, + .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, + .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, + .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-pwr.c b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c new file mode 100644 index 0000000000..3fcdeba2e8 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +const uint32_t stm32h7_config_pwr_regulator_voltagescaling = + PWR_REGULATOR_VOLTAGE_SCALE0; diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c deleted file mode 100644 index 874ad047db..0000000000 --- a/bsps/arm/stm32h7/start/stm32h7-config.c +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include - -const uint32_t stm32h7_config_pwr_regulator_voltagescaling = - PWR_REGULATOR_VOLTAGE_SCALE0; - -const RCC_OscInitTypeDef stm32h7_config_oscillator = { - .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, - .HSEState = RCC_HSE_ON, - .LSEState = RCC_LSE_ON, - .HSIState = RCC_HSI_DIV1, - .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT, - .HSI48State = RCC_HSI48_ON, - .PLL.PLLState = RCC_PLL_ON, - .PLL.PLLSource = RCC_PLLSOURCE_HSE, - .PLL.PLLM = 5, - .PLL.PLLN = 192, - .PLL.PLLP = 2, - .PLL.PLLQ = 12, - .PLL.PLLR = 2, - .PLL.PLLRGE = RCC_PLL1VCIRANGE_2, - .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, - .PLL.PLLFRACN = 0 -}; - -const RCC_ClkInitTypeDef stm32h7_config_clocks = { - .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, - .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, - .SYSCLKDivider = RCC_SYSCLK_DIV1, - .AHBCLKDivider = RCC_HCLK_DIV2, - .APB3CLKDivider = RCC_APB3_DIV2, - .APB1CLKDivider = RCC_APB1_DIV2, - .APB2CLKDivider = RCC_APB2_DIV2, - .APB4CLKDivider = RCC_APB4_DIV2 -}; - -const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; - -const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { - .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 - | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 - | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, - .PLL2.PLL2M = 3, - .PLL2.PLL2N = 48, - .PLL2.PLL2P = 1, - .PLL2.PLL2Q = 2, - .PLL2.PLL2R = 2, - .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, - .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, - .PLL2.PLL2FRACN = 0, - .PLL3.PLL3M = 25, - .PLL3.PLL3N = 192, - .PLL3.PLL3P = 2, - .PLL3.PLL3Q = 4, - .PLL3.PLL3R = 2, - .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, - .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, - .PLL3.PLL3FRACN = 0, - .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, - .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, - .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, - .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, - .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, - .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, - .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, - .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 -}; diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml index 835247316c..6424de3c3f 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -398,7 +398,11 @@ source: - bsps/arm/stm32h7/start/ext-mem-ctl.c - bsps/arm/stm32h7/start/getentropy-rng.c - bsps/arm/stm32h7/start/mpu-config.c -- bsps/arm/stm32h7/start/stm32h7-config.c +- bsps/arm/stm32h7/start/stm32h7-config-clk.c +- bsps/arm/stm32h7/start/stm32h7-config-fls.c +- bsps/arm/stm32h7/start/stm32h7-config-osc.c +- bsps/arm/stm32h7/start/stm32h7-config-per.c +- bsps/arm/stm32h7/start/stm32h7-config-pwr.c - bsps/arm/stm32h7/start/stm32h7-hal.c - bsps/arm/stm32h7/start/stm32h7-hal-eth.c - bsps/arm/stm32h7/start/stm32h7-hal-uart.c -- cgit v1.2.3