From a4d97d942b6e13cdd83e69308741f730091c13a1 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 18 Sep 1996 20:45:27 +0000 Subject: new files submitted by Craig Lebakken (lebakken@minn.net) and Derrick Ostertag (ostertag@transition.com). --- c/src/exec/score/cpu/a29k/a29k.h | 75 +++ c/src/exec/score/cpu/a29k/a29ktypes.h | 57 ++ c/src/exec/score/cpu/a29k/amd.ah | 531 +++++++++++++++++++ c/src/exec/score/cpu/a29k/asm.h | 98 ++++ c/src/exec/score/cpu/a29k/cpu.c | 256 +++++++++ c/src/exec/score/cpu/a29k/cpu.h | 953 ++++++++++++++++++++++++++++++++++ c/src/exec/score/cpu/a29k/cpu_asm.h | 71 +++ c/src/exec/score/cpu/a29k/cpu_asm.s | 476 +++++++++++++++++ c/src/exec/score/cpu/a29k/pswmacro.ah | 442 ++++++++++++++++ c/src/exec/score/cpu/a29k/rtems.c | 48 ++ cpukit/score/cpu/a29k/amd.ah | 531 +++++++++++++++++++ cpukit/score/cpu/a29k/asm.h | 98 ++++ cpukit/score/cpu/a29k/cpu.c | 256 +++++++++ cpukit/score/cpu/a29k/pswmacro.ah | 442 ++++++++++++++++ 14 files changed, 4334 insertions(+) create mode 100644 c/src/exec/score/cpu/a29k/a29k.h create mode 100644 c/src/exec/score/cpu/a29k/a29ktypes.h create mode 100644 c/src/exec/score/cpu/a29k/amd.ah create mode 100644 c/src/exec/score/cpu/a29k/asm.h create mode 100644 c/src/exec/score/cpu/a29k/cpu.c create mode 100644 c/src/exec/score/cpu/a29k/cpu.h create mode 100644 c/src/exec/score/cpu/a29k/cpu_asm.h create mode 100644 c/src/exec/score/cpu/a29k/cpu_asm.s create mode 100644 c/src/exec/score/cpu/a29k/pswmacro.ah create mode 100644 c/src/exec/score/cpu/a29k/rtems.c create mode 100644 cpukit/score/cpu/a29k/amd.ah create mode 100644 cpukit/score/cpu/a29k/asm.h create mode 100644 cpukit/score/cpu/a29k/cpu.c create mode 100644 cpukit/score/cpu/a29k/pswmacro.ah diff --git a/c/src/exec/score/cpu/a29k/a29k.h b/c/src/exec/score/cpu/a29k/a29k.h new file mode 100644 index 0000000000..c2fa60cd08 --- /dev/null +++ b/c/src/exec/score/cpu/a29k/a29k.h @@ -0,0 +1,75 @@ +/* a29k.h + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + * + */ +/* @(#)a29k.h 09/12/96 1.2 */ + +#ifndef _INCLUDE_A29K_h +#define _INCLUDE_A29K_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The following define the CPU Family and Model within the family + * + * NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced + * with the name of the appropriate macro for this target CPU. + */ + +#ifdef a29k +#undef a29k +#endif +#define a29k + +#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL +#undef REPLACE_THIS_WITH_THE_CPU_MODEL +#endif +#define REPLACE_THIS_WITH_THE_CPU_MODEL + +#ifdef REPLACE_THIS_WITH_THE_BSP +#undef REPLACE_THIS_WITH_THE_BSP +#endif +#define REPLACE_THIS_WITH_THE_BSP + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "no cpu" + * family when executing in protected mode. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + */ + +#if defined(a29205) + +#define CPU_MODEL_NAME "a29205" +#define A29K_HAS_FPU 0 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "AMD 29K" + +#ifdef __cplusplus +} +#endif + +#endif /* ! _INCLUDE_A29K_h */ +/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/a29ktypes.h b/c/src/exec/score/cpu/a29k/a29ktypes.h new file mode 100644 index 0000000000..9909a4f699 --- /dev/null +++ b/c/src/exec/score/cpu/a29k/a29ktypes.h @@ -0,0 +1,57 @@ +/* no_cputypes.h + * + * This include file contains type definitions pertaining to the Intel + * no_cpu processor family. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __NO_CPU_TYPES_h +#define __NO_CPU_TYPES_h + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +typedef unsigned char unsigned8; /* unsigned 8-bit integer */ +typedef unsigned short unsigned16; /* unsigned 16-bit integer */ +typedef unsigned int unsigned32; /* unsigned 32-bit integer */ +typedef unsigned long unsigned64; /* unsigned 64-bit integer */ + +typedef unsigned16 Priority_Bit_map_control; + +typedef signed char signed8; /* 8-bit signed integer */ +typedef signed short signed16; /* 16-bit signed integer */ +typedef signed int signed32; /* 32-bit signed integer */ +typedef signed long signed64; /* 64 bit signed integer */ + +typedef unsigned32 boolean; /* Boolean value */ + +typedef float single_precision; /* single precision float */ +typedef double double_precision; /* double precision float */ + +typedef void no_cpu_isr; +typedef void ( *no_cpu_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif +/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/amd.ah b/c/src/exec/score/cpu/a29k/amd.ah new file mode 100644 index 0000000000..ceef89564a --- /dev/null +++ b/c/src/exec/score/cpu/a29k/amd.ah @@ -0,0 +1,531 @@ +; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Initialization values for registers after RESET +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +' /* $Id */ +;* File information and includes. + + .file "amd.ah" + .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI" + + + +; +;* AMD PROCESSOR SPECIFIC VALUES... +; + +; +;* Processor revision levels... +; + +; PRL values: 31-28 27-24 +; Am29000 0 x +; Am29005 1 x +; Am29050 2 x +; Am29035 3 x +; Am29030 4 x +; Am29200 5 x +; Am29205 5 1x +; Am29240 6 0 +; Manx 7 0 +; Cougar 8 0 + + + .equ AM29000_PRL, 0x00 + + .equ AM29005_PRL, 0x10 + + .equ AM29050_PRL, 0x20 + + .equ AM29035_PRL, 0x30 + + .equ AM29030_PRL, 0x40 + + .equ AM29200_PRL, 0x50 + + .equ AM29205_PRL, 0x58 + + .equ AM29240_PRL, 0x60 + + .equ AM29040_PRL, 0x70 + + .equ MANX_PRL, 0x70 + + .equ COUGAR_PRL, 0x80 + +; +;* data structures sizes. +; + .equ CFGINFO_SIZE, 16*4 + + .equ PGMINFO_SIZE, 16*4 + + .equ VARARGS_SPACE, 16*4 + + .equ WINDOWSIZE, 0x80 +; +;* Am29027 Mode registers +; + + .equ Am29027Mode1, 0x0fc00820 + + .equ Am29027Mode2, 0x00001375 + + + +;* Processor Based Equates and Defines + + .equ SIG_SYNC, -1 + + .equ ENABLE, (SM) + + .equ DISABLE, (ENABLE | DI | DA) + + .equ DISABLE_FZ, (FZ | ENABLE | DI | DA) + + .equ CLR_TRAP, (FZ | DA) + + .equ InitOPS, (TD | SM | (3< + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif +/* end of include file */ + + diff --git a/c/src/exec/score/cpu/a29k/cpu.c b/c/src/exec/score/cpu/a29k/cpu.c new file mode 100644 index 0000000000..4312e85035 --- /dev/null +++ b/c/src/exec/score/cpu/a29k/cpu.c @@ -0,0 +1,256 @@ +/* + * AMD 29K CPU Dependent Source + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ +#ifndef lint +static char _sccsid[] = "@(#)cpu.c 21 Aug 1996 1.6\n"; +#endif + +#include +#include +#include +#include +#include +#include + +void a29k_ISR_Handler(unsigned32 vector); + +/* _CPU_Initialize + * + * This routine performs processor dependent initialization. + * + * INPUT PARAMETERS: + * cpu_table - CPU table to initialize + * thread_dispatch - address of disptaching routine + */ + + +void _CPU_Initialize( + rtems_cpu_table *cpu_table, + void (*thread_dispatch)() /* ignored on this CPU */ +) +{ + unsigned int i; + /* + * The thread_dispatch argument is the address of the entry point + * for the routine called at the end of an ISR once it has been + * decided a context switch is necessary. On some compilation + * systems it is difficult to call a high-level language routine + * from assembly. This allows us to trick these systems. + * + * If you encounter this problem save the entry point in a CPU + * dependent variable. + */ + + _CPU_Thread_dispatch_pointer = thread_dispatch; + + /* + * If there is not an easy way to initialize the FP context + * during Context_Initialize, then it is usually easier to + * save an "uninitialized" FP context here and copy it to + * the task's during Context_Initialize. + */ + + /* FP context initialization support goes here */ + + _CPU_Table = *cpu_table; + + for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ ) + { + _ISR_Vector_table[i] = (proc_ptr)NULL; + } +} + +/*PAGE + * + * _CPU_ISR_Get_level + */ + +unsigned32 _CPU_ISR_Get_level( void ) +{ + /* + * This routine returns the current interrupt level. + */ + return 0; +} + +/*PAGE + * + * _CPU_ISR_install_raw_handler + */ + +extern void intr14( void ); +extern void intr3( void ); +extern void intr2( void ); + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + /* + * This is where we install the interrupt handler into the "raw" interrupt + * table used by the CPU to dispatch interrupt handlers. + */ + switch( vector ) + { + case 14: + _settrap( vector, intr14 ); + break; + case 3: + _settrap( vector, intr3 ); + break; + case 2: + _settrap( vector, intr2 ); + break; + default: + break; + } +} + + +/*PAGE + * + * _CPU_ISR_install_vector + * + * This kernel routine installs the RTEMS handler for the + * specified vector. + * + * Input parameters: + * vector - interrupt vector number + * old_handler - former ISR for this vector number + * new_handler - replacement ISR for this vector number + * + * Output parameters: NONE + * + */ + +void _CPU_ISR_install_vector( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + *old_handler = _ISR_Vector_table[ vector ]; + + /* + * If the interrupt vector table is a table of pointer to isr entry + * points, then we need to install the appropriate RTEMS interrupt + * handler for this vector number. + */ + + _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); + + /* + * We put the actual user ISR address in '_ISR_vector_table'. This will + * be used by the _ISR_Handler so the user gets control. + */ + + _ISR_Vector_table[ vector ] = new_handler; +} + +/*PAGE + * + * _CPU_Install_interrupt_stack + */ + +void _CPU_Install_interrupt_stack( void ) +{ +} + +/*PAGE + * + * _CPU_Internal_threads_Idle_thread_body + * + * NOTES: + * + * 1. This is the same as the regular CPU independent algorithm. + * + * 2. If you implement this using a "halt", "idle", or "shutdown" + * instruction, then don't forget to put it in an infinite loop. + * + * 3. Be warned. Some processors with onboard DMA have been known + * to stop the DMA if the CPU were put in IDLE mode. This might + * also be a problem with other on-chip peripherals. So use this + * hook with caution. + */ + +void _CPU_Internal_threads_Idle_thread_body( void ) +{ + + for( ; ; ) + { + } + /* insert your "halt" instruction here */ ; +} + +void a29k_fatal_error( unsigned32 error ) +{ + printf("\n\nfatal error %d, rebooting!!!\n",error ); + exit(error); +} + + /* + * This discussion ignores a lot of the ugly details in a real + * implementation such as saving enough registers/state to be + * able to do something real. Keep in mind that the goal is + * to invoke a user's ISR handler which is written in C and + * uses a certain set of registers. + * + * Also note that the exact order is to a large extent flexible. + * Hardware will dictate a sequence for a certain subset of + * _ISR_Handler while requirements for setting + */ + + /* + * At entry to "common" _ISR_Handler, the vector number must be + * available. On some CPUs the hardware puts either the vector + * number or the offset into the vector table for this ISR in a + * known place. If the hardware does not give us this information, + * then the assembly portion of RTEMS for this port will contain + * a set of distinct interrupt entry points which somehow place + * the vector number in a known place (which is safe if another + * interrupt nests this one) and branches to _ISR_Handler. + * + */ + +void a29k_ISR_Handler(unsigned32 vector) +{ + _ISR_Nest_level++; + _Thread_Dispatch_disable_level++; + if ( _ISR_Vector_table[ vector ] ) + (*_ISR_Vector_table[ vector ])( vector ); + --_Thread_Dispatch_disable_level; + --_ISR_Nest_level; + if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level && + (_Context_Switch_necessary || _ISR_Signals_to_thread_executing )) + _Thread_Dispatch(); + return; +} diff --git a/c/src/exec/score/cpu/a29k/cpu.h b/c/src/exec/score/cpu/a29k/cpu.h new file mode 100644 index 0000000000..17a7d718e6 --- /dev/null +++ b/c/src/exec/score/cpu/a29k/cpu.h @@ -0,0 +1,953 @@ +/* cpu.h + * + * This include file contains information pertaining to the AMD 29K + * processor. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ +/* @(#)cpu.h 09/06/96 1.10 */ + +#ifndef __CPU_h +#define __CPU_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* pick up machine definitions */ +#ifndef ASM +#include +#endif + +extern unsigned int a29k_disable( void ); +extern void a29k_enable( unsigned int cookie ); +extern void a29k_disable_sup( void ); +extern void a29k_enable_sup( void ); +extern void a29k_disable_all( void ); +extern void a29k_disable_all_sup( void ); +extern void a29k_enable_all( void ); +extern void a29k_enable_all_sup( void ); +extern void a29k_halt( void ); +extern void a29k_fatal_error( unsigned32 error ); +extern void a29k_as70( void ); +extern void a29k_super_mode( void ); +extern void a29k_context_switch_sup(void); +extern void a29k_context_restore_sup(void); +extern void a29k_context_save_sup(void); +extern void a29k_sigdfl_sup(void); + +/* conditional compilation parameters */ + +/* + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * Basically this is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * [NOTE: In general, the _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls _Thread_Enable_dispatch which in turns calls + * _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely.] + */ + +#define CPU_INLINE_ENABLE_DISPATCH TRUE + +/* + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + */ + +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE + +/* + * Does this CPU have hardware support for a dedicated interrupt stack? + * + * If TRUE, then it must be installed during initialization. + * If FALSE, then no installation is performed. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? + * + * If TRUE, then the memory is allocated during initialization. + * If FALSE, then the memory is allocated during initialization. + * + * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE + * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. + */ + +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * If there is a FP coprocessor such as the i387 or mc68881, then + * the answer is TRUE. + * + * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#if ( A29K_HAS_FPU == 1 ) +#define CPU_HARDWARE_FP TRUE +#else +#define CPU_HARDWARE_FP FALSE +#endif + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPU in which this option has been used is the + * HP PA-RISC. The HP C compiler and gcc both implicitly use the + * floating point registers to perform integer multiplies. If + * a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body + * must be provided and is the default IDLE thread body instead of + * _Internal_threads_Idle_thread_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * NOTE: Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + */ + +#define CPU_STRUCTURE_ALIGNMENT + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + */ + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +/* + * Processor defined structures + * + * Examples structures include the descriptor tables from the i386 + * and the processor control structure on the i960ca. + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +typedef struct { + unsigned32 signal; + unsigned32 gr1; + unsigned32 rab; + unsigned32 PC0; + unsigned32 PC1; + unsigned32 PC2; + unsigned32 CHA; + unsigned32 CHD; + unsigned32 CHC; + unsigned32 ALU; + unsigned32 OPS; + unsigned32 tav; + unsigned32 lr1; + unsigned32 rfb; + unsigned32 msp; + + unsigned32 FPStat0; + unsigned32 FPStat1; + unsigned32 FPStat2; + unsigned32 IPA; + unsigned32 IPB; + unsigned32 IPC; + unsigned32 Q; + + unsigned32 gr96; + unsigned32 gr97; + unsigned32 gr98; + unsigned32 gr99; + unsigned32 gr100; + unsigned32 gr101; + unsigned32 gr102; + unsigned32 gr103; + unsigned32 gr104; + unsigned32 gr105; + unsigned32 gr106; + unsigned32 gr107; + unsigned32 gr108; + unsigned32 gr109; + unsigned32 gr110; + unsigned32 gr111; + + unsigned32 gr112; + unsigned32 gr113; + unsigned32 gr114; + unsigned32 gr115; + + unsigned32 gr116; + unsigned32 gr117; + unsigned32 gr118; + unsigned32 gr119; + unsigned32 gr120; + unsigned32 gr121; + unsigned32 gr122; + unsigned32 gr123; + unsigned32 gr124; + + unsigned32 local_count; + + unsigned32 locals[128]; +} Context_Control; + +typedef struct { + double some_float_register; +} Context_Control_fp; + +typedef struct { + unsigned32 special_interrupt_register; +} CPU_Interrupt_frame; + + +/* + * The following table contains the information required to configure + * the XXX processor specific parameters. + * + * NOTE: The interrupt_stack_size field is required if + * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. + * + * The pretasking_hook, predriver_hook, and postdriver_hook, + * and the do_zero_of_workspace fields are required on ALL CPUs. + */ + +typedef struct { + void (*pretasking_hook)( void ); + void (*predriver_hook)( void ); + void (*postdriver_hook)( void ); + void (*idle_task)( void ); + boolean do_zero_of_workspace; + unsigned32 interrupt_stack_size; + unsigned32 extra_system_initialization_stack; + unsigned32 some_other_cpu_dependent_info; +} rtems_cpu_table; + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +EXTERN Context_Control_fp _CPU_Null_fp_context; + +/* + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * NOTE: These two variables are required if the macro + * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + */ + +EXTERN void *_CPU_Interrupt_stack_low; +EXTERN void *_CPU_Interrupt_stack_high; + +/* + * With some compilation systems, it is difficult if not impossible to + * call a high-level language routine from assembly language. This + * is especially true of commercial Ada compilers and name mangling + * C++ ones. This variable can be optionally defined by the CPU porter + * and contains the address of the routine _Thread_Dispatch. This + * can make it easier to invoke that routine at the end of the interrupt + * sequence (if a dispatch is necessary). + */ + +EXTERN void (*_CPU_Thread_dispatch_pointer)(); + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +/* XXX: if needed, put more variables here */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * system initialization thread. Remember that in a multiprocessor + * system the system intialization thread becomes the MP server thread. + */ + +#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + */ + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * Should be large enough to run all RTEMS tests. This insures + * that a "reasonable" small application should not have any problems. + */ + +#define CPU_STACK_MINIMUM_SIZE (8192) + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ + +#define CPU_ALIGNMENT 4 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT 0 + +/* ISR handler macros */ + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + */ + +#define _CPU_ISR_Disable( _isr_cookie ) \ + do{ _isr_cookie = a29k_disable(); }while(0) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _isr_cookie ) \ + do{ a29k_enable(_isr_cookie) ; }while(0) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _isr_cookie ) \ + do{ \ + _CPU_ISR_Enable( _isr_cookie ); \ + _CPU_ISR_Disable( _isr_cookie ); \ + }while(0) + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + */ + +#define _CPU_ISR_Set_level( new_level ) \ + do{ \ + if ( new_level ) a29k_disable_all(); \ + else a29k_enable_all(); \ + }while(0); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +extern void _CPU_Context_save( + Context_Control *new_context +); + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + */ + +#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ + _isr, _entry_point, _is_fp ) \ + do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */ \ + unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size); \ + unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \ + _mem_stack_tmp &= ~(CPU_ALIGNMENT-1); \ + _reg_stack_tmp &= ~(CPU_ALIGNMENT-1); \ + _CPU_Context_save(_the_context); \ + (_the_context)->msp = _mem_stack_tmp; /* gr125 */ \ + (_the_context)->lr1 = \ + (_the_context)->locals[1] = \ + (_the_context)->rfb = _reg_stack_tmp; /* gr127 */ \ + (_the_context)->gr1 = _reg_stack_tmp - 4 * 4; \ + (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */ \ + (_the_context)->local_count = 1-1; \ + (_the_context)->PC1 = _entry_point; \ + (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \ + }while(0) + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ) + +/* + * The purpose of this macro is to allow the initial pointer into + * a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + */ + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (char *) (_base) + (_offset) ) + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + do { \ + *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ + } while(0) + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * halts/stops the CPU. + */ + +#define _CPU_Fatal_halt( _error ) \ + a29k_fatal_error(_error) + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_Bit_map_control. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + (_output) = 0; /* do something to prevent warnings */ \ + } + +#endif + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) + +#endif + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize( + rtems_cpu_table *cpu_table, + void (*thread_dispatch)() +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Internal_threads_Idle_thread_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void _CPU_Internal_threads_Idle_thread_body( void ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generallu used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: May be unnecessary to reload some registers. + */ + +void _CPU_Context_restore( + Context_Control *new_context +); + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + +/* The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + * + * This version will work on any processor, but if there is a better + * way for your CPU PLEASE use it. The most common way to do this is to: + * + * swap least significant two bytes with 16-bit rotate + * swap upper and lower 16-bits + * swap most significant two bytes with 16-bit rotate + * + * Some CPUs have special instructions which swap a 32-bit quantity in + * a single instruction (e.g. i486). It is probably best to avoid + * an "endian swapping control bit" in the CPU. One good reason is + * that interrupts would probably have to be disabled to insure that + * an interrupt does not try to access the same "chunk" with the wrong + * endian. Another good reason is that on some CPUs, the endian bit + * endianness for ALL fetches -- both code and data -- so the code + * will be fetched incorrectly. + */ + +#define CPU_swap_u32( value ) \ + ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | (((value >> 16)&0xff) << 8) | ((value>>24)&0xff) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/exec/score/cpu/a29k/cpu_asm.h b/c/src/exec/score/cpu/a29k/cpu_asm.h new file mode 100644 index 0000000000..c8ec99f52e --- /dev/null +++ b/c/src/exec/score/cpu/a29k/cpu_asm.h @@ -0,0 +1,71 @@ +/* + * cpu_asm.h + * + * Very loose template for an include file for the cpu_asm.? file + * if it is implemented as a ".S" file (preprocessed by cpp) instead + * of a ".s" file (preprocessed by gm4 or gasp). + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + * + */ +/* @(#)cpu_asm.h 06/08/96 1.2 */ + +#ifndef __CPU_ASM_h +#define __CPU_ASM_h + +/* pull in the generated offsets */ + +/* #include */ + +/* + * Hardware General Registers + */ + +/* put something here */ + +/* + * Hardware Floating Point Registers + */ + +/* put something here */ + +/* + * Hardware Control Registers + */ + +/* put something here */ + +/* + * Calling Convention + */ + +/* put something here */ + +/* + * Temporary registers + */ + +/* put something here */ + +/* + * Floating Point Registers - SW Conventions + */ + +/* put something here */ + +/* + * Temporary floating point registers + */ + +/* put something here */ + +#endif + +/* end of file */ diff --git a/c/src/exec/score/cpu/a29k/cpu_asm.s b/c/src/exec/score/cpu/a29k/cpu_asm.s new file mode 100644 index 0000000000..e915dd2ecf --- /dev/null +++ b/c/src/exec/score/cpu/a29k/cpu_asm.s @@ -0,0 +1,476 @@ +;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s +; * +; * Author: Craig Lebakken +; * +; * COPYRIGHT (c) 1996 by Transition Networks Inc. +; * +; * To anyone who acknowledges that this file is provided "AS IS" +; * without any express or implied warranty: +; * permission to use, copy, modify, and distribute this file +; * for any purpose is hereby granted without fee, provided that +; * the above copyright notice and this notice appears in all +; * copies, and that the name of Transition Networks not be used in +; * advertising or publicity pertaining to distribution of the +; * software without specific, written prior permission. +; * Transition Networks makes no representations about the suitability +; * of this software for any purpose. +; * +; * +; * This file contains the basic algorithms for all assembly code used +; * in an specific CPU port of RTEMS. These algorithms must be implemented +; * in assembly language +; * +; * NOTE: This is supposed to be a .S or .s file NOT a C file. +; * +; * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. +; * On-Line Applications Research Corporation (OAR). +; * All rights assigned to U.S. Government, 1994. +; * +; * This material may be reproduced by or for the U.S. Government pursuant +; * to the copyright license under the clause at DFARS 252.227-7013. This +; * notice must appear in all copies of this file and its derivatives. +; * +; * $Id$ +; */ + +;/* +; * This is supposed to be an assembly file. This means that system.h +; * and cpu.h should not be included in a "real" cpu_asm file. An +; * implementation in assembly should include "cpu_asm.h> +; */ + +;#include + .include "register.ah" + .include "amd.ah" + .include "pswmacro.ah" +; .extern _bsp_exit +; +; push a register onto the struct + .macro spush, sp, reg + store 0, 0, reg, sp ; push register + add sp, sp, 4 ; adjust stack pointer + .endm +; push a register onto the struct + .macro spushsr, sp, reg, sr + mfsr reg, sr + store 0, 0, reg, sp ; push register + add sp, sp, 4 ; adjust stack pointer + .endm +; pop a register from the struct + .macro spop, reg, sp + load 0, 0, reg, sp + add sp,sp,4 + .endm +; pop a special register from the struct + .macro spopsr, sreg, reg, sp + load 0, 0, reg, sp + mtsr sreg, reg + add sp,sp,4 + .endm +; +;/* +; * _CPU_Context_save_fp_context +; * +; * This routine is responsible for saving the FP context +; * at *fp_context_ptr. If the point to load the FP context +; * from is changed then the pointer is modified by this routine. +; * +; * Sometimes a macro implementation of this is in cpu.h which dereferences +; * the ** and a similarly named routine in this file is passed something +; * like a (Context_Control_fp *). The general rule on making this decision +; * is to avoid writing assembly language. +; */ + +;#if 0 +;void _CPU_Context_save_fp( +; void **fp_context_ptr +;) +;{ +;} +;#endif + .global _CPU_Context_save_fp +_CPU_Context_save_fp: + jmpi lr0 + nop + +;/* +; * _CPU_Context_restore_fp_context +; * +; * This routine is responsible for restoring the FP context +; * at *fp_context_ptr. If the point to load the FP context +; * from is changed then the pointer is modified by this routine. +; * +; * Sometimes a macro implementation of this is in cpu.h which dereferences +; * the ** and a similarly named routine in this file is passed something +; * like a (Context_Control_fp *). The general rule on making this decision +; * is to avoid writing assembly language. +; */ + +;#if 0 +;void _CPU_Context_restore_fp( +; void **fp_context_ptr +;) +;{ +;} +;#endif + .global __CPU_Context_restore_fp +__CPU_Context_restore_fp: + jmpi lr0 + nop + +;/* _CPU_Context_switch +; * +; * This routine performs a normal non-FP context switch. +; */ +;#if 0 +;void _CPU_Context_switch( +; Context_Control *run, +; Context_Control *heir +;) +;{ +;} +;#endif + .global __CPU_Context_switch +__CPU_Context_switch: + asneq 106, gr1, gr1 ; syscall + jmpi lr0 ; + nop ; + + + + .global _a29k_context_switch_sup +_a29k_context_switch_sup: + add pcb,lr2,0 + add kt1,lr3,0 ;move heir pointer to safe location + constn it0,SIG_SYNC + spush pcb,it0 + spush pcb,gr1 + spush pcb,rab ;push rab + spushsr pcb,it0,pc0 ;push specials + spushsr pcb,it0,pc1 + add pcb,pcb,1*4 ;space pc2 + spushsr pcb,it0,CHA ;push CHA + spushsr pcb,it0,CHD ;push CHD + spushsr pcb,it0,CHC ;push CHC + add pcb,pcb,1*4 ;space for alu + spushsr pcb,it0,ops ;push OPS + mfsr kt0,cps ;current status + const it1,FZ ;FZ constant + andn it1,kt0,it1 ;clear FZ bit + mtsr cps,it1 ;cps without FZ + add pcb,pcb,1*4 ;space for tav + mtsrim chc,0 ;possible DERR +; + spush pcb,lr1 ;push R-stack + spush pcb,rfb ; support + spush pcb,msp ;push M-stack pnt. +; + add pcb,pcb,3*4 ;space for floating point +; spush pcb,FPStat0 ;floating point +; spush pcb,FPStat1 +; spush pcb,FPStat2 +; + add pcb,pcb,4*4 ;space for IPA..Q +; + mtsrim cr,29-1 + storem 0,0,gr96,pcb ;push gr96-124, optional + add pcb,pcb,29*4 ;space for gr96-124 +; + sub it0,rfb,gr1 ;get bytes in cache + srl it0,it0,2 ;adjust to words + sub it0,it0,1 + spush pcb,it0 + mtsr cr,it0 + storem 0,0,lr0,pcb ;save lr0-rfb +; +context_restore: + add pcb,kt1,0 ;pcb=heir + add pcb,pcb,4 ;space for signal num + spop gr1,pcb ;restore freeze registers + add gr1,gr1,0 ;alu op + add pcb,pcb,9*4 ;move past freeze registers + add pcb,pcb,1*4 ;space for tav + spop lr1,pcb + spop rfb,pcb + spop msp,pcb +; spop FPStat0,pcb +; spop FPStat1,pcb +; spop FPStat2,pcb + add pcb,pcb,3*4 ;space for floating point + add pcb,pcb,4*4 ;space for IPA..Q + mtsrim cr,29-1 + loadm 0,0,gr96,pcb ;pop gr96-gr124 + add pcb,pcb,29*4 ;space for gr96-124 + + spop it1,pcb ;pop locals count + mtsr cr,it1 + loadm 0,0,lr0,pcb ;load locals + + add pcb,kt1,0 ;pcb=heir + mtsr cps,kt0 ;cps with FZ + nop + add pcb,pcb,4 ;space for signal num + spop gr1,pcb ;restore freeze registers + add gr1,gr1,0 ;alu op + spop rab,pcb + spopsr pc0,it1,pcb + spopsr pc1,it1,pcb + add pcb,pcb,4 ;space for pc2 + spopsr CHA,it1,pcb + spopsr CHD,it1,pcb + spopsr CHC,it1,pcb + add pcb,pcb,4 ;space for alu + spopsr ops,it1,pcb + nop + iret + + +;/* +; * _CPU_Context_restore +; * +; * This routine is generallu used only to restart self in an +; * efficient manner. It may simply be a label in _CPU_Context_switch. +; * +; * NOTE: May be unnecessary to reload some registers. +; */ +;#if 0 +;void _CPU_Context_restore( +; Context_Control *new_context +;) +;{ +;} +;#endif + + .global __CPU_Context_restore +__CPU_Context_restore: + asneq 107, gr1, gr1 ; syscall + jmpi lr0 ; + nop ; + + .global _a29k_context_restore_sup +_a29k_context_restore_sup: + add kt1,lr2,0 ;kt1 = restore context + mfsr kt0,cps ;current status + const it1,FZ ;FZ constant + andn it1,kt0,it1 ;clear FZ bit + mtsr cps,it1 ;cps without FZ + jmp context_restore + nop + + .global _a29k_context_save_sup +_a29k_context_save_sup: + add pcb,lr2,0 + constn it0,SIG_SYNC + spush pcb,it0 + spush pcb,gr1 + spush pcb,rab ;push rab + spushsr pcb,it0,pc0 ;push specials + spushsr pcb,it0,pc1 + add pcb,pcb,1*4 ;space pc2 + spushsr pcb,it0,CHA ;push CHA + spushsr pcb,it0,CHD ;push CHD + spushsr pcb,it0,CHC ;push CHC + add pcb,pcb,1*4 ;space for alu + spushsr pcb,it0,ops ;push OPS + mfsr it0,cps ;current status +SaveFZState it1,it2 + add pcb,pcb,1*4 ;space for tav + mtsrim chc,0 ;possible DERR +; + spush pcb,lr1 ;push R-stack + spush pcb,rfb ; support + spush pcb,msp ;push M-stack pnt. +; + spush pcb,FPStat0 ;floating point + spush pcb,FPStat1 + spush pcb,FPStat2 +; + add pcb,pcb,4*4 ;space for IPA..Q +; + mtsrim cr,29-1 + storem 0,0,gr96,pcb ;push gr96-124, optional + add pcb,pcb,29*4 ;space for gr96-124 +; + sub kt0,rfb,gr1 ;get bytes in cache + srl kt0,kt0,2 ;adjust to words + sub kt0,kt0,1 + spush pcb,kt0 ;push number of words + mtsr cr,kt0 + storem 0,0,lr0,pcb ;save lr0-rfb +; + mtsr cps,it0 ;cps with FZ +RestoreFZState it1,it2 + + nop + nop + nop +; + iret +; + + .global __CPU_Context_save +__CPU_Context_save: + asneq 108, gr1, gr1 ; syscall + jmpi lr0 ; + nop ; + + +;/* void __ISR_Handler() +; * +; * This routine provides the RTEMS interrupt management. +; * +; */ + +;#if 0 +;void _ISR_Handler() +;{ +; /* +; * This discussion ignores a lot of the ugly details in a real +; * implementation such as saving enough registers/state to be +; * able to do something real. Keep in mind that the goal is +; * to invoke a user's ISR handler which is written in C and +; * uses a certain set of registers. +; * +; * Also note that the exact order is to a large extent flexible. +; * Hardware will dictate a sequence for a certain subset of +; * _ISR_Handler while requirements for setting +; */ + +; /* +; * At entry to "common" _ISR_Handler, the vector number must be +; * available. On some CPUs the hardware puts either the vector +; * number or the offset into the vector table for this ISR in a +; * known place. If the hardware does not give us this information, +; * then the assembly portion of RTEMS for this port will contain +; * a set of distinct interrupt entry points which somehow place +; * the vector number in a known place (which is safe if another +; * interrupt nests this one) and branches to _ISR_Handler. +; * +; * save some or all context on stack +; * may need to save some special interrupt information for exit +; * +; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) +; * if ( _ISR_Nest_level == 0 ) +; * switch to software interrupt stack +; * #endif +; * +; * _ISR_Nest_level++; +; * +; * _Thread_Dispatch_disable_level++; +; * +; * (*_ISR_Vector_table[ vector ])( vector ); +; * +; * --_ISR_Nest_level; +; * +; * if ( _ISR_Nest_level ) +; * goto the label "exit interrupt (simple case)" +; * +; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) +; * restore stack +; * #endif +; * +; * if ( !_Context_Switch_necessary ) +; * goto the label "exit interrupt (simple case)" +; * +; * if ( !_ISR_Signals_to_thread_executing ) +; * goto the label "exit interrupt (simple case)" +; * +; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch +; * +; * prepare to get out of interrupt +; * return from interrupt (maybe to _ISR_Dispatch) +; * +; * LABEL "exit interrupt (simple case): +; * prepare to get out of interrupt +; * return from interrupt +; */ +;} +;#endif +; .global __ISR_Handler +;__ISR_Handler: +; jmpi lr0 +; nop + + .global _a29k_disable +_a29k_disable: + asneq 110, gr96, gr96 + jmpi lr0 + nop + + .global _a29k_disable_sup +_a29k_disable_sup: + mfsr kt0, ops + const kt1, (DI | TD) + consth kt1, (DI | TD) + or kt1, kt0, kt1 + mtsr ops, kt1 + iret + nop + + .global _a29k_disable_all +_a29k_disable_all: + asneq 112, gr96, gr96 + jmpi lr0 + nop + + .global _a29k_disable_all_sup +_a29k_disable_all_sup: + mfsr kt0, ops + const kt1, DA + consth kt1, DA + or kt1, kt0, kt1 + mtsr ops, kt1 + iret + nop + + .global _a29k_enable_all +_a29k_enable_all: + asneq 111, gr96, gr96 + jmpi lr0 + nop + + .global _a29k_enable_all_sup +_a29k_enable_all_sup: + mfsr kt0, ops + const kt1, DA + consth kt1, DA + andn kt1, kt0, kt1 + mtsr ops, kt1 + iret + nop + + .global _a29k_enable +_a29k_enable: + asneq 109, gr96, gr96 + jmpi lr0 + nop + + .global _a29k_enable_sup +_a29k_enable_sup: + mfsr kt0, ops + const kt1, (DI | TD) + consth kt1, (DI | TD) + andn kt1, kt0, kt1 + mtsr ops, kt1 + iret + nop + + .global _a29k_halt +_a29k_halt: + halt + jmp _a29k_halt + nop + + .global _a29k_super_mode +_a29k_super_mode: + mfsr gr96, ops + or gr96, gr96, 0x10 + mtsr ops, gr96 + iret + nop + + .global _a29k_as70 +_a29k_as70: + asneq 70,gr96,gr96 + jmpi lr0 + nop diff --git a/c/src/exec/score/cpu/a29k/pswmacro.ah b/c/src/exec/score/cpu/a29k/pswmacro.ah new file mode 100644 index 0000000000..c21eee4f35 --- /dev/null +++ b/c/src/exec/score/cpu/a29k/pswmacro.ah @@ -0,0 +1,442 @@ +; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; macros: Do_install and init_TLB +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ + +;* File information and includes. + + .file "macro.ah" + .ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI" + + + .macro CONST32, RegName, RegValue + const RegName, RegValue + consth RegName, RegValue + .endm + + .macro CONSTX, RegName, RegValue + .if (RegValue) <= 0x0000ffff + const RegName, RegValue + .else + const RegName, RegValue + consth RegName, RegValue + .endif + .endm + + .macro PRODEV, RegName + srl RegName, RegName, 24 + .endm + +; +;* MACRO TO INSTALL VECTOR TABLE ENTRIES +; + +;* Assumes vector table address in v0 + + .macro _setvec, trapnum, trapaddr + mfsr v0, vab ; + const v2, trapnum ; + sll v1, v2, 2 ; + add v1, v1, v0 ; v0 has location of vector tab + + const v2, trapaddr ; + consth v2, trapaddr ; + store 0, 0, v2, v1 ; + nop ; + .endm + + .macro syscall, name + const tav, HIF_@name ; + asneq V_SYSCALL, gr1, gr1 ; + nop ; + nop ; + .endm + + + +;* MACRO TO INSTALL VECTOR TABLE ENTRIES + + .macro Do_Install, V_Number, V_Address + const lr4, V_Address + consth lr4, V_Address + const lr3, V_Number * 4 + consth lr3, V_Number * 4 + call lr0, V_Install + nop + .endm + + .macro Do_InstallX, V_Number, V_Address + const lr4, V_Address + consth lr4, V_Address + const lr3, V_Number * 4 + consth lr3, V_Number * 4 + call lr0, V_InstallX + nop + .endm + + + +; push a register onto the stack + .macro pushreg, reg, sp + sub sp, sp, 4 ; adjust stack pointer + store 0, 0, reg, sp ; push register + .endm + + .macro push, sp, reg + sub sp, sp, 4 + store 0, 0, reg, sp + .endm + +; pop the register from stack + .macro popreg, reg, sp + load 0, 0, reg, sp ; pop register + add sp, sp, 4 ; adjust stack pointer + .endm + .macro pop, reg, sp + load 0, 0, reg, sp + add sp, sp, 4 + .endm + +; push a special register onto stack + .macro pushspcl, spcl, tmpreg, sp + sub sp, sp, 4 ; adjust stack pointer + mfsr tmpreg, spcl ; get spcl reg + store 0, 0, tmpreg, sp ; push onto stack + .endm + + .macro pushsr, sp, reg, sreg + mfsr reg, sreg + sub sp, sp, 4 + store 0, 0, reg, sp + .endm + +; pop a special register from stack + .macro popspcl, spcl, tmpreg, sp + load 0, 0, tmpreg, sp ; pop from stack + add sp, sp, 4 ; adjust stack pointer + mtsr spcl, tmpreg ; set spcl reg + .endm + + .macro popsr, sreg, reg, sp + load 0, 0, reg, sp + add sp, sp, 4 + mtsr sreg, reg + .endm + +; +; save freeze mode registers on memory stack. +; + + .macro SaveFZState, tmp1, tmp2 + + ; save freeze mode registers. + + pushspcl pc0, tmp1, msp + pushspcl pc1, tmp1, msp + pushspcl alu, tmp1, msp + + pushspcl cha, tmp1, msp + pushspcl chd, tmp1, msp + pushspcl chc, tmp1, msp + + pushspcl ops, tmp1, msp + + ; turn freeze off + + const tmp2, FZ + mfsr tmp1, cps + andn tmp1, tmp1, tmp2 + mtsr cps, tmp1 + .endm + +; restore freeze mode registers from memory stack. + + .macro RestoreFZState, tmp1, tmp2 + + ; turn freeze on + + const tmp2, (FZ|DI|DA) + mfsr tmp1, cps + or tmp1, tmp1, tmp2 + mtsr cps, tmp1 + + ; restore freeze mode registers. + + popspcl ops, tmp1, msp + popspcl chc, tmp1, msp + popspcl chd, tmp1, msp + popspcl cha, tmp1, msp + popspcl alu, tmp1, msp + popspcl pc1, tmp1, msp + popspcl pc0, tmp1, msp + .endm + +; +;* +; + .equ WS, 512 ; window size + .equ RALLOC, 4 * 4 ; stack alloc for C + .equ SIGCTX_UM_SIZE, 40 * 4 ; + .equ SIGCTX_RFB, (38) * 4 ; user mode saved + .equ SIGCTX_SM_SIZE, 12 * 4 ; + .equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ; + + .macro sup_sv + add it2, trapreg, 0 ; transfer signal # + sub msp, msp, 4 ; + store 0, 0, it2, msp ; save signal number + sub msp, msp, 4 ; push gr1 + + store 0, 0, gr1, msp ; + sub msp, msp, 4 ; push rab + store 0, 0, rab, msp ; + const it0, WS ; Window size + + sub rab, rfb, it0 ; set rab = rfb-512 + pushsr msp, it0, PC0 ; save program counter0 + pushsr msp, it0, PC1 ; save program counter1 + pushsr msp, it0, PC2 ; save program counter2 + + pushsr msp, it0, CHA ; save channel address + pushsr msp, it0, CHD ; save channel data + pushsr msp, it0, CHC ; save channel control + pushsr msp, it0, ALU ; save alu + + pushsr msp, it0, OPS ; save ops + sub msp, msp, 4 ; + store 0, 0, tav, msp ; push tav + mtsrim chc, 0 ; no loadm/storem + + mfsr it0, ops ; get ops value + const it1, (TD | DI) ; disable interrupts + consth it1, (TD | DI) ; disable interrupts + or it0, it0, it1 ; set bits + + mtsr ops, it0 ; set new ops + const it0, _sigcode ; signal handler + consth it0, _sigcode ; signal handler + mtsr pc1, it0 ; store pc1 + + add it1, it0, 4 ; next addr + mtsr pc0, it1 ; store pc1 location + iret ; return + nop ; ALIGN + .endm + + .macro sig_return + mfsr it0, cps ; get processor status + const it1, FZ|DA ; Freeze + traps disable + or it0, it0, it1 ; to set FZ+DA + mtsr cps, it0 ; in freeze mode + + load 0, 0, tav, msp ; restore tav + add msp, msp, 4 ; + + popsr OPS,it0, msp ; + popsr ALU,it0, msp ; + popsr CHC,it0, msp ; + popsr CHD,it0, msp ; + + popsr CHA,it0, msp ; + popsr PC2,it0, msp ; + popsr PC1,it0, msp ; + popsr PC0,it0, msp ; + + load 0, 0, rab, msp ; + add msp, msp, 4 ; + load 0, 0, it0, msp ; + add gr1, it0, 0 ; pop rsp + + add msp, msp, 8 ; discount signal # + iret + .endm + + .macro repair_R_stack + add v0, msp, SIGCTX_GR1 ; interrupted gr1 + load 0, 0, v2, v0 ; + add v0, msp, SIGCTX_RFB ; + load 0, 0, v3, v0 ; interupted rfb + + const v1, WS ; + sub v1, v3, v1 ; rfb-512 + cpltu v0, v2, v1 ; test gr1 < rfb-512 + jmpf v0, $1 ; + + add gr1, rab, 0 ; + add v2, v1, 0 ; set LB = rfb-512 +$1: +;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill +;* if no, LB=gr1 interrupted cache < 126 registers + cpleu v0, v2, rfb ; test LB<=rfb + jmpf v0, $2 ; + nop ; + add v2, rfb, 0 ; +$2: + cpeq v0, v3, rfb ; fill rfb->'rfb + jmpt v0, $3 ; if rfb==rfb' + const tav, (0x80<<2) ; prepare for fill + or tav, tav, v2 ; + + mtsr IPA, tav ; IPA=LA<<2 + sub tav, v3, gr98 ; cache fill LA->rfb + srl tav, tav, 2 ; convert to words + sub tav, tav, 1 ; + + mtsr cr, tav ; + loadm 0, 0, gr0, v2 ; fill from LA->rfb +$3: + add rfb, v3, 0 ; move rfb upto 'rfb + sub rab, v1, 0 ; assign rab to rfb-512 + + add v0, msp, SIGCTX_GR1 ; + load 0, 0, v2, v0 ; v0 = interrupted gr1 + add gr1, v2, 0 ; move gr1 upto 'gr1 + nop ; + .endm + + .macro repair_regs + mtsrim cr, 29 - 1 ; to restore locals + loadm 0, 0, v0, msp ; + add msp, msp, 29*4 ; + popsr Q, tav, msp ; + + popsr IPC, tav, msp ; + popsr IPB, tav, msp ; + popsr IPA, tav, msp ; + pop FPStat3, msp ; floating point regs + + pop FPStat2, msp ; floating point regs + pop FPStat1, msp ; floating point regs + pop FPStat0, msp ; floating point regs + + add msp, msp, 3*4 ; R-stack repaired + .endm + +; +;*HIF related... +; + + + + +; send the message in bufaddr to Montip. + .macro SendMessageToMontip, bufaddr + const lr2, bufaddr +$1: + call lr0, _msg_send + consth lr2, bufaddr + cpeq gr96, gr96, 0 + jmpf gr96, $1 + const lr2, bufaddr + .endm + +; build a HIF_CALL message in bufaddr to send to montip. + .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2 + const tmp1, bufaddr + consth tmp1, bufaddr + const tmp2, HIF_CALL_MSGCODE + store 0, 0, tmp2, tmp1 ; msg code + add tmp1, tmp1, 4 + const tmp2, HIF_CALL_MSGLEN + store 0, 0, tmp2, tmp1 ; msg len + add tmp1, tmp1, 4 + store 0, 0, gr121, tmp1 ; service number + add tmp1, tmp1, 4 + store 0, 0, lr2, tmp1 ; lr2 + add tmp1, tmp1, 4 + store 0, 0, lr3, tmp1 ; lr3 + add tmp1, tmp1, 4 + store 0, 0, lr4, tmp1 ; lr4 + .endm + +; +;* +;* All the funky AMD style macros go in here...simply for +;* compatility +; +; + .macro IMPORT, symbol + .extern symbol + .endm + + .macro GLOBAL, symbol + .global symbol + .endm + + .macro USESECT, name, type + .sect name, type + .use name + .endm + + .macro SECTION, name, type + .sect name, type + .endm + + .macro FUNC, fname, lineno + .global fname +fname: + .endm + + .macro ENDFUNC, fname, lineno + .endm + +;*************************************LONG + .macro LONG, varname +varname: + .block 4 + .endm + +;*************************************UNSIGNED LONG + .macro ULONG, varname +varname: + .block 4 + .endm + +;*************************************SHORT + .macro SHORT, varname +varname: + .block 2 + .endm + +;*************************************CHAR + .macro CHAR, varname +varname: + .block 1 + .endm + +;*************************************LONGARRAY + .macro LONGARRAY, name, count +name: + .block count*4 + .endm + +;*************************************SHORTARRAY + + .macro SHORTARRAY, name, count +name: + .block count*2 + .endm + +;*************************************CHARARRAY + + .macro CHARARRAY, name, count +name: + .block count + .endm + + +;*************************************VOID_FPTR + + .macro VOID_FPTR, name +name: + .block 4 + .endm diff --git a/c/src/exec/score/cpu/a29k/rtems.c b/c/src/exec/score/cpu/a29k/rtems.c new file mode 100644 index 0000000000..a5c8699a0f --- /dev/null +++ b/c/src/exec/score/cpu/a29k/rtems.c @@ -0,0 +1,48 @@ +/* rtems.c ===> rtems.S or rtems.s + * + * This file contains the single entry point code for + * the XXX implementation of RTEMS. + * + * NOTE: This is supposed to be a .S or .s file NOT a C file. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ +#ifndef lint +static char _sccsid[] = "@(#)rtems.c 04/08/96 1.1\n"; +#endif + +/* + * This is supposed to be an assembly file. This means that system.h + * and cpu.h should not be included in a "real" rtems file. + */ + +#include +#include +/* #include "asm.h> */ + +/* + * RTEMS + * + * This routine jumps to the directive indicated in the + * CPU defined register. This routine is used when RTEMS is + * linked by itself and placed in ROM. This routine is the + * first address in the ROM space for RTEMS. The user "calls" + * this address with the directive arguments in the normal place. + * This routine then jumps indirectly to the correct directive + * preserving the arguments. The directive should not realize + * it has been "wrapped" in this way. The table "_Entry_points" + * is used to look up the directive. + */ + +void RTEMS() +{ +} + diff --git a/cpukit/score/cpu/a29k/amd.ah b/cpukit/score/cpu/a29k/amd.ah new file mode 100644 index 0000000000..ceef89564a --- /dev/null +++ b/cpukit/score/cpu/a29k/amd.ah @@ -0,0 +1,531 @@ +; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Initialization values for registers after RESET +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; +' /* $Id */ +;* File information and includes. + + .file "amd.ah" + .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI" + + + +; +;* AMD PROCESSOR SPECIFIC VALUES... +; + +; +;* Processor revision levels... +; + +; PRL values: 31-28 27-24 +; Am29000 0 x +; Am29005 1 x +; Am29050 2 x +; Am29035 3 x +; Am29030 4 x +; Am29200 5 x +; Am29205 5 1x +; Am29240 6 0 +; Manx 7 0 +; Cougar 8 0 + + + .equ AM29000_PRL, 0x00 + + .equ AM29005_PRL, 0x10 + + .equ AM29050_PRL, 0x20 + + .equ AM29035_PRL, 0x30 + + .equ AM29030_PRL, 0x40 + + .equ AM29200_PRL, 0x50 + + .equ AM29205_PRL, 0x58 + + .equ AM29240_PRL, 0x60 + + .equ AM29040_PRL, 0x70 + + .equ MANX_PRL, 0x70 + + .equ COUGAR_PRL, 0x80 + +; +;* data structures sizes. +; + .equ CFGINFO_SIZE, 16*4 + + .equ PGMINFO_SIZE, 16*4 + + .equ VARARGS_SPACE, 16*4 + + .equ WINDOWSIZE, 0x80 +; +;* Am29027 Mode registers +; + + .equ Am29027Mode1, 0x0fc00820 + + .equ Am29027Mode2, 0x00001375 + + + +;* Processor Based Equates and Defines + + .equ SIG_SYNC, -1 + + .equ ENABLE, (SM) + + .equ DISABLE, (ENABLE | DI | DA) + + .equ DISABLE_FZ, (FZ | ENABLE | DI | DA) + + .equ CLR_TRAP, (FZ | DA) + + .equ InitOPS, (TD | SM | (3< + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .globl SYM (sym) +#define EXTERN(sym) .globl SYM (sym) + +#endif +/* end of include file */ + + diff --git a/cpukit/score/cpu/a29k/cpu.c b/cpukit/score/cpu/a29k/cpu.c new file mode 100644 index 0000000000..4312e85035 --- /dev/null +++ b/cpukit/score/cpu/a29k/cpu.c @@ -0,0 +1,256 @@ +/* + * AMD 29K CPU Dependent Source + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ +#ifndef lint +static char _sccsid[] = "@(#)cpu.c 21 Aug 1996 1.6\n"; +#endif + +#include +#include +#include +#include +#include +#include + +void a29k_ISR_Handler(unsigned32 vector); + +/* _CPU_Initialize + * + * This routine performs processor dependent initialization. + * + * INPUT PARAMETERS: + * cpu_table - CPU table to initialize + * thread_dispatch - address of disptaching routine + */ + + +void _CPU_Initialize( + rtems_cpu_table *cpu_table, + void (*thread_dispatch)() /* ignored on this CPU */ +) +{ + unsigned int i; + /* + * The thread_dispatch argument is the address of the entry point + * for the routine called at the end of an ISR once it has been + * decided a context switch is necessary. On some compilation + * systems it is difficult to call a high-level language routine + * from assembly. This allows us to trick these systems. + * + * If you encounter this problem save the entry point in a CPU + * dependent variable. + */ + + _CPU_Thread_dispatch_pointer = thread_dispatch; + + /* + * If there is not an easy way to initialize the FP context + * during Context_Initialize, then it is usually easier to + * save an "uninitialized" FP context here and copy it to + * the task's during Context_Initialize. + */ + + /* FP context initialization support goes here */ + + _CPU_Table = *cpu_table; + + for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ ) + { + _ISR_Vector_table[i] = (proc_ptr)NULL; + } +} + +/*PAGE + * + * _CPU_ISR_Get_level + */ + +unsigned32 _CPU_ISR_Get_level( void ) +{ + /* + * This routine returns the current interrupt level. + */ + return 0; +} + +/*PAGE + * + * _CPU_ISR_install_raw_handler + */ + +extern void intr14( void ); +extern void intr3( void ); +extern void intr2( void ); + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + /* + * This is where we install the interrupt handler into the "raw" interrupt + * table used by the CPU to dispatch interrupt handlers. + */ + switch( vector ) + { + case 14: + _settrap( vector, intr14 ); + break; + case 3: + _settrap( vector, intr3 ); + break; + case 2: + _settrap( vector, intr2 ); + break; + default: + break; + } +} + + +/*PAGE + * + * _CPU_ISR_install_vector + * + * This kernel routine installs the RTEMS handler for the + * specified vector. + * + * Input parameters: + * vector - interrupt vector number + * old_handler - former ISR for this vector number + * new_handler - replacement ISR for this vector number + * + * Output parameters: NONE + * + */ + +void _CPU_ISR_install_vector( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + *old_handler = _ISR_Vector_table[ vector ]; + + /* + * If the interrupt vector table is a table of pointer to isr entry + * points, then we need to install the appropriate RTEMS interrupt + * handler for this vector number. + */ + + _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); + + /* + * We put the actual user ISR address in '_ISR_vector_table'. This will + * be used by the _ISR_Handler so the user gets control. + */ + + _ISR_Vector_table[ vector ] = new_handler; +} + +/*PAGE + * + * _CPU_Install_interrupt_stack + */ + +void _CPU_Install_interrupt_stack( void ) +{ +} + +/*PAGE + * + * _CPU_Internal_threads_Idle_thread_body + * + * NOTES: + * + * 1. This is the same as the regular CPU independent algorithm. + * + * 2. If you implement this using a "halt", "idle", or "shutdown" + * instruction, then don't forget to put it in an infinite loop. + * + * 3. Be warned. Some processors with onboard DMA have been known + * to stop the DMA if the CPU were put in IDLE mode. This might + * also be a problem with other on-chip peripherals. So use this + * hook with caution. + */ + +void _CPU_Internal_threads_Idle_thread_body( void ) +{ + + for( ; ; ) + { + } + /* insert your "halt" instruction here */ ; +} + +void a29k_fatal_error( unsigned32 error ) +{ + printf("\n\nfatal error %d, rebooting!!!\n",error ); + exit(error); +} + + /* + * This discussion ignores a lot of the ugly details in a real + * implementation such as saving enough registers/state to be + * able to do something real. Keep in mind that the goal is + * to invoke a user's ISR handler which is written in C and + * uses a certain set of registers. + * + * Also note that the exact order is to a large extent flexible. + * Hardware will dictate a sequence for a certain subset of + * _ISR_Handler while requirements for setting + */ + + /* + * At entry to "common" _ISR_Handler, the vector number must be + * available. On some CPUs the hardware puts either the vector + * number or the offset into the vector table for this ISR in a + * known place. If the hardware does not give us this information, + * then the assembly portion of RTEMS for this port will contain + * a set of distinct interrupt entry points which somehow place + * the vector number in a known place (which is safe if another + * interrupt nests this one) and branches to _ISR_Handler. + * + */ + +void a29k_ISR_Handler(unsigned32 vector) +{ + _ISR_Nest_level++; + _Thread_Dispatch_disable_level++; + if ( _ISR_Vector_table[ vector ] ) + (*_ISR_Vector_table[ vector ])( vector ); + --_Thread_Dispatch_disable_level; + --_ISR_Nest_level; + if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level && + (_Context_Switch_necessary || _ISR_Signals_to_thread_executing )) + _Thread_Dispatch(); + return; +} diff --git a/cpukit/score/cpu/a29k/pswmacro.ah b/cpukit/score/cpu/a29k/pswmacro.ah new file mode 100644 index 0000000000..c21eee4f35 --- /dev/null +++ b/cpukit/score/cpu/a29k/pswmacro.ah @@ -0,0 +1,442 @@ +; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; macros: Do_install and init_TLB +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ + +;* File information and includes. + + .file "macro.ah" + .ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI" + + + .macro CONST32, RegName, RegValue + const RegName, RegValue + consth RegName, RegValue + .endm + + .macro CONSTX, RegName, RegValue + .if (RegValue) <= 0x0000ffff + const RegName, RegValue + .else + const RegName, RegValue + consth RegName, RegValue + .endif + .endm + + .macro PRODEV, RegName + srl RegName, RegName, 24 + .endm + +; +;* MACRO TO INSTALL VECTOR TABLE ENTRIES +; + +;* Assumes vector table address in v0 + + .macro _setvec, trapnum, trapaddr + mfsr v0, vab ; + const v2, trapnum ; + sll v1, v2, 2 ; + add v1, v1, v0 ; v0 has location of vector tab + + const v2, trapaddr ; + consth v2, trapaddr ; + store 0, 0, v2, v1 ; + nop ; + .endm + + .macro syscall, name + const tav, HIF_@name ; + asneq V_SYSCALL, gr1, gr1 ; + nop ; + nop ; + .endm + + + +;* MACRO TO INSTALL VECTOR TABLE ENTRIES + + .macro Do_Install, V_Number, V_Address + const lr4, V_Address + consth lr4, V_Address + const lr3, V_Number * 4 + consth lr3, V_Number * 4 + call lr0, V_Install + nop + .endm + + .macro Do_InstallX, V_Number, V_Address + const lr4, V_Address + consth lr4, V_Address + const lr3, V_Number * 4 + consth lr3, V_Number * 4 + call lr0, V_InstallX + nop + .endm + + + +; push a register onto the stack + .macro pushreg, reg, sp + sub sp, sp, 4 ; adjust stack pointer + store 0, 0, reg, sp ; push register + .endm + + .macro push, sp, reg + sub sp, sp, 4 + store 0, 0, reg, sp + .endm + +; pop the register from stack + .macro popreg, reg, sp + load 0, 0, reg, sp ; pop register + add sp, sp, 4 ; adjust stack pointer + .endm + .macro pop, reg, sp + load 0, 0, reg, sp + add sp, sp, 4 + .endm + +; push a special register onto stack + .macro pushspcl, spcl, tmpreg, sp + sub sp, sp, 4 ; adjust stack pointer + mfsr tmpreg, spcl ; get spcl reg + store 0, 0, tmpreg, sp ; push onto stack + .endm + + .macro pushsr, sp, reg, sreg + mfsr reg, sreg + sub sp, sp, 4 + store 0, 0, reg, sp + .endm + +; pop a special register from stack + .macro popspcl, spcl, tmpreg, sp + load 0, 0, tmpreg, sp ; pop from stack + add sp, sp, 4 ; adjust stack pointer + mtsr spcl, tmpreg ; set spcl reg + .endm + + .macro popsr, sreg, reg, sp + load 0, 0, reg, sp + add sp, sp, 4 + mtsr sreg, reg + .endm + +; +; save freeze mode registers on memory stack. +; + + .macro SaveFZState, tmp1, tmp2 + + ; save freeze mode registers. + + pushspcl pc0, tmp1, msp + pushspcl pc1, tmp1, msp + pushspcl alu, tmp1, msp + + pushspcl cha, tmp1, msp + pushspcl chd, tmp1, msp + pushspcl chc, tmp1, msp + + pushspcl ops, tmp1, msp + + ; turn freeze off + + const tmp2, FZ + mfsr tmp1, cps + andn tmp1, tmp1, tmp2 + mtsr cps, tmp1 + .endm + +; restore freeze mode registers from memory stack. + + .macro RestoreFZState, tmp1, tmp2 + + ; turn freeze on + + const tmp2, (FZ|DI|DA) + mfsr tmp1, cps + or tmp1, tmp1, tmp2 + mtsr cps, tmp1 + + ; restore freeze mode registers. + + popspcl ops, tmp1, msp + popspcl chc, tmp1, msp + popspcl chd, tmp1, msp + popspcl cha, tmp1, msp + popspcl alu, tmp1, msp + popspcl pc1, tmp1, msp + popspcl pc0, tmp1, msp + .endm + +; +;* +; + .equ WS, 512 ; window size + .equ RALLOC, 4 * 4 ; stack alloc for C + .equ SIGCTX_UM_SIZE, 40 * 4 ; + .equ SIGCTX_RFB, (38) * 4 ; user mode saved + .equ SIGCTX_SM_SIZE, 12 * 4 ; + .equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ; + + .macro sup_sv + add it2, trapreg, 0 ; transfer signal # + sub msp, msp, 4 ; + store 0, 0, it2, msp ; save signal number + sub msp, msp, 4 ; push gr1 + + store 0, 0, gr1, msp ; + sub msp, msp, 4 ; push rab + store 0, 0, rab, msp ; + const it0, WS ; Window size + + sub rab, rfb, it0 ; set rab = rfb-512 + pushsr msp, it0, PC0 ; save program counter0 + pushsr msp, it0, PC1 ; save program counter1 + pushsr msp, it0, PC2 ; save program counter2 + + pushsr msp, it0, CHA ; save channel address + pushsr msp, it0, CHD ; save channel data + pushsr msp, it0, CHC ; save channel control + pushsr msp, it0, ALU ; save alu + + pushsr msp, it0, OPS ; save ops + sub msp, msp, 4 ; + store 0, 0, tav, msp ; push tav + mtsrim chc, 0 ; no loadm/storem + + mfsr it0, ops ; get ops value + const it1, (TD | DI) ; disable interrupts + consth it1, (TD | DI) ; disable interrupts + or it0, it0, it1 ; set bits + + mtsr ops, it0 ; set new ops + const it0, _sigcode ; signal handler + consth it0, _sigcode ; signal handler + mtsr pc1, it0 ; store pc1 + + add it1, it0, 4 ; next addr + mtsr pc0, it1 ; store pc1 location + iret ; return + nop ; ALIGN + .endm + + .macro sig_return + mfsr it0, cps ; get processor status + const it1, FZ|DA ; Freeze + traps disable + or it0, it0, it1 ; to set FZ+DA + mtsr cps, it0 ; in freeze mode + + load 0, 0, tav, msp ; restore tav + add msp, msp, 4 ; + + popsr OPS,it0, msp ; + popsr ALU,it0, msp ; + popsr CHC,it0, msp ; + popsr CHD,it0, msp ; + + popsr CHA,it0, msp ; + popsr PC2,it0, msp ; + popsr PC1,it0, msp ; + popsr PC0,it0, msp ; + + load 0, 0, rab, msp ; + add msp, msp, 4 ; + load 0, 0, it0, msp ; + add gr1, it0, 0 ; pop rsp + + add msp, msp, 8 ; discount signal # + iret + .endm + + .macro repair_R_stack + add v0, msp, SIGCTX_GR1 ; interrupted gr1 + load 0, 0, v2, v0 ; + add v0, msp, SIGCTX_RFB ; + load 0, 0, v3, v0 ; interupted rfb + + const v1, WS ; + sub v1, v3, v1 ; rfb-512 + cpltu v0, v2, v1 ; test gr1 < rfb-512 + jmpf v0, $1 ; + + add gr1, rab, 0 ; + add v2, v1, 0 ; set LB = rfb-512 +$1: +;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill +;* if no, LB=gr1 interrupted cache < 126 registers + cpleu v0, v2, rfb ; test LB<=rfb + jmpf v0, $2 ; + nop ; + add v2, rfb, 0 ; +$2: + cpeq v0, v3, rfb ; fill rfb->'rfb + jmpt v0, $3 ; if rfb==rfb' + const tav, (0x80<<2) ; prepare for fill + or tav, tav, v2 ; + + mtsr IPA, tav ; IPA=LA<<2 + sub tav, v3, gr98 ; cache fill LA->rfb + srl tav, tav, 2 ; convert to words + sub tav, tav, 1 ; + + mtsr cr, tav ; + loadm 0, 0, gr0, v2 ; fill from LA->rfb +$3: + add rfb, v3, 0 ; move rfb upto 'rfb + sub rab, v1, 0 ; assign rab to rfb-512 + + add v0, msp, SIGCTX_GR1 ; + load 0, 0, v2, v0 ; v0 = interrupted gr1 + add gr1, v2, 0 ; move gr1 upto 'gr1 + nop ; + .endm + + .macro repair_regs + mtsrim cr, 29 - 1 ; to restore locals + loadm 0, 0, v0, msp ; + add msp, msp, 29*4 ; + popsr Q, tav, msp ; + + popsr IPC, tav, msp ; + popsr IPB, tav, msp ; + popsr IPA, tav, msp ; + pop FPStat3, msp ; floating point regs + + pop FPStat2, msp ; floating point regs + pop FPStat1, msp ; floating point regs + pop FPStat0, msp ; floating point regs + + add msp, msp, 3*4 ; R-stack repaired + .endm + +; +;*HIF related... +; + + + + +; send the message in bufaddr to Montip. + .macro SendMessageToMontip, bufaddr + const lr2, bufaddr +$1: + call lr0, _msg_send + consth lr2, bufaddr + cpeq gr96, gr96, 0 + jmpf gr96, $1 + const lr2, bufaddr + .endm + +; build a HIF_CALL message in bufaddr to send to montip. + .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2 + const tmp1, bufaddr + consth tmp1, bufaddr + const tmp2, HIF_CALL_MSGCODE + store 0, 0, tmp2, tmp1 ; msg code + add tmp1, tmp1, 4 + const tmp2, HIF_CALL_MSGLEN + store 0, 0, tmp2, tmp1 ; msg len + add tmp1, tmp1, 4 + store 0, 0, gr121, tmp1 ; service number + add tmp1, tmp1, 4 + store 0, 0, lr2, tmp1 ; lr2 + add tmp1, tmp1, 4 + store 0, 0, lr3, tmp1 ; lr3 + add tmp1, tmp1, 4 + store 0, 0, lr4, tmp1 ; lr4 + .endm + +; +;* +;* All the funky AMD style macros go in here...simply for +;* compatility +; +; + .macro IMPORT, symbol + .extern symbol + .endm + + .macro GLOBAL, symbol + .global symbol + .endm + + .macro USESECT, name, type + .sect name, type + .use name + .endm + + .macro SECTION, name, type + .sect name, type + .endm + + .macro FUNC, fname, lineno + .global fname +fname: + .endm + + .macro ENDFUNC, fname, lineno + .endm + +;*************************************LONG + .macro LONG, varname +varname: + .block 4 + .endm + +;*************************************UNSIGNED LONG + .macro ULONG, varname +varname: + .block 4 + .endm + +;*************************************SHORT + .macro SHORT, varname +varname: + .block 2 + .endm + +;*************************************CHAR + .macro CHAR, varname +varname: + .block 1 + .endm + +;*************************************LONGARRAY + .macro LONGARRAY, name, count +name: + .block count*4 + .endm + +;*************************************SHORTARRAY + + .macro SHORTARRAY, name, count +name: + .block count*2 + .endm + +;*************************************CHARARRAY + + .macro CHARARRAY, name, count +name: + .block count + .endm + + +;*************************************VOID_FPTR + + .macro VOID_FPTR, name +name: + .block 4 + .endm -- cgit v1.2.3