From a151ee167ecf7cc7f18e66d03b49843c01031d00 Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Thu, 29 Oct 2020 13:40:54 -0500 Subject: bsps: Move ARM GICv2 driver to bsps/shared This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code. --- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c | 64 ----- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c | 64 +++++ bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c | 61 ----- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c | 61 +++++ bsps/arm/shared/irq/irq-gic.c | 286 --------------------- bsps/include/dev/irq/arm-gic-irq.h | 4 +- bsps/shared/dev/irq/arm-gicv2.c | 275 ++++++++++++++++++++ bsps/shared/dev/irq/arm-gicv3.c | 2 +- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 3 +- c/src/lib/libbsp/arm/imx/Makefile.am | 3 +- c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 3 +- c/src/lib/libbsp/arm/xen/Makefile.am | 3 +- c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +- c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 3 +- spec/build/bsps/aarch64/a53/obj.yml | 2 +- .../arm/altera-cyclone-v/bspalteracyclonev.yml | 3 +- spec/build/bsps/arm/imx/bspimx.yml | 3 +- .../bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 3 +- spec/build/bsps/arm/xen/bspxen.yml | 3 +- spec/build/bsps/arm/xilinx-zynq/obj.yml | 3 +- .../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 3 +- 21 files changed, 428 insertions(+), 427 deletions(-) delete mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c delete mode 100644 bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c create mode 100644 bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c delete mode 100644 bsps/arm/shared/irq/irq-gic.c create mode 100644 bsps/shared/dev/irq/arm-gicv2.c diff --git a/bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c b/bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c deleted file mode 100644 index fe74bf46bd..0000000000 --- a/bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup RTEMSBSPsAArch64Shared - * - * @brief AArch64-specific ARM GICv3 handlers. - */ - -/* - * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) - * Written by Kinsey Moore - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -void arm_interrupt_handler_dispatch(rtems_vector_number vector) -{ - uint32_t interrupt_level = _CPU_ISR_Get_level(); - AArch64_interrupt_enable(1); - bsp_interrupt_handler_dispatch(vector); - _CPU_ISR_Set_level(interrupt_level); -} - -void arm_interrupt_facility_set_exception_handler(void) -{ - AArch64_set_exception_handler( - AARCH64_EXCEPTION_SPx_IRQ, - _AArch64_Exception_interrupt_no_nest - ); - AArch64_set_exception_handler( - AARCH64_EXCEPTION_SP0_IRQ, - _AArch64_Exception_interrupt_nest - ); -} - -void bsp_interrupt_dispatch(void) -{ - gicv3_interrupt_dispatch(); -} diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c new file mode 100644 index 0000000000..67839118e1 --- /dev/null +++ b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Shared + * + * @brief AArch64-specific ARM GICv3 handlers. + */ + +/* + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void arm_interrupt_handler_dispatch(rtems_vector_number vector) +{ + uint32_t interrupt_level = _CPU_ISR_Get_level(); + AArch64_interrupt_enable(1); + bsp_interrupt_handler_dispatch(vector); + _CPU_ISR_Set_level(interrupt_level); +} + +void arm_interrupt_facility_set_exception_handler(void) +{ + AArch64_set_exception_handler( + AARCH64_EXCEPTION_SPx_IRQ, + _AArch64_Exception_interrupt_no_nest + ); + AArch64_set_exception_handler( + AARCH64_EXCEPTION_SP0_IRQ, + _AArch64_Exception_interrupt_nest + ); +} + +void bsp_interrupt_dispatch(void) +{ + gicvx_interrupt_dispatch(); +} diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c deleted file mode 100644 index b805199ba9..0000000000 --- a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup RTEMSBSPsARMShared - * - * @brief ARM-specific IRQ handlers. - */ - -/* - * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) - * Written by Kinsey Moore - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -void arm_interrupt_handler_dispatch(rtems_vector_number vector) -{ - uint32_t psr = _ARMV4_Status_irq_enable(); - bsp_interrupt_handler_dispatch(vector); - - _ARMV4_Status_restore(psr); -} - -void arm_interrupt_facility_set_exception_handler(void) -{ - arm_cp15_set_exception_handler( - ARM_EXCEPTION_IRQ, - _ARMV4_Exception_interrupt - ); -} - -void bsp_interrupt_dispatch(void) -{ - gicv3_interrupt_dispatch(); -} diff --git a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c new file mode 100644 index 0000000000..b9267aecba --- /dev/null +++ b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMShared + * + * @brief ARM-specific IRQ handlers. + */ + +/* + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +void arm_interrupt_handler_dispatch(rtems_vector_number vector) +{ + uint32_t psr = _ARMV4_Status_irq_enable(); + bsp_interrupt_handler_dispatch(vector); + + _ARMV4_Status_restore(psr); +} + +void arm_interrupt_facility_set_exception_handler(void) +{ + arm_cp15_set_exception_handler( + ARM_EXCEPTION_IRQ, + _ARMV4_Exception_interrupt + ); +} + +void bsp_interrupt_dispatch(void) +{ + gicvx_interrupt_dispatch(); +} diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c deleted file mode 100644 index 1a401b67b6..0000000000 --- a/bsps/arm/shared/irq/irq-gic.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -#include - -#include - -#include -#include -#include - -#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE) - -#define PRIORITY_DEFAULT 127 - -/* - * The following variants - * - * - GICv1 with Security Extensions, - * - GICv2 without Security Extensions, or - * - within Secure processor mode - * - * have the ability to assign group 0 or 1 to individual interrupts. Group - * 0 interrupts can be configured to raise an FIQ exception. This enables - * the use of NMIs with respect to RTEMS. - * - * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - * define. Use arm_gic_irq_set_group() to change the group of an - * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is - * defined). - */ -#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 -#define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE) -#define CPUIF_ICCICR \ - (GIC_CPUIF_ICCICR_CBPR | GIC_CPUIF_ICCICR_FIQ_EN \ - | GIC_CPUIF_ICCICR_ACK_CTL | GIC_CPUIF_ICCICR_ENABLE_GRP_1 \ - | GIC_CPUIF_ICCICR_ENABLE) -#else -#define DIST_ICDDCR GIC_DIST_ICDDCR_ENABLE -#define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE -#endif - -void bsp_interrupt_dispatch(void) -{ - volatile gic_cpuif *cpuif = GIC_CPUIF; - uint32_t icciar = cpuif->icciar; - rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); - rtems_vector_number spurious = 1023; - - if (vector != spurious) { - uint32_t psr = _ARMV4_Status_irq_enable(); - - bsp_interrupt_handler_dispatch(vector); - - _ARMV4_Status_restore(psr); - - cpuif->icceoir = icciar; - } -} - -void bsp_interrupt_vector_enable(rtems_vector_number vector) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - - gic_id_enable(dist, vector); -} - -void bsp_interrupt_vector_disable(rtems_vector_number vector) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - - gic_id_disable(dist, vector); -} - -static inline uint32_t get_id_count(volatile gic_dist *dist) -{ - uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); - - id_count = 32 * (id_count + 1); - id_count = id_count <= 1020 ? id_count : 1020; - - return id_count; -} - -static void enable_fiq(void) -{ -#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - rtems_interrupt_level level; - - rtems_interrupt_local_disable(level); - level &= ~ARM_PSR_F; - rtems_interrupt_local_enable(level); -#endif -} - -rtems_status_code bsp_interrupt_facility_initialize(void) -{ - volatile gic_cpuif *cpuif = GIC_CPUIF; - volatile gic_dist *dist = ARM_GIC_DIST; - uint32_t id_count = get_id_count(dist); - uint32_t id; - - arm_cp15_set_exception_handler( - ARM_EXCEPTION_IRQ, - _ARMV4_Exception_interrupt - ); - - for (id = 0; id < id_count; id += 32) { -#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - dist->icdigr[id / 32] = 0xffffffff; -#endif - dist->icdicer[id / 32] = 0xffffffff; - } - - for (id = 0; id < id_count; ++id) { - gic_id_set_priority(dist, id, PRIORITY_DEFAULT); - } - - for (id = 32; id < id_count; ++id) { - gic_id_set_targets(dist, id, 0x01); - } - - cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); - cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); - cpuif->iccicr = CPUIF_ICCICR; - - dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE; - - enable_fiq(); - return RTEMS_SUCCESSFUL; -} - -#ifdef RTEMS_SMP -BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) -{ - volatile gic_cpuif *cpuif = GIC_CPUIF; - volatile gic_dist *dist = ARM_GIC_DIST; - uint32_t id; - - while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { - /* Wait */ - } - -#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - dist->icdigr[0] = 0xffffffff; -#endif - - /* Initialize Peripheral Private Interrupts (PPIs) */ - for (id = 0; id < 32; ++id) { - gic_id_set_priority(dist, id, PRIORITY_DEFAULT); - } - - cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); - cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); - cpuif->iccicr = CPUIF_ICCICR; - - enable_fiq(); -} -#endif - -rtems_status_code arm_gic_irq_set_priority( - rtems_vector_number vector, - uint8_t priority -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (bsp_interrupt_is_valid_vector(vector)) { - volatile gic_dist *dist = ARM_GIC_DIST; - - gic_id_set_priority(dist, vector, priority); - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -rtems_status_code arm_gic_irq_get_priority( - rtems_vector_number vector, - uint8_t *priority -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (bsp_interrupt_is_valid_vector(vector)) { - volatile gic_dist *dist = ARM_GIC_DIST; - - *priority = gic_id_get_priority(dist, vector); - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -rtems_status_code arm_gic_irq_set_group( - rtems_vector_number vector, - gic_group group -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (bsp_interrupt_is_valid_vector(vector)) { - volatile gic_dist *dist = ARM_GIC_DIST; - - gic_id_set_group(dist, vector, group); - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -rtems_status_code arm_gic_irq_get_group( - rtems_vector_number vector, - gic_group *group -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (bsp_interrupt_is_valid_vector(vector)) { - volatile gic_dist *dist = ARM_GIC_DIST; - - *group = gic_id_get_group(dist, vector); - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -void bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0); - - gic_id_set_targets(dist, vector, targets); -} - -void bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - uint8_t targets = gic_id_get_targets(dist, vector); - - _Processor_mask_From_uint32_t(affinity, targets, 0); -} - -void arm_gic_trigger_sgi( - rtems_vector_number vector, - arm_gic_irq_software_irq_target_filter filter, - uint8_t targets -) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - - dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) - | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) -#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 - | GIC_DIST_ICDSGIR_NSATT -#endif - | GIC_DIST_ICDSGIR_SGIINTID(vector); -} diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h index a97191faca..d63fce32d1 100644 --- a/bsps/include/dev/irq/arm-gic-irq.h +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -122,10 +122,10 @@ void arm_interrupt_facility_set_exception_handler(void); void arm_interrupt_handler_dispatch(rtems_vector_number vector); /** - * This is the GICv3 interrupt dispatcher that is to be called from the + * This is the GICv1/GICv2/GICv3 interrupt dispatcher that is to be called from the * architecture-specific implementation of the IRQ handler. */ -void gicv3_interrupt_dispatch(void); +void gicvx_interrupt_dispatch(void); static inline uint32_t arm_gic_irq_processor_count(void) { diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c new file mode 100644 index 0000000000..cba8982764 --- /dev/null +++ b/bsps/shared/dev/irq/arm-gicv2.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +#include +#include +#include + +#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE) + +#define PRIORITY_DEFAULT 127 + +/* + * The following variants + * + * - GICv1 with Security Extensions, + * - GICv2 without Security Extensions, or + * - within Secure processor mode + * + * have the ability to assign group 0 or 1 to individual interrupts. Group + * 0 interrupts can be configured to raise an FIQ exception. This enables + * the use of NMIs with respect to RTEMS. + * + * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + * define. Use arm_gic_irq_set_group() to change the group of an + * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is + * defined). + */ +#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 +#define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE) +#define CPUIF_ICCICR \ + (GIC_CPUIF_ICCICR_CBPR | GIC_CPUIF_ICCICR_FIQ_EN \ + | GIC_CPUIF_ICCICR_ACK_CTL | GIC_CPUIF_ICCICR_ENABLE_GRP_1 \ + | GIC_CPUIF_ICCICR_ENABLE) +#else +#define DIST_ICDDCR GIC_DIST_ICDDCR_ENABLE +#define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE +#endif + +void gicvx_interrupt_dispatch(void) +{ + volatile gic_cpuif *cpuif = GIC_CPUIF; + uint32_t icciar = cpuif->icciar; + rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); + rtems_vector_number spurious = 1023; + + if (vector != spurious) { + arm_interrupt_handler_dispatch(vector); + + cpuif->icceoir = icciar; + } +} + +void bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); + + gic_id_enable(dist, vector); +} + +void bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); + + gic_id_disable(dist, vector); +} + +static inline uint32_t get_id_count(volatile gic_dist *dist) +{ + uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); + + id_count = 32 * (id_count + 1); + id_count = id_count <= 1020 ? id_count : 1020; + + return id_count; +} + +static void enable_fiq(void) +{ +#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + rtems_interrupt_level level; + + rtems_interrupt_local_disable(level); + level &= ~ARM_PSR_F; + rtems_interrupt_local_enable(level); +#endif +} + +rtems_status_code bsp_interrupt_facility_initialize(void) +{ + volatile gic_cpuif *cpuif = GIC_CPUIF; + volatile gic_dist *dist = ARM_GIC_DIST; + uint32_t id_count = get_id_count(dist); + uint32_t id; + + arm_interrupt_facility_set_exception_handler(); + + for (id = 0; id < id_count; id += 32) { +#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + dist->icdigr[id / 32] = 0xffffffff; +#endif + dist->icdicer[id / 32] = 0xffffffff; + } + + for (id = 0; id < id_count; ++id) { + gic_id_set_priority(dist, id, PRIORITY_DEFAULT); + } + + for (id = 32; id < id_count; ++id) { + gic_id_set_targets(dist, id, 0x01); + } + + cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); + cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); + cpuif->iccicr = CPUIF_ICCICR; + + dist->icddcr = GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE; + + enable_fiq(); + return RTEMS_SUCCESSFUL; +} + +#ifdef RTEMS_SMP +BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) +{ + volatile gic_cpuif *cpuif = GIC_CPUIF; + volatile gic_dist *dist = ARM_GIC_DIST; + uint32_t id; + + while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { + /* Wait */ + } + +#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + dist->icdigr[0] = 0xffffffff; +#endif + + /* Initialize Peripheral Private Interrupts (PPIs) */ + for (id = 0; id < 32; ++id) { + gic_id_set_priority(dist, id, PRIORITY_DEFAULT); + } + + cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); + cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); + cpuif->iccicr = CPUIF_ICCICR; + + enable_fiq(); +} +#endif + +rtems_status_code arm_gic_irq_set_priority( + rtems_vector_number vector, + uint8_t priority +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (bsp_interrupt_is_valid_vector(vector)) { + volatile gic_dist *dist = ARM_GIC_DIST; + + gic_id_set_priority(dist, vector, priority); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +rtems_status_code arm_gic_irq_get_priority( + rtems_vector_number vector, + uint8_t *priority +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (bsp_interrupt_is_valid_vector(vector)) { + volatile gic_dist *dist = ARM_GIC_DIST; + + *priority = gic_id_get_priority(dist, vector); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +rtems_status_code arm_gic_irq_set_group( + rtems_vector_number vector, + gic_group group +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (bsp_interrupt_is_valid_vector(vector)) { + volatile gic_dist *dist = ARM_GIC_DIST; + + gic_id_set_group(dist, vector, group); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +rtems_status_code arm_gic_irq_get_group( + rtems_vector_number vector, + gic_group *group +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (bsp_interrupt_is_valid_vector(vector)) { + volatile gic_dist *dist = ARM_GIC_DIST; + + *group = gic_id_get_group(dist, vector); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0); + + gic_id_set_targets(dist, vector, targets); +} + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + uint8_t targets = gic_id_get_targets(dist, vector); + + _Processor_mask_From_uint32_t(affinity, targets, 0); +} + +void arm_gic_trigger_sgi( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) + | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) +#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 + | GIC_DIST_ICDSGIR_NSATT +#endif + | GIC_DIST_ICDSGIR_SGIINTID(vector); +} diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index ad39872eb0..da19300b15 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -134,7 +134,7 @@ #define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE) #define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16)))) -void gicv3_interrupt_dispatch(void) +void gicvx_interrupt_dispatch(void) { uint32_t icciar = READ_SR(ICC_IAR1); rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index b2785988e0..22be647261 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -62,7 +62,8 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios-init.c diff --git a/c/src/lib/libbsp/arm/imx/Makefile.am b/c/src/lib/libbsp/arm/imx/Makefile.am index c9537a773d..caef3c6170 100644 --- a/c/src/lib/libbsp/arm/imx/Makefile.am +++ b/c/src/lib/libbsp/arm/imx/Makefile.am @@ -51,7 +51,8 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am index 77b7db4cca..d1597068ef 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am @@ -56,7 +56,8 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios-init.c diff --git a/c/src/lib/libbsp/arm/xen/Makefile.am b/c/src/lib/libbsp/arm/xen/Makefile.am index c8f7eb4f20..e01c33deb5 100644 --- a/c/src/lib/libbsp/arm/xen/Makefile.am +++ b/c/src/lib/libbsp/arm/xen/Makefile.am @@ -35,7 +35,8 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/arm-generic-tim librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c # irq librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # console librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xen/console/console.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 299e69c128..a4b9496630 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -55,7 +55,8 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index f689c2e294..11d6ab8039 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -55,7 +55,8 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/spec/build/bsps/aarch64/a53/obj.yml b/spec/build/bsps/aarch64/a53/obj.yml index b584a2413c..0d69b59416 100644 --- a/spec/build/bsps/aarch64/a53/obj.yml +++ b/spec/build/bsps/aarch64/a53/obj.yml @@ -30,7 +30,7 @@ source: - bsps/shared/start/sbrk.c - bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/irq/irq-default-handler.c -- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c +- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c diff --git a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml index abe3d7f490..c6732c4d47 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml @@ -128,7 +128,8 @@ source: - bsps/arm/shared/clock/clock-a9mpcore.c - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c -- bsps/arm/shared/irq/irq-gic.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c diff --git a/spec/build/bsps/arm/imx/bspimx.yml b/spec/build/bsps/arm/imx/bspimx.yml index 6b3cfdbb2e..5f448682ed 100644 --- a/spec/build/bsps/arm/imx/bspimx.yml +++ b/spec/build/bsps/arm/imx/bspimx.yml @@ -97,7 +97,8 @@ source: - bsps/arm/shared/clock/arm-generic-timer-aarch32.c - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c -- bsps/arm/shared/irq/irq-gic.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c diff --git a/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml b/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml index 8e4dd318f2..6233aae2f0 100644 --- a/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml +++ b/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml @@ -67,7 +67,8 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/arm/shared/fb/arm-pl111.c -- bsps/arm/shared/irq/irq-gic.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/serial/arm-pl050.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c diff --git a/spec/build/bsps/arm/xen/bspxen.yml b/spec/build/bsps/arm/xen/bspxen.yml index 59d3f8581e..3784315acd 100644 --- a/spec/build/bsps/arm/xen/bspxen.yml +++ b/spec/build/bsps/arm/xen/bspxen.yml @@ -63,7 +63,8 @@ source: - bsps/arm/shared/clock/arm-generic-timer-aarch32.c - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c -- bsps/arm/shared/irq/irq-gic.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/xen/console/console.c - bsps/arm/xen/start/bspstart.c diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml b/spec/build/bsps/arm/xilinx-zynq/obj.yml index 06e13e4ea1..c2dde615b8 100644 --- a/spec/build/bsps/arm/xilinx-zynq/obj.yml +++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml @@ -24,7 +24,8 @@ source: - bsps/arm/shared/clock/clock-a9mpcore.c - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c -- bsps/arm/shared/irq/irq-gic.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/xilinx-zynq/console/console-config.c - bsps/arm/xilinx-zynq/console/console-init.c diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml index 8c8013db24..92da7904c9 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml @@ -79,7 +79,8 @@ source: - bsps/arm/shared/clock/arm-generic-timer-aarch32.c - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c -- bsps/arm/shared/irq/irq-gic.c +- bsps/shared/dev/irq/arm-gicv2.c +- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/xilinx-zynqmp/console/console-config.c - bsps/arm/xilinx-zynqmp/start/bspreset.c -- cgit v1.2.3