From 9f3a08ef2de99714d679aecf6b1ecb4e11869424 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 22 Dec 2020 13:00:27 +0100 Subject: bsps: Use header file for GIC architecture support This avoids a function call overhead in the interrupt dispatching. Update #4202. --- bsps/aarch64/include/dev/irq/arm-gic-arch.h | 72 ++++++++++++++++++++++ bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c | 58 ----------------- bsps/arm/include/dev/irq/arm-gic-arch.h | 68 ++++++++++++++++++++ bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c | 56 ----------------- bsps/include/dev/irq/arm-gic-irq.h | 13 ---- bsps/shared/dev/irq/arm-gicv2.c | 1 + bsps/shared/dev/irq/arm-gicv3.c | 1 + c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 1 - c/src/lib/libbsp/arm/imx/Makefile.am | 1 - c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 1 - c/src/lib/libbsp/arm/xen/Makefile.am | 1 - c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 1 - c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 1 - spec/build/bsps/aarch64/a53/obj.yml | 1 - spec/build/bsps/aarch64/grp.yml | 1 + spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 - .../arm/altera-cyclone-v/bspalteracyclonev.yml | 1 - spec/build/bsps/arm/grp.yml | 1 + spec/build/bsps/arm/imx/bspimx.yml | 1 - .../bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 - spec/build/bsps/arm/xen/bspxen.yml | 1 - spec/build/bsps/arm/xilinx-zynq/obj.yml | 1 - .../bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 1 - 23 files changed, 144 insertions(+), 141 deletions(-) create mode 100644 bsps/aarch64/include/dev/irq/arm-gic-arch.h delete mode 100644 bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c create mode 100644 bsps/arm/include/dev/irq/arm-gic-arch.h delete mode 100644 bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h b/bsps/aarch64/include/dev/irq/arm-gic-arch.h new file mode 100644 index 0000000000..c3332faf42 --- /dev/null +++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Shared + * + * @brief AArch64-specific ARM GICv3 handlers. + */ + +/* + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H +#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector) +{ + uint32_t interrupt_level = _CPU_ISR_Get_level(); + AArch64_interrupt_enable(1); + bsp_interrupt_handler_dispatch(vector); + _CPU_ISR_Set_level(interrupt_level); +} + +static inline void arm_interrupt_facility_set_exception_handler(void) +{ + AArch64_set_exception_handler( + AARCH64_EXCEPTION_SPx_IRQ, + _AArch64_Exception_interrupt_no_nest + ); + AArch64_set_exception_handler( + AARCH64_EXCEPTION_SP0_IRQ, + _AArch64_Exception_interrupt_nest + ); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */ diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c b/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c deleted file mode 100644 index 4c26ec3c2b..0000000000 --- a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup RTEMSBSPsAArch64Shared - * - * @brief AArch64-specific ARM GICv3 handlers. - */ - -/* - * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) - * Written by Kinsey Moore - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -void arm_interrupt_handler_dispatch(rtems_vector_number vector) -{ - uint32_t interrupt_level = _CPU_ISR_Get_level(); - AArch64_interrupt_enable(1); - bsp_interrupt_handler_dispatch(vector); - _CPU_ISR_Set_level(interrupt_level); -} - -void arm_interrupt_facility_set_exception_handler(void) -{ - AArch64_set_exception_handler( - AARCH64_EXCEPTION_SPx_IRQ, - _AArch64_Exception_interrupt_no_nest - ); - AArch64_set_exception_handler( - AARCH64_EXCEPTION_SP0_IRQ, - _AArch64_Exception_interrupt_nest - ); -} diff --git a/bsps/arm/include/dev/irq/arm-gic-arch.h b/bsps/arm/include/dev/irq/arm-gic-arch.h new file mode 100644 index 0000000000..fe981da4f7 --- /dev/null +++ b/bsps/arm/include/dev/irq/arm-gic-arch.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMShared + * + * @brief ARM-specific IRQ handlers. + */ + +/* + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_DEV_IRQ_ARM_GIC_ARM_H +#define _RTEMS_DEV_IRQ_ARM_GIC_ARM_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector) +{ + uint32_t psr = _ARMV4_Status_irq_enable(); + bsp_interrupt_handler_dispatch(vector); + + _ARMV4_Status_restore(psr); +} + +static inline void arm_interrupt_facility_set_exception_handler(void) +{ + arm_cp15_set_exception_handler( + ARM_EXCEPTION_IRQ, + _ARMV4_Exception_interrupt + ); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_DEV_IRQ_ARM_GIC_ARM_H */ diff --git a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c b/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c deleted file mode 100644 index 7c0462d04d..0000000000 --- a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup RTEMSBSPsARMShared - * - * @brief ARM-specific IRQ handlers. - */ - -/* - * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) - * Written by Kinsey Moore - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -void arm_interrupt_handler_dispatch(rtems_vector_number vector) -{ - uint32_t psr = _ARMV4_Status_irq_enable(); - bsp_interrupt_handler_dispatch(vector); - - _ARMV4_Status_restore(psr); -} - -void arm_interrupt_facility_set_exception_handler(void) -{ - arm_cp15_set_exception_handler( - ARM_EXCEPTION_IRQ, - _ARMV4_Exception_interrupt - ); -} diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h index 5270331624..5ce9d54684 100644 --- a/bsps/include/dev/irq/arm-gic-irq.h +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -97,19 +97,6 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq( return sc; } -/** - * This architecture-specific function sets the exception vector for handling - * IRQs. - */ -void arm_interrupt_facility_set_exception_handler(void); - -/** - * This architecture-specific function dispatches a triggered IRQ. - * - * @param[in] vector The vector on which the IRQ occurred. - */ -void arm_interrupt_handler_dispatch(rtems_vector_number vector); - uint32_t arm_gic_irq_processor_count(void); void arm_gic_irq_initialize_secondary_cpu(void); diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c index 74989a4de5..c29cae1d97 100644 --- a/bsps/shared/dev/irq/arm-gicv2.c +++ b/bsps/shared/dev/irq/arm-gicv2.c @@ -13,6 +13,7 @@ */ #include +#include #include #include diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index 77128adb5b..113b840068 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -26,6 +26,7 @@ */ #include +#include #include #include diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 22be647261..314808ee6c 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -63,7 +63,6 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios-init.c diff --git a/c/src/lib/libbsp/arm/imx/Makefile.am b/c/src/lib/libbsp/arm/imx/Makefile.am index caef3c6170..fc66b7964e 100644 --- a/c/src/lib/libbsp/arm/imx/Makefile.am +++ b/c/src/lib/libbsp/arm/imx/Makefile.am @@ -52,7 +52,6 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am index d1597068ef..19a8529d9c 100644 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am +++ b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am @@ -57,7 +57,6 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios-init.c diff --git a/c/src/lib/libbsp/arm/xen/Makefile.am b/c/src/lib/libbsp/arm/xen/Makefile.am index e01c33deb5..c1a6251e86 100644 --- a/c/src/lib/libbsp/arm/xen/Makefile.am +++ b/c/src/lib/libbsp/arm/xen/Makefile.am @@ -36,7 +36,6 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c # irq librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # console librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xen/console/console.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index a4b9496630..8804dc40da 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -56,7 +56,6 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am index 11d6ab8039..21db56a0ea 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -56,7 +56,6 @@ endif # IRQ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c -librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c # Console librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c diff --git a/spec/build/bsps/aarch64/a53/obj.yml b/spec/build/bsps/aarch64/a53/obj.yml index 0d69b59416..235191742e 100644 --- a/spec/build/bsps/aarch64/a53/obj.yml +++ b/spec/build/bsps/aarch64/a53/obj.yml @@ -30,7 +30,6 @@ source: - bsps/shared/start/sbrk.c - bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/irq/irq-default-handler.c -- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml index 1b8dc1c629..a6bc0d5a31 100644 --- a/spec/build/bsps/aarch64/grp.yml +++ b/spec/build/bsps/aarch64/grp.yml @@ -14,6 +14,7 @@ install: - bsps/include/dev/clock/arm-generic-timer.h - destination: ${BSP_INCLUDEDIR}/dev/irq source: + - bsps/aarch64/include/dev/irq/arm-gic-arch.h - bsps/include/dev/irq/arm-gic-irq.h - bsps/include/dev/irq/arm-gic-regs.h - bsps/include/dev/irq/arm-gic-tm27.h diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml index 2ca4ef093b..c1a859af85 100644 --- a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml @@ -29,7 +29,6 @@ source: - bsps/shared/start/bspreset-arm-psci.c - bsps/shared/start/sbrk.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c - bsps/shared/irq/irq-default-handler.c - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c diff --git a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml index c6732c4d47..b4b43ab106 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/bspalteracyclonev.yml @@ -129,7 +129,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml index 408288044f..dbd21638fd 100644 --- a/spec/build/bsps/arm/grp.yml +++ b/spec/build/bsps/arm/grp.yml @@ -37,6 +37,7 @@ install: - bsps/arm/include/bsp/start.h - destination: ${BSP_INCLUDEDIR}/dev/irq source: + - bsps/arm/include/dev/irq/arm-gic-arch.h - bsps/include/dev/irq/arm-gic-irq.h - bsps/include/dev/irq/arm-gic-regs.h - bsps/include/dev/irq/arm-gic-tm27.h diff --git a/spec/build/bsps/arm/imx/bspimx.yml b/spec/build/bsps/arm/imx/bspimx.yml index 93628f0368..386a769bc0 100644 --- a/spec/build/bsps/arm/imx/bspimx.yml +++ b/spec/build/bsps/arm/imx/bspimx.yml @@ -97,7 +97,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c diff --git a/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml b/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml index 6233aae2f0..2eb06e5348 100644 --- a/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml +++ b/spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml @@ -68,7 +68,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/arm/shared/fb/arm-pl111.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/serial/arm-pl050.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/shared/dev/btimer/btimer-stub.c diff --git a/spec/build/bsps/arm/xen/bspxen.yml b/spec/build/bsps/arm/xen/bspxen.yml index 1a3db8d172..c8de39a4f7 100644 --- a/spec/build/bsps/arm/xen/bspxen.yml +++ b/spec/build/bsps/arm/xen/bspxen.yml @@ -64,7 +64,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/xen/console/console.c - bsps/arm/xen/start/bspstart.c diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml b/spec/build/bsps/arm/xilinx-zynq/obj.yml index c2dde615b8..6602b20a03 100644 --- a/spec/build/bsps/arm/xilinx-zynq/obj.yml +++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml @@ -25,7 +25,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/xilinx-zynq/console/console-config.c - bsps/arm/xilinx-zynq/console/console-init.c diff --git a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml index b8cc1c043c..51d3268e99 100644 --- a/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml +++ b/spec/build/bsps/arm/xilinx-zynqmp/bspxilinxzynqmp.yml @@ -82,7 +82,6 @@ source: - bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c - bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/xilinx-zynqmp/console/console-config.c - bsps/arm/xilinx-zynqmp/start/bspreset.c -- cgit v1.2.3