From 7c3b0df10752cc4bdd1175f5b16fd0978763ff46 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 22 Jun 2018 13:30:49 +0200
Subject: riscv: Implement ISR set/get level

Fix prototypes.

Update #3433.
---
 cpukit/score/cpu/riscv/cpu.c                     | 12 +++++-------
 cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 15 +++++++++++++--
 2 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c
index fbdb4c5238..7c14a8bffd 100644
--- a/cpukit/score/cpu/riscv/cpu.c
+++ b/cpukit/score/cpu/riscv/cpu.c
@@ -59,15 +59,13 @@ void _CPU_Initialize(void)
   /* Do nothing */
 }
 
-void _CPU_ISR_Set_level(unsigned long level)
+uint32_t _CPU_ISR_Get_level( void )
 {
-  /* Do nothing */
-}
+  if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) {
+    return 0;
+  }
 
-unsigned long  _CPU_ISR_Get_level( void )
-{
-  /* Do nothing */
-  return 0;
+  return 1;
 }
 
 void _CPU_ISR_install_raw_handler(
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 1e72dd3709..d70db39b85 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -187,9 +187,20 @@ RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
   return ( level & MSTATUS_MIE ) != 0;
 }
 
-void _CPU_ISR_Set_level( unsigned long level );
+RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level )
+{
+  if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
+    __asm__ volatile (
+      "csrrs zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE )
+    );
+  } else {
+    __asm__ volatile (
+      "csrrc zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE )
+    );
+  }
+}
 
-unsigned long _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
-- 
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