From 694e79a0b778e20b70c04e024ec43e76e563cc61 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 28 Jun 2018 08:20:47 +0200 Subject: riscv: Add TLS support Update #3433. --- cpukit/score/cpu/riscv/riscv-context-initialize.c | 8 ++++++++ cpukit/score/cpu/riscv/riscv-context-switch.S | 1 + 2 files changed, 9 insertions(+) diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c index d293e24b00..9f51d05008 100644 --- a/cpukit/score/cpu/riscv/riscv-context-initialize.c +++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c @@ -35,6 +35,7 @@ #include #include +#include void _CPU_Context_Initialize( Context_Control *context, @@ -54,4 +55,11 @@ void _CPU_Context_Initialize( context->ra = (uintptr_t) entry_point; context->sp = (uintptr_t) stack; context->isr_dispatch_disable = 0; + + if ( tls_area != NULL ) { + void *tls_block; + + tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area ); + context->tp = (uintptr_t) tls_block; + } } diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 1b82e2aa79..3626155409 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -67,6 +67,7 @@ SYM(_CPU_Context_switch): LREG ra, RISCV_CONTEXT_RA(a1) LREG sp, RISCV_CONTEXT_SP(a1) + LREG tp, RISCV_CONTEXT_TP(a1) LREG s0, RISCV_CONTEXT_S0(a1) LREG s1, RISCV_CONTEXT_S1(a1) LREG s2, RISCV_CONTEXT_S2(a1) -- cgit v1.2.3