From 677d5167ba6605036032a32744a904947f6a0dc2 Mon Sep 17 00:00:00 2001 From: Jeff Kubascik Date: Wed, 10 Apr 2019 19:38:54 -0400 Subject: bsp/xilinx-zynqmp: Stub out Xilinx MPSoC BSP Source files were copied from xilinx-zynq. Update #3682. --- bsps/arm/xilinx-zynqmp/README | 13 +++ bsps/arm/xilinx-zynqmp/config/xilinx_zynq.inc | 10 ++ bsps/arm/xilinx-zynqmp/console/console-config.c | 75 +++++++++++++ bsps/arm/xilinx-zynqmp/headers.am | 15 +++ bsps/arm/xilinx-zynqmp/include/bsp.h | 99 +++++++++++++++++ bsps/arm/xilinx-zynqmp/include/bsp/irq.h | 128 +++++++++++++++++++++ bsps/arm/xilinx-zynqmp/include/tm27.h | 49 ++++++++ bsps/arm/xilinx-zynqmp/start/bsp_specs | 9 ++ bsps/arm/xilinx-zynqmp/start/bspreset.c | 43 +++++++ bsps/arm/xilinx-zynqmp/start/bspsmp.c | 52 +++++++++ bsps/arm/xilinx-zynqmp/start/bspstart.c | 45 ++++++++ bsps/arm/xilinx-zynqmp/start/bspstarthooks.c | 89 +++++++++++++++ bsps/arm/xilinx-zynqmp/start/bspstartmmu.c | 75 +++++++++++++ bsps/arm/xilinx-zynqmp/start/linkcmds.in | 36 ++++++ c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am | 86 ++++++++++++++ c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac | 142 ++++++++++++++++++++++++ 16 files changed, 966 insertions(+) create mode 100644 bsps/arm/xilinx-zynqmp/README create mode 100644 bsps/arm/xilinx-zynqmp/config/xilinx_zynq.inc create mode 100644 bsps/arm/xilinx-zynqmp/console/console-config.c create mode 100644 bsps/arm/xilinx-zynqmp/headers.am create mode 100644 bsps/arm/xilinx-zynqmp/include/bsp.h create mode 100644 bsps/arm/xilinx-zynqmp/include/bsp/irq.h create mode 100644 bsps/arm/xilinx-zynqmp/include/tm27.h create mode 100644 bsps/arm/xilinx-zynqmp/start/bsp_specs create mode 100644 bsps/arm/xilinx-zynqmp/start/bspreset.c create mode 100644 bsps/arm/xilinx-zynqmp/start/bspsmp.c create mode 100644 bsps/arm/xilinx-zynqmp/start/bspstart.c create mode 100644 bsps/arm/xilinx-zynqmp/start/bspstarthooks.c create mode 100644 bsps/arm/xilinx-zynqmp/start/bspstartmmu.c create mode 100644 bsps/arm/xilinx-zynqmp/start/linkcmds.in create mode 100644 c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am create mode 100644 c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac diff --git a/bsps/arm/xilinx-zynqmp/README b/bsps/arm/xilinx-zynqmp/README new file mode 100644 index 0000000000..eef9159926 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/README @@ -0,0 +1,13 @@ +Tested only on Qemu. + +git clone git://git.qemu.org/qemu.git qemu +cd qemu +git checkout 1b0d3845b454eaaac0b2064c78926ca4d739a080 +mkdir build +cd build +../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu +make +make install +export PATH="$PATH:/opt/qemu/bin" + +qemu-system-arm -no-reboot -serial null -serial mon:stdio -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe diff --git a/bsps/arm/xilinx-zynqmp/config/xilinx_zynq.inc b/bsps/arm/xilinx-zynqmp/config/xilinx_zynq.inc new file mode 100644 index 0000000000..59c18f7c95 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/config/xilinx_zynq.inc @@ -0,0 +1,10 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 + +CFLAGS_OPTIMIZE_V ?= -O2 -g +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections + +LDFLAGS = -Wl,--gc-sections diff --git a/bsps/arm/xilinx-zynqmp/console/console-config.c b/bsps/arm/xilinx-zynqmp/console/console-config.c new file mode 100644 index 0000000000..6ab9e1e015 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/console/console-config.c @@ -0,0 +1,75 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013, 2017 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include + +zynq_uart_context zynq_uart_instances[2] = { + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ), + .regs = (volatile struct zynq_uart *) 0xe0000000, + .irq = ZYNQ_IRQ_UART_0 + }, { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ), + .regs = (volatile struct zynq_uart *) 0xe0001000, + .irq = ZYNQ_IRQ_UART_1 + } +}; + +rtems_status_code console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + size_t i; + + rtems_termios_initialize(); + + for (i = 0; i < RTEMS_ARRAY_SIZE(zynq_uart_instances); ++i) { + char uart[] = "/dev/ttySX"; + + uart[sizeof(uart) - 2] = (char) ('0' + i); + rtems_termios_device_install( + &uart[0], + &zynq_uart_handler, + NULL, + &zynq_uart_instances[i].base + ); + + if (i == BSP_CONSOLE_MINOR) { + link(&uart[0], CONSOLE_DEVICE_NAME); + } + } + + return RTEMS_SUCCESSFUL; +} diff --git a/bsps/arm/xilinx-zynqmp/headers.am b/bsps/arm/xilinx-zynqmp/headers.am new file mode 100644 index 0000000000..ed7061964c --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/arm/include/bsp/zynq-uart-regs.h +include_bsp_HEADERS += ../../../../../../bsps/arm/include/bsp/zynq-uart.h diff --git a/bsps/arm/xilinx-zynqmp/include/bsp.h b/bsps/arm/xilinx-zynqmp/include/bsp.h new file mode 100644 index 0000000000..6c2759ce50 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/include/bsp.h @@ -0,0 +1,99 @@ +/** + * @file + * @ingroup RTEMSBSPsARMZynq + * @brief Global BSP definitions. + */ + +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013, 2014 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H +#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H + +/** + * @defgroup RTEMSBSPsARMZynq Xilinx Zynq + * + * @ingroup RTEMSBSPsARM + * + * @brief Xilinx Zynq Board Support Package. + * + * @{ + */ + +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000 + +#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100 + +#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200 + +#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600 + +#define BSP_ARM_GIC_DIST_BASE 0xf8f01000 + +#define BSP_ARM_L2C_310_BASE 0xf8f02000 + +#define BSP_ARM_L2C_310_ID 0x410000c8 + +extern zynq_uart_context zynq_uart_instances[2]; + +/** + * @brief Zynq specific set up of the MMU. + * + * Provide in the application to override + * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1 + * AXI ports. You should add the specific regions that map into your + * PL rather than just open the whole of the GP[01] address space up. + */ +BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void); + +uint32_t zynq_clock_cpu_1x(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +/** @} */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h new file mode 100644 index 0000000000..edea29b7df --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h @@ -0,0 +1,128 @@ +/** + * @file + * @ingroup zynq_interrupt + * @brief Interrupt definitions. + */ + +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H +#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H + +#ifndef ASM + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup zynq_interrupt Interrupt Support + * @ingroup RTEMSBSPsARMZynq + * @brief Interrupt Support + * @{ + */ + +#define ZYNQ_IRQ_CPU_0 32 +#define ZYNQ_IRQ_CPU_1 33 +#define ZYNQ_IRQ_L2_CACHE 34 +#define ZYNQ_IRQ_OCM 35 +#define ZYNQ_IRQ_PMU_0 37 +#define ZYNQ_IRQ_PMU_1 38 +#define ZYNQ_IRQ_XADC 39 +#define ZYNQ_IRQ_DVI 40 +#define ZYNQ_IRQ_SWDT 41 +#define ZYNQ_IRQ_TTC_0_0 42 +#define ZYNQ_IRQ_TTC_1_0 43 +#define ZYNQ_IRQ_TTC_2_0 44 +#define ZYNQ_IRQ_DMAC_ABORT 45 +#define ZYNQ_IRQ_DMAC_0 46 +#define ZYNQ_IRQ_DMAC_1 47 +#define ZYNQ_IRQ_DMAC_2 48 +#define ZYNQ_IRQ_DMAC_3 49 +#define ZYNQ_IRQ_SMC 50 +#define ZYNQ_IRQ_QUAD_SPI 51 +#define ZYNQ_IRQ_GPIO 52 +#define ZYNQ_IRQ_USB_0 53 +#define ZYNQ_IRQ_ETHERNET_0 54 +#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 +#define ZYNQ_IRQ_SDIO_0 56 +#define ZYNQ_IRQ_I2C_0 57 +#define ZYNQ_IRQ_SPI_0 58 +#define ZYNQ_IRQ_UART_0 59 +#define ZYNQ_IRQ_CAN_0 60 +#define ZYNQ_IRQ_FPGA_0 61 +#define ZYNQ_IRQ_FPGA_1 62 +#define ZYNQ_IRQ_FPGA_2 63 +#define ZYNQ_IRQ_FPGA_3 64 +#define ZYNQ_IRQ_FPGA_4 65 +#define ZYNQ_IRQ_FPGA_5 66 +#define ZYNQ_IRQ_FPGA_6 67 +#define ZYNQ_IRQ_FPGA_7 68 +#define ZYNQ_IRQ_TTC_0_1 69 +#define ZYNQ_IRQ_TTC_1_1 70 +#define ZYNQ_IRQ_TTC_2_1 71 +#define ZYNQ_IRQ_DMAC_4 72 +#define ZYNQ_IRQ_DMAC_5 73 +#define ZYNQ_IRQ_DMAC_6 74 +#define ZYNQ_IRQ_DMAC_7 75 +#define ZYNQ_IRQ_USB_1 76 +#define ZYNQ_IRQ_ETHERNET_1 77 +#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 +#define ZYNQ_IRQ_SDIO_1 79 +#define ZYNQ_IRQ_I2C_1 80 +#define ZYNQ_IRQ_SPI_1 81 +#define ZYNQ_IRQ_UART_1 82 +#define ZYNQ_IRQ_CAN_1 83 +#define ZYNQ_IRQ_FPGA_8 84 +#define ZYNQ_IRQ_FPGA_9 85 +#define ZYNQ_IRQ_FPGA_10 86 +#define ZYNQ_IRQ_FPGA_11 87 +#define ZYNQ_IRQ_FPGA_12 88 +#define ZYNQ_IRQ_FPGA_13 89 +#define ZYNQ_IRQ_FPGA_14 90 +#define ZYNQ_IRQ_FPGA_15 91 +#define ZYNQ_IRQ_PARITY 92 + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 92 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ diff --git a/bsps/arm/xilinx-zynqmp/include/tm27.h b/bsps/arm/xilinx-zynqmp/include/tm27.h new file mode 100644 index 0000000000..885b97a30c --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/include/tm27.h @@ -0,0 +1,49 @@ +/** + * @file + * @ingroup zynq_tm27 + * @brief Interrupt mechanisms for tm27 test. + */ + +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/** + * @defgroup zynq_tm27 TM27 Test Support + * @ingroup RTEMSBSPsARMZynq + * @brief Interrupt Mechanisms for tm27 test + */ + +#include + +#endif /* __tm27_h */ diff --git a/bsps/arm/xilinx-zynqmp/start/bsp_specs b/bsps/arm/xilinx-zynqmp/start/bsp_specs new file mode 100644 index 0000000000..47dd31d46b --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/bsp_specs @@ -0,0 +1,9 @@ +%rename endfile old_endfile +%rename startfile old_startfile + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}} + +*endfile: +%{!qrtems: %(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s} diff --git a/bsps/arm/xilinx-zynqmp/start/bspreset.c b/bsps/arm/xilinx-zynqmp/start/bspreset.c new file mode 100644 index 0000000000..e0c81ca2ef --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/bspreset.c @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void bsp_reset(void) +{ + volatile uint32_t *slcr_unlock = (volatile uint32_t *) 0xf8000008; + volatile uint32_t *pss_rst_ctrl = (volatile uint32_t *) 0xf8000200; + + zynq_uart_reset_tx_flush(&zynq_uart_instances[BSP_CONSOLE_MINOR]); + + while (true) { + *slcr_unlock = 0xdf0d; + *pss_rst_ctrl = 0x1; + } +} diff --git a/bsps/arm/xilinx-zynqmp/start/bspsmp.c b/bsps/arm/xilinx-zynqmp/start/bspsmp.c new file mode 100644 index 0000000000..fdb7f85ba6 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/bspsmp.c @@ -0,0 +1,52 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2014 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include + +bool _CPU_SMP_Start_processor(uint32_t cpu_index) +{ + /* + * Enable the second CPU. + */ + if (cpu_index != 0) { + volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL; + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); + *kick_address = (uint32_t) _start; + _ARM_Data_synchronization_barrier(); + _ARM_Instruction_synchronization_barrier(); + _ARM_Send_event(); + } + + /* + * Wait for secondary processor to complete its basic initialization so that + * we can enable the unified L2 cache. + */ + return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); +} diff --git a/bsps/arm/xilinx-zynqmp/start/bspstart.c b/bsps/arm/xilinx-zynqmp/start/bspstart.c new file mode 100644 index 0000000000..68b0ef0b03 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/bspstart.c @@ -0,0 +1,45 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013, 2015 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +__attribute__ ((weak)) uint32_t zynq_clock_cpu_1x(void) +{ + return ZYNQ_CLOCK_CPU_1X; +} + +void bsp_start(void) +{ + bsp_interrupt_initialize(); + rtems_cache_coherent_add_area( + bsp_section_nocacheheap_begin, + (uintptr_t) bsp_section_nocacheheap_size + ); +} diff --git a/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c new file mode 100644 index 0000000000..a0f0fbacf6 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/bspstarthooks.c @@ -0,0 +1,89 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013, 2014 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION + +#include +#include +#include +#include + +BSP_START_TEXT_SECTION void bsp_start_hook_0(void) +{ + uint32_t sctlr_val; + + sctlr_val = arm_cp15_get_control(); + + /* + * Current U-boot loader seems to start kernel image + * with I and D caches on and MMU enabled. + * If RTEMS application image finds that cache is on + * during startup then disable caches. + */ + if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) { + if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) { + /* + * If the data cache is on then ensure that it is clean + * before switching off to be extra carefull. + */ + arm_cp15_data_cache_clean_all_levels(); + } + arm_cp15_flush_prefetch_buffer(); + sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A ); + arm_cp15_set_control( sctlr_val ); + } + arm_cp15_instruction_cache_invalidate(); + /* + * The care should be taken there that no shared levels + * are invalidated by secondary CPUs in SMP case. + * It is not problem on Zynq because level of coherency + * is L1 only and higher level is not maintained and seen + * by CP15. So no special care to limit levels on the secondary + * are required there. + */ + arm_cp15_data_cache_invalidate_all_levels(); + arm_cp15_branch_predictor_invalidate_all(); + arm_cp15_tlb_invalidate(); + arm_cp15_flush_prefetch_buffer(); + arm_a9mpcore_start_hook_0(); +} + +BSP_START_TEXT_SECTION void bsp_start_hook_1(void) +{ + arm_a9mpcore_start_hook_1(); + bsp_start_copy_sections(); + zynq_setup_mmu_and_cache(); + +#if !defined(RTEMS_SMP) \ + && (defined(BSP_DATA_CACHE_ENABLED) \ + || defined(BSP_INSTRUCTION_CACHE_ENABLED)) + /* Enable unified L2 cache */ + rtems_cache_enable_data(); +#endif + + bsp_start_clear_bss(); +} diff --git a/bsps/arm/xilinx-zynqmp/start/bspstartmmu.c b/bsps/arm/xilinx-zynqmp/start/bspstartmmu.c new file mode 100644 index 0000000000..c18f8623f7 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/bspstartmmu.c @@ -0,0 +1,75 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2013 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION + +#include +#include +#include +#include + +BSP_START_DATA_SECTION static const arm_cp15_start_section_config +zynq_mmu_config_table[] = { + ARMV7_CP15_START_DEFAULT_SECTIONS, +#if defined(RTEMS_SMP) + { + .begin = 0xffff0000U, + .end = 0xffffffffU, + .flags = ARMV7_MMU_DEVICE + }, +#endif + { + .begin = 0xe0000000U, + .end = 0xe0200000U, + .flags = ARMV7_MMU_DEVICE + }, { + .begin = 0xf8000000U, + .end = 0xf9000000U, + .flags = ARMV7_MMU_DEVICE + } +}; + +/* + * Make weak and let the user override. + */ +BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) __attribute__ ((weak)); + +BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) +{ + uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache( + ARM_CP15_CTRL_A, + ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z + ); + + arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( + ctrl, + (uint32_t *) bsp_translation_table_base, + ARM_MMU_DEFAULT_CLIENT_DOMAIN, + &zynq_mmu_config_table[0], + RTEMS_ARRAY_SIZE(zynq_mmu_config_table) + ); +} diff --git a/bsps/arm/xilinx-zynqmp/start/linkcmds.in b/bsps/arm/xilinx-zynqmp/start/linkcmds.in new file mode 100644 index 0000000000..b56309bf37 --- /dev/null +++ b/bsps/arm/xilinx-zynqmp/start/linkcmds.in @@ -0,0 +1,36 @@ +MEMORY { + RAM_INT_0 : ORIGIN = @ZYNQ_RAM_INT_0_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_0_LENGTH@ + RAM_INT_1 : ORIGIN = @ZYNQ_RAM_INT_1_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_1_LENGTH@ + RAM_MMU : ORIGIN = @ZYNQ_RAM_MMU@, LENGTH = @ZYNQ_RAM_MMU_LENGTH@ + RAM : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@ + NOCACHE : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@ +} + +REGION_ALIAS ("REGION_START", RAM); +REGION_ALIAS ("REGION_VECTOR", RAM); +REGION_ALIAS ("REGION_TEXT", RAM); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_RODATA", RAM); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM); +REGION_ALIAS ("REGION_DATA", RAM); +REGION_ALIAS ("REGION_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_TEXT", RAM); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_DATA", RAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_BSS", RAM); +REGION_ALIAS ("REGION_WORK", RAM); +REGION_ALIAS ("REGION_STACK", RAM); +REGION_ALIAS ("REGION_NOCACHE", NOCACHE); +REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE); + +bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; + +bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; + +bsp_vector_table_in_start_section = 1; + +bsp_translation_table_base = ORIGIN (RAM_MMU); +bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU); + +INCLUDE linkcmds.armv4 diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am new file mode 100644 index 0000000000..7b4e4aea94 --- /dev/null +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am @@ -0,0 +1,86 @@ +## +# +# @file +# +# @brief Makefile of LibBSP for the Xilinx Zynq platform. +# + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am +include $(top_srcdir)/../../bsp.am + +dist_project_lib_DATA = ../../../../../../bsps/arm/xilinx-zynq/start/bsp_specs + +############################################################################### +# Header # +############################################################################### + +############################################################################### +# Data # +############################################################################### + +start.$(OBJEXT): ../../../../../../bsps/arm/shared/start/start.S + $(CPPASCOMPILE) -o $@ -c $< +project_lib_DATA = start.$(OBJEXT) + +project_lib_DATA += linkcmds + +############################################################################### +# LibBSP # +############################################################################### + +project_lib_LIBRARIES = librtemsbsp.a + +librtemsbsp_a_SOURCES = + +# Shared +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/getentropy/getentropy-cpucounter.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspfatal-default.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-default.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/sbrk.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-stub.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/stackalloc.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/start/bsp-start-memcpy.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c + +# Startup +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspreset.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspstart.c +if HAS_SMP +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/start/arm-a9mpcore-smp.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspsmp.c +endif + +# IRQ +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-gic.c + +# Console +librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/console-config.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/debug-console.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart.c + +# Clock +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/clock/clock-a9mpcore.c + +# I2C +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c + +# Cache +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c + +# Start hooks +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspstarthooks.c +librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/start/bspstartmmu.c + +############################################################################### +# Special Rules # +############################################################################### + + +include $(srcdir)/../../../../../../bsps/shared/irq-sources.am +include $(srcdir)/../../../../../../bsps/shared/shared-sources.am +include $(srcdir)/../../../../../../bsps/arm/xilinx-zynq/headers.am diff --git a/c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac b/c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac new file mode 100644 index 0000000000..f58b737b1b --- /dev/null +++ b/c/src/lib/libbsp/arm/xilinx-zynqmp/configure.ac @@ -0,0 +1,142 @@ +## +# +# @file +# +# @brief Configure script of LibBSP for the Xilinx Zynq platform. +# + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) +RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + + + +RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) + +RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[]) +RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) + +RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[]) +RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) + +RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U]) +RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U]) +RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) +RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) + +RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zc702*],[50000000UL]) +RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[xilinx_zynq_zedboard*],[50000000UL]) +RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_UART],[*],[50000000UL]) +RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_UART],[Zynq UART clock frequency in Hz]) + +RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zc702*],[111111111U]) +RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[xilinx_zynq_zedboard*],[111111111U]) +RTEMS_BSPOPTS_SET([ZYNQ_CLOCK_CPU_1X],[*],[111111111U]) +RTEMS_BSPOPTS_HELP([ZYNQ_CLOCK_CPU_1X],[Zynq cpu_1x clock frequency in Hz]) + +USE_FAST_IDLE=0 +AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], [USE_FAST_IDLE=1]) + +RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[${USE_FAST_IDLE}]) +RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE], +[This sets a mode where the time runs as fast as possible when a clock ISR +occurs while the IDLE thread is executing. This can significantly reduce +simulation times.]) + +RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device]) + +RTEMS_BSPOPTS_SET([ZYNQ_CONSOLE_USE_INTERRUPTS],[*],[1]) +RTEMS_BSPOPTS_HELP([ZYNQ_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)]) + +# +# Zynq Memory map can be controlled from the configure command line. Use ... +# +# ..../configure --target=arm-rtems4.11 ... BSP_ZYNQ_RAM_LENGTH=256M +# +RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_a9_qemu],[256M]) +RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc702],[1024M]) +RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zc706],[1024M]) +RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[xilinx_zynq_zedboard],[512M]) +RTEMS_BSPOPTS_SET([BSP_ZYNQ_RAM_LENGTH],[*],[256M]) +RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length]) + +RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M]) +RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region]) + +AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu], + [ZYNQ_RAM_ORIGIN="0x00000000" + ZYNQ_RAM_MMU="0x0fffc000" + ZYNQ_RAM_MMU_LENGTH="16k" + ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}" + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k" + ZYNQ_RAM_INT_0_ORIGIN="0x00000000" + ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" + ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" + ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + +AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702], + [ZYNQ_RAM_ORIGIN="0x00100000" + ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" + ZYNQ_RAM_MMU_LENGTH="16k" + ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" + ZYNQ_RAM_INT_0_ORIGIN="0x00000000" + ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" + ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" + ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + +AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706], + [ZYNQ_RAM_ORIGIN="0x00400000" + ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" + ZYNQ_RAM_MMU_LENGTH="16k" + ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k" + ZYNQ_RAM_INT_0_ORIGIN="0x00000000" + ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" + ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" + ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + +AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard], + [ZYNQ_RAM_ORIGIN="0x00100000" + ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}" + ZYNQ_RAM_MMU_LENGTH="16k" + ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000" + ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k" + ZYNQ_RAM_INT_0_ORIGIN="0x00000000" + ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k" + ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000" + ZYNQ_RAM_INT_1_LENGTH="64k - 512"]) + +AC_DEFUN([ZYNQ_LINKCMD],[ +AC_ARG_VAR([$1],[$2; default $3])dnl +[$1]=[$]{[$1]:-[$3]} +]) + +ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN],[normal RAM region origin],[${ZYNQ_RAM_ORIGIN}]) +ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH],[normal RAM region length],[${BSP_ZYNQ_RAM_LENGTH}]) +ZYNQ_LINKCMD([ZYNQ_RAM_MMU],[MMU region origin],[${ZYNQ_RAM_MMU}]) +ZYNQ_LINKCMD([ZYNQ_RAM_MMU_LENGTH],[MMU region length],[${ZYNQ_RAM_MMU_LENGTH}]) +ZYNQ_LINKCMD([ZYNQ_RAM_ORIGIN_AVAILABLE],[origin of available RAM],[${ZYNQ_RAM_ORIGIN_AVAILABLE}]) +ZYNQ_LINKCMD([ZYNQ_RAM_LENGTH_AVAILABLE],[length of available RAM],[${ZYNQ_RAM_LENGTH_AVAILABLE}]) +ZYNQ_LINKCMD([ZYNQ_RAM_NOCACHE_LENGTH],[length of nocache RAM region],[${BSP_ZYNQ_NOCACHE_LENGTH}]) +ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_ORIGIN],[internal 0 RAM region origin],[${ZYNQ_RAM_INT_0_ORIGIN}]) +ZYNQ_LINKCMD([ZYNQ_RAM_INT_0_LENGTH],[internal 0 RAM region length],[${ZYNQ_RAM_INT_0_LENGTH}]) +ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_ORIGIN],[internal 1 RAM region origin],[${ZYNQ_RAM_INT_1_ORIGIN}]) +ZYNQ_LINKCMD([ZYNQ_RAM_INT_1_LENGTH],[internal 1 RAM region length],[${ZYNQ_RAM_INT_1_LENGTH}]) + +RTEMS_BSP_CLEANUP_OPTIONS + +AC_CONFIG_FILES([ +Makefile +linkcmds:../../../../../../bsps/arm/xilinx-zynq/start/linkcmds.in]) +AC_OUTPUT -- cgit v1.2.3