From 61bd030179f252d14f9639cf4921eb4eee07b5ef Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 14 Jun 2000 15:52:24 +0000 Subject: Moved PowerPC cache management code to libcpu. Also compiled mpc8xx libcpu support for the first time and remove includes of bsp.h, references to BSP_Configuration, and Cpu_table. All of these can be obtained directly from RTEMS now. --- c/src/exec/score/cpu/powerpc/rtems/score/ppc.h | 151 --------------------- c/src/exec/score/cpu/powerpc/shared/ppc.h | 151 --------------------- c/src/lib/libcpu/powerpc/configure.in | 2 + c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c | 60 ++++---- .../mpc8xx/console-generic/console-generic.c | 23 ++-- c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c | 7 +- c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c | 6 +- c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h | 2 - c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h | 2 - c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c | 3 +- c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c | 7 +- cpukit/score/cpu/powerpc/rtems/score/ppc.h | 151 --------------------- 12 files changed, 55 insertions(+), 510 deletions(-) diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h index 682675efde..cdff768d7d 100644 --- a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h +++ b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h @@ -384,157 +384,6 @@ extern "C" { #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" #endif -#ifndef ASM - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Some functions simply have not been implemented. - */ - -#if defined(ppc603) /* And possibly others */ -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - -/* Helpful macros */ -#define PPC_Get_HID0( _value ) \ - do { \ - _value = 0; /* to avoid warnings */ \ - asm volatile( \ - "mfspr %0, 0x3f0;" /* get HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -#define PPC_Set_HID0( _value ) \ - do { \ - asm volatile( \ - "isync;" \ - "mtspr 0x3f0, %0;" /* load HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -static inline void _CPU_enable_data_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value |= 0x00004000; /* set DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value &= 0xFFFFBFFF; /* clear DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value |= 0x00008000; /* Set ICE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value &= 0xFFFF7FFF; /* Clear ICE bit */ - PPC_Set_HID0( value ); -} - -#elif ( defined(mpc860) || defined(mpc821) ) - -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - -#define mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) -#define isync __asm__ volatile ("isync\n"::) - -static inline void _CPU_flush_1_data_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "dcbf 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_invalidate_1_data_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "dcbi 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_flush_entire_data_cache ( void ) {} -static inline void _CPU_invalidate_entire_data_cache ( void ) {} -static inline void _CPU_freeze_data_cache ( void ) {} -static inline void _CPU_unfreeze_data_cache ( void ) {} - -static inline void _CPU_enable_data_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x2<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x4<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_invalidate_1_inst_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "icbi 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( void ) {} -static inline void _CPU_freeze_inst_cache ( void ) {} -static inline void _CPU_unfreeze_inst_cache ( void ) {} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x2<<24); - mtspr( 560, r1 ); - isync; -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x4<<24); - mtspr( 560, r1 ); - isync; -} -#endif - -#endif /* !ASM */ - /* * Unless otherwise specified, assume the model has an IP/EP bit to * set the exception address prefix. diff --git a/c/src/exec/score/cpu/powerpc/shared/ppc.h b/c/src/exec/score/cpu/powerpc/shared/ppc.h index 682675efde..cdff768d7d 100644 --- a/c/src/exec/score/cpu/powerpc/shared/ppc.h +++ b/c/src/exec/score/cpu/powerpc/shared/ppc.h @@ -384,157 +384,6 @@ extern "C" { #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" #endif -#ifndef ASM - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Some functions simply have not been implemented. - */ - -#if defined(ppc603) /* And possibly others */ -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - -/* Helpful macros */ -#define PPC_Get_HID0( _value ) \ - do { \ - _value = 0; /* to avoid warnings */ \ - asm volatile( \ - "mfspr %0, 0x3f0;" /* get HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -#define PPC_Set_HID0( _value ) \ - do { \ - asm volatile( \ - "isync;" \ - "mtspr 0x3f0, %0;" /* load HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -static inline void _CPU_enable_data_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value |= 0x00004000; /* set DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value &= 0xFFFFBFFF; /* clear DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value |= 0x00008000; /* Set ICE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value &= 0xFFFF7FFF; /* Clear ICE bit */ - PPC_Set_HID0( value ); -} - -#elif ( defined(mpc860) || defined(mpc821) ) - -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - -#define mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) -#define isync __asm__ volatile ("isync\n"::) - -static inline void _CPU_flush_1_data_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "dcbf 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_invalidate_1_data_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "dcbi 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_flush_entire_data_cache ( void ) {} -static inline void _CPU_invalidate_entire_data_cache ( void ) {} -static inline void _CPU_freeze_data_cache ( void ) {} -static inline void _CPU_unfreeze_data_cache ( void ) {} - -static inline void _CPU_enable_data_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x2<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x4<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_invalidate_1_inst_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "icbi 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( void ) {} -static inline void _CPU_freeze_inst_cache ( void ) {} -static inline void _CPU_unfreeze_inst_cache ( void ) {} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x2<<24); - mtspr( 560, r1 ); - isync; -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x4<<24); - mtspr( 560, r1 ); - isync; -} -#endif - -#endif /* !ASM */ - /* * Unless otherwise specified, assume the model has an IP/EP bit to * set the exception address prefix. diff --git a/c/src/lib/libcpu/powerpc/configure.in b/c/src/lib/libcpu/powerpc/configure.in index db92d4bc8f..94781cf671 100644 --- a/c/src/lib/libcpu/powerpc/configure.in +++ b/c/src/lib/libcpu/powerpc/configure.in @@ -70,4 +70,6 @@ mpc6xx/mmu/Makefile mpc6xx/timer/Makefile mpc6xx/wrapup/Makefile shared/Makefile +shared/include/Makefile +shared/src/Makefile wrapup/Makefile) diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c index 50de9d7772..21c8de6df6 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c @@ -36,15 +36,13 @@ * $Id$ */ -#include +#include #include #include #include /* for atexit() */ #include -extern rtems_cpu_table Cpu_table; /* owned by BSP */ - volatile rtems_unsigned32 Clock_driver_ticks; extern volatile m8xx_t m8xx; @@ -78,37 +76,35 @@ void Install_clock(rtems_isr_entry clock_isr) Clock_driver_ticks = 0; - pit_value = (BSP_Configuration.microseconds_per_tick * - Cpu_table.clicks_per_usec) - 1 ; + pit_value = (rtems_configuration_get_microseconds_per_tick() * + rtems_cpu_configuration_get_clicks_per_usec()) - 1 ; if (pit_value > 0xffff) { /* pit is only 16 bits long */ rtems_fatal_error_occurred(-1); } - if (BSP_Configuration.ticks_per_timeslice) { - - /* - * initialize the interval here - * First tick is set to right amount of time in the future - * Future ticks will be incremented over last value set - * in order to provide consistent clicks in the face of - * interrupt overhead - */ - - rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); - - m8xx.sccr &= ~(1<<24); - m8xx.pitc = pit_value; - - /* set PIT irq level, enable PIT, PIT interrupts */ - /* and clear int. status */ - m8xx.piscr = M8xx_PISCR_PIRQ(0) | - M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; + + /* + * initialize the interval here + * First tick is set to right amount of time in the future + * Future ticks will be incremented over last value set + * in order to provide consistent clicks in the face of + * interrupt overhead + */ + + rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); + + m8xx.sccr &= ~(1<<24); + m8xx.pitc = pit_value; + + /* set PIT irq level, enable PIT, PIT interrupts */ + /* and clear int. status */ + m8xx.piscr = M8xx_PISCR_PIRQ(0) | + M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; #ifdef EPPCBUG_SMC1 - simask_copy = m8xx.simask | M8xx_SIMASK_LVM0; + simask_copy = m8xx.simask | M8xx_SIMASK_LVM0; #endif /* EPPCBUG_SMC1 */ - m8xx.simask |= M8xx_SIMASK_LVM0; - } + m8xx.simask |= M8xx_SIMASK_LVM0; atexit(Clock_exit); } @@ -133,12 +129,10 @@ ReInstall_clock(rtems_isr_entry new_clock_isr) void Clock_exit(void) { - if ( BSP_Configuration.ticks_per_timeslice ) { - /* disable PIT and PIT interrupts */ - m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); - - (void) set_vector(0, PPC_IRQ_LVL0, 1); - } + /* disable PIT and PIT interrupts */ + m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); + + (void) set_vector(0, PPC_IRQ_LVL0, 1); } rtems_device_driver Clock_initialize( diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c index 92c504d92e..0f25b297b4 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c @@ -46,10 +46,11 @@ * $Id$ */ -#include +#include #include #include #include +#include #include #include #include @@ -399,7 +400,7 @@ m8xx_scc2_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { rtems_invalidate_multiple_data_cache_lines( - RxBd[SCC2_MINOR]->buffer, + (const void *) RxBd[SCC2_MINOR]->buffer, RxBd[SCC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC2_MINOR], @@ -442,7 +443,7 @@ m8xx_scc3_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { rtems_invalidate_multiple_data_cache_lines( - RxBd[SCC3_MINOR]->buffer, + (const void *) RxBd[SCC3_MINOR]->buffer, RxBd[SCC3_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC3_MINOR], @@ -484,7 +485,7 @@ m8xx_scc4_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { rtems_invalidate_multiple_data_cache_lines( - RxBd[SCC4_MINOR]->buffer, + (const void *) RxBd[SCC4_MINOR]->buffer, RxBd[SCC4_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC4_MINOR], @@ -526,7 +527,7 @@ m8xx_smc1_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { rtems_invalidate_multiple_data_cache_lines( - RxBd[SMC1_MINOR]->buffer, + (const void *) RxBd[SMC1_MINOR]->buffer, RxBd[SMC1_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC1_MINOR], @@ -568,7 +569,7 @@ m8xx_smc2_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { rtems_invalidate_multiple_data_cache_lines( - RxBd[SMC2_MINOR]->buffer, + (const void *) RxBd[SMC2_MINOR]->buffer, RxBd[SMC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC2_MINOR], @@ -983,7 +984,10 @@ m8xx_uart_pollRead( if (RxBd[minor]->status & M8xx_BD_EMPTY) { return -1; } - _CPU_Data_Cache_Block_Invalidate( RxBd[minor]->buffer ); + rtems_invalidate_multiple_data_cache_lines( + (const void *) RxBd[minor]->buffer, + RxBd[minor]->length + ); c = ((char *)RxBd[minor]->buffer)[0]; RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP; return c; @@ -1019,7 +1023,10 @@ m8xx_uart_pollWrite( while (TxBd[minor]->status & M8xx_BD_READY) continue; txBuf[minor] = *buf++; - _CPU_Data_Cache_Block_Flush( &txBuf[minor] ); + rtems_flush_multiple_data_cache_lines( + (const void *) TxBd[minor]->buffer, + TxBd[minor]->length + ); TxBd[minor]->buffer = &txBuf[minor]; TxBd[minor]->length = 1; TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c index 235e4bafc3..b1ca0eed6b 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c @@ -12,13 +12,14 @@ * Copyright (c) 1999, National Research Council of Canada */ -#include -#include -#include +#include +#include +#include /* * Send a command to the CPM RISC processer */ + void m8xx_cp_execute_cmd( unsigned16 command ) { rtems_unsigned16 lvl; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c index 985b5b5bd1..825e591351 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c @@ -13,9 +13,9 @@ * Copyright (c) 1999, National Research Council of Canada */ -#include -#include -#include +#include +#include +#include /* * Allocation order: diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h index d39ddf2e23..2e0e0b84d2 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h @@ -18,8 +18,6 @@ extern "C" { #endif -#include - /* Functions */ void m8xx_cp_execute_cmd( unsigned16 command ); diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h index 7370e0cf5a..9ade5f977c 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h @@ -18,8 +18,6 @@ extern "C" { #endif -#include - /* * The MMU_TLB_table is used to statically initialize the Table Lookaside * Buffers in the MMU of an MPC8xx. diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c index 7e877b106f..9ae75d84f7 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @@ -11,7 +11,8 @@ * http://www.OARcorp.com/rtems/license.html. */ -#include +#include +#include #include /* diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c index 50c2a3e00a..d9fbbe4a39 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c @@ -43,12 +43,9 @@ * $Id$ */ -#include #include #include -extern rtems_cpu_table Cpu_table; /* owned by BSP */ - static volatile rtems_unsigned32 Timer_starting; static rtems_boolean Timer_driver_Find_average_overhead; @@ -86,10 +83,10 @@ int Read_timer(void) return total; /* in XXX microsecond units */ else { - if ( total < Cpu_table.timer_least_valid ) { + if ( total < rtems_cpu_configuration_get_timer_least_valid() ) { return 0; /* below timer resolution */ } - return (total - Cpu_table.timer_average_overhead); + return (total - rtems_cpu_configuration_get_timer_average_overhead()); } } diff --git a/cpukit/score/cpu/powerpc/rtems/score/ppc.h b/cpukit/score/cpu/powerpc/rtems/score/ppc.h index 682675efde..cdff768d7d 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/ppc.h +++ b/cpukit/score/cpu/powerpc/rtems/score/ppc.h @@ -384,157 +384,6 @@ extern "C" { #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" #endif -#ifndef ASM - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Some functions simply have not been implemented. - */ - -#if defined(ppc603) /* And possibly others */ -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - -/* Helpful macros */ -#define PPC_Get_HID0( _value ) \ - do { \ - _value = 0; /* to avoid warnings */ \ - asm volatile( \ - "mfspr %0, 0x3f0;" /* get HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -#define PPC_Set_HID0( _value ) \ - do { \ - asm volatile( \ - "isync;" \ - "mtspr 0x3f0, %0;" /* load HID0 */ \ - "isync" \ - : "=r" (_value) \ - : "0" (_value) \ - ); \ - } while (0) - -static inline void _CPU_enable_data_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value |= 0x00004000; /* set DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value &= 0xFFFFBFFF; /* clear DCE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value |= 0x00008000; /* Set ICE bit */ - PPC_Set_HID0( value ); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - unsigned32 value; - PPC_Get_HID0( value ); - value &= 0xFFFF7FFF; /* Clear ICE bit */ - PPC_Set_HID0( value ); -} - -#elif ( defined(mpc860) || defined(mpc821) ) - -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT - -#define mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) -#define isync __asm__ volatile ("isync\n"::) - -static inline void _CPU_flush_1_data_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "dcbf 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_invalidate_1_data_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "dcbi 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_flush_entire_data_cache ( void ) {} -static inline void _CPU_invalidate_entire_data_cache ( void ) {} -static inline void _CPU_freeze_data_cache ( void ) {} -static inline void _CPU_unfreeze_data_cache ( void ) {} - -static inline void _CPU_enable_data_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x2<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x4<<24); - mtspr( 568, r1 ); - isync; -} - -static inline void _CPU_invalidate_1_inst_cache_line( - const void * _address ) -{ - register const void *__address = _address; - asm volatile ( "icbi 0,%0" :: "r" (__address) ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( void ) {} -static inline void _CPU_freeze_inst_cache ( void ) {} -static inline void _CPU_unfreeze_inst_cache ( void ) {} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x2<<24); - mtspr( 560, r1 ); - isync; -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - unsigned32 r1; - r1 = (0x4<<24); - mtspr( 560, r1 ); - isync; -} -#endif - -#endif /* !ASM */ - /* * Unless otherwise specified, assume the model has an IP/EP bit to * set the exception address prefix. -- cgit v1.2.3