From 5cc075712e628191477d0c9d074e15b6a7c1e1e3 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 1 Jul 2022 15:21:47 +0200 Subject: irq/arm-gicv3.h: Customize CPU Interface init Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers. --- bsps/include/dev/irq/arm-gicv3.h | 58 +++++++++++++++-------- spec/build/bsps/aarch64/a53/grp.yml | 2 + spec/build/bsps/aarch64/a53/obj.yml | 1 - spec/build/bsps/aarch64/a72/grp.yml | 2 + spec/build/bsps/aarch64/a72/obj.yml | 1 - spec/build/bsps/aarch64/grp.yml | 1 - spec/build/bsps/aarch64/xilinx-versal/grp.yml | 2 + spec/build/bsps/aarch64/xilinx-versal/obj.yml | 1 - spec/build/bsps/arm/fvp/grp.yml | 2 + spec/build/bsps/arm/fvp/obj.yml | 1 - spec/build/bsps/arm/grp.yml | 1 - spec/build/bsps/dev/irq/objarmgicv3.yml | 31 ++++++++++++ spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml | 21 ++++++++ spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml | 18 +++++++ spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml | 18 +++++++ spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml | 21 ++++++++ spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml | 18 +++++++ spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml | 18 +++++++ spec/build/bsps/dev/irq/optarmgic-icc-sre.yml | 18 +++++++ 19 files changed, 208 insertions(+), 27 deletions(-) create mode 100644 spec/build/bsps/dev/irq/objarmgicv3.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml create mode 100644 spec/build/bsps/dev/irq/optarmgic-icc-sre.yml diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h index a79368ebdf..a716ffbca5 100644 --- a/bsps/include/dev/irq/arm-gicv3.h +++ b/bsps/include/dev/irq/arm-gicv3.h @@ -116,13 +116,16 @@ extern "C" { #else /* ARM_MULTILIB_ARCH_V4 */ /* AArch64 GICv3 registers are not named in GCC */ -#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0" -#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0" +#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0" +#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0" #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0" +#define ICC_IGRPEN0 ICC_IGRPEN0_EL1 +#define ICC_IGRPEN1 ICC_IGRPEN1_EL1 #define ICC_PMR "S3_0_C4_C6_0, %0" #define ICC_EOIR1 "S3_0_C12_C12_1, %0" #define ICC_SRE "S3_0_C12_C12_5, %0" #define ICC_BPR0 "S3_0_C12_C8_3, %0" +#define ICC_BPR1 "S3_0_C12_C12_3, %0" #define ICC_CTLR "S3_0_C12_C12_4, %0" #define ICC_IAR1 "%0, S3_0_C12_C12_0" #define MPIDR "%0, mpidr_el1" @@ -300,25 +303,27 @@ static void gicv3_init_dist(volatile gic_dist *dist) } } -/* - * A better way to access these registers than special opcodes - */ -#define isb() __asm __volatile("isb" : : : "memory") +static void gicv3_init_cpu_interface(uint32_t cpu_index) +{ + /* Initialize Interrupt Controller System Register Enable Register */ +#ifdef BSP_ARM_GIC_ICC_SRE + WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE); +#endif -#define WRITE_SPECIALREG(reg, _val) \ - __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) + /* Initialize Interrupt Controller Interrupt Priority Mask Register */ +#ifdef BSP_ARM_GIC_ICC_PMR + WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR); +#endif -#define gic_icc_write(reg, val) \ -do { \ - WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \ - isb(); \ -} while (0) + /* Initialize Interrupt Controller Binary Point Register 0 */ +#ifdef BSP_ARM_GIC_ICC_BPR0 + WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0); +#endif -static void gicv3_init_cpu_interface(uint32_t cpu_index) -{ - uint32_t sre_value = 0x7; - WRITE_SR(ICC_SRE, sre_value); - WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff)); + /* Initialize Interrupt Controller Binary Point Register 1 */ +#ifdef BSP_ARM_GIC_ICC_BPR1 + WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1); +#endif volatile gic_redist *redist = gicv3_get_redist(cpu_index); uint32_t waker = redist->icrwaker; @@ -334,9 +339,20 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index) sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT; } - /* Enable interrupt groups 0 and 1 */ - gic_icc_write(IGRPEN1, 1); - WRITE_SR(ICC_CTLR, 0x0); + /* Initialize Interrupt Controller Interrupt Group Enable 0 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN0 + WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0); +#endif + + /* Initialize Interrupt Controller Interrupt Group Enable 1 Register */ +#ifdef BSP_ARM_GIC_ICC_IGRPEN1 + WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1); +#endif + + /* Initialize Interrupt Controller Control Register */ +#ifdef BSP_ARM_GIC_ICC_CTRL + WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL); +#endif } static inline void gicv3_get_attributes( diff --git a/spec/build/bsps/aarch64/a53/grp.yml b/spec/build/bsps/aarch64/a53/grp.yml index 091f18d6f5..9ab10d643d 100644 --- a/spec/build/bsps/aarch64/a53/grp.yml +++ b/spec/build/bsps/aarch64/a53/grp.yml @@ -32,6 +32,8 @@ links: uid: ../../obj - role: build-dependency uid: ../../objirq +- role: build-dependency + uid: ../../dev/irq/objarmgicv3 - role: build-dependency uid: ../../objmem - role: build-dependency diff --git a/spec/build/bsps/aarch64/a53/obj.yml b/spec/build/bsps/aarch64/a53/obj.yml index 242631fba2..33c0884b85 100644 --- a/spec/build/bsps/aarch64/a53/obj.yml +++ b/spec/build/bsps/aarch64/a53/obj.yml @@ -26,7 +26,6 @@ source: - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/dev/serial/console-termios-init.c - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c diff --git a/spec/build/bsps/aarch64/a72/grp.yml b/spec/build/bsps/aarch64/a72/grp.yml index 341f832a61..a8d09d108c 100644 --- a/spec/build/bsps/aarch64/a72/grp.yml +++ b/spec/build/bsps/aarch64/a72/grp.yml @@ -32,6 +32,8 @@ links: uid: ../../obj - role: build-dependency uid: ../../objirq +- role: build-dependency + uid: ../../dev/irq/objarmgicv3 - role: build-dependency uid: ../../objmem - role: build-dependency diff --git a/spec/build/bsps/aarch64/a72/obj.yml b/spec/build/bsps/aarch64/a72/obj.yml index f797762b41..4fb5e59ba3 100644 --- a/spec/build/bsps/aarch64/a72/obj.yml +++ b/spec/build/bsps/aarch64/a72/obj.yml @@ -26,7 +26,6 @@ source: - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/dev/serial/console-termios-init.c - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml index ba4ec6c6cf..9428fb9435 100644 --- a/spec/build/bsps/aarch64/grp.yml +++ b/spec/build/bsps/aarch64/grp.yml @@ -22,7 +22,6 @@ install: - bsps/include/dev/irq/arm-gic-regs.h - bsps/include/dev/irq/arm-gic-tm27.h - bsps/include/dev/irq/arm-gic.h - - bsps/include/dev/irq/arm-gicv3.h - destination: ${BSP_LIBDIR} source: - bsps/aarch64/shared/start/linkcmds.base diff --git a/spec/build/bsps/aarch64/xilinx-versal/grp.yml b/spec/build/bsps/aarch64/xilinx-versal/grp.yml index 0f23e20950..27a77e9e6f 100644 --- a/spec/build/bsps/aarch64/xilinx-versal/grp.yml +++ b/spec/build/bsps/aarch64/xilinx-versal/grp.yml @@ -40,6 +40,8 @@ links: uid: ../../obj - role: build-dependency uid: ../../objirq +- role: build-dependency + uid: ../../dev/irq/objarmgicv3 - role: build-dependency uid: ../../objdevspizynq - role: build-dependency diff --git a/spec/build/bsps/aarch64/xilinx-versal/obj.yml b/spec/build/bsps/aarch64/xilinx-versal/obj.yml index d5748aca9a..04ac3761f9 100644 --- a/spec/build/bsps/aarch64/xilinx-versal/obj.yml +++ b/spec/build/bsps/aarch64/xilinx-versal/obj.yml @@ -33,7 +33,6 @@ source: - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/dev/serial/console-termios-init.c - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c diff --git a/spec/build/bsps/arm/fvp/grp.yml b/spec/build/bsps/arm/fvp/grp.yml index 8de7d10917..eecbd9efd9 100644 --- a/spec/build/bsps/arm/fvp/grp.yml +++ b/spec/build/bsps/arm/fvp/grp.yml @@ -24,6 +24,8 @@ links: uid: ../../obj - role: build-dependency uid: ../../objirq +- role: build-dependency + uid: ../../dev/irq/objarmgicv3 - role: build-dependency uid: ../../objmem - role: build-dependency diff --git a/spec/build/bsps/arm/fvp/obj.yml b/spec/build/bsps/arm/fvp/obj.yml index 3db46c6ccc..05fa6dc368 100644 --- a/spec/build/bsps/arm/fvp/obj.yml +++ b/spec/build/bsps/arm/fvp/obj.yml @@ -34,7 +34,6 @@ source: - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c - bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/irq/arm-gicv3.c - bsps/shared/dev/serial/console-termios.c - bsps/shared/irq/irq-default-handler.c - bsps/shared/start/bspfatal-default.c diff --git a/spec/build/bsps/arm/grp.yml b/spec/build/bsps/arm/grp.yml index bb51734b3c..37229fddc2 100644 --- a/spec/build/bsps/arm/grp.yml +++ b/spec/build/bsps/arm/grp.yml @@ -46,7 +46,6 @@ install: - bsps/include/dev/irq/arm-gic-regs.h - bsps/include/dev/irq/arm-gic-tm27.h - bsps/include/dev/irq/arm-gic.h - - bsps/include/dev/irq/arm-gicv3.h - destination: ${BSP_INCLUDEDIR}/libcpu source: - bsps/arm/include/libcpu/am335x.h diff --git a/spec/build/bsps/dev/irq/objarmgicv3.yml b/spec/build/bsps/dev/irq/objarmgicv3.yml new file mode 100644 index 0000000000..aa84ae5416 --- /dev/null +++ b/spec/build/bsps/dev/irq/objarmgicv3.yml @@ -0,0 +1,31 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR}/dev/irq + source: + - bsps/include/dev/irq/arm-gicv3.h +links: +- role: build-dependency + uid: optarmgic-icc-bpr0 +- role: build-dependency + uid: optarmgic-icc-bpr1 +- role: build-dependency + uid: optarmgic-icc-ctrl +- role: build-dependency + uid: optarmgic-icc-igrpen0 +- role: build-dependency + uid: optarmgic-icc-igrpen1 +- role: build-dependency + uid: optarmgic-icc-pmr +- role: build-dependency + uid: optarmgic-icc-sre +source: +- bsps/shared/dev/irq/arm-gicv3.c +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml new file mode 100644 index 0000000000..01933d00ca --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 2 +default-by-variant: +- value: null + variants: + - aarch64/.* +description: | + Defines the initial value of the ICC_BPR0 register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_BPR0 +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml b/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml new file mode 100644 index 0000000000..c9c99dfc63 --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 3 +default-by-variant: [] +description: | + Defines the initial value of the ICC_BPR1 register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_BPR1 +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml b/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml new file mode 100644 index 0000000000..1f9ae33e0f --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 0 +default-by-variant: [] +description: | + Defines the initial value of the ICC_CTRL register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_CTRL +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml new file mode 100644 index 0000000000..aea536d7d1 --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 1 +default-by-variant: +- value: null + variants: + - aarch64/.* +description: | + Defines the initial value of the ICC_IGRPEN0 register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_IGRPEN0 +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml new file mode 100644 index 0000000000..1c18db63b7 --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 1 +default-by-variant: [] +description: | + Defines the initial value of the ICC_IGRPEN1 register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_IGRPEN1 +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml b/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml new file mode 100644 index 0000000000..d0fbda520a --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 255 +default-by-variant: [] +description: | + Defines the initial value of the ICC_PMR register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_PMR +type: build diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml b/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml new file mode 100644 index 0000000000..aca2f2720b --- /dev/null +++ b/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de) +default: 3 +default-by-variant: [] +description: | + Defines the initial value of the ICC_SRE register of the ARM GIC CPU + Interface. The value is optional. If it is not defined, then the register + is not initialized. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_ARM_GIC_ICC_SRE +type: build -- cgit v1.2.3