From 5b6111b499f0e727b7987a87117b464398ee2500 Mon Sep 17 00:00:00 2001 From: Eric Norum Date: Thu, 3 Feb 2005 16:01:04 +0000 Subject: Add support for interrupt controller allocation. This will provides a mechanism for applications to find a free level/priority. --- c/src/lib/libbsp/m68k/uC5282/clock/clock.c | 3 ++- c/src/lib/libbsp/m68k/uC5282/console/console.c | 5 ++++- c/src/lib/libbsp/m68k/uC5282/include/bsp.h | 3 ++- c/src/lib/libbsp/m68k/uC5282/network/network.c | 4 +++- c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c | 22 +++++++++++++++++++++- c/src/lib/libbsp/m68k/uC5282/timer/timer.c | 2 +- 6 files changed, 33 insertions(+), 6 deletions(-) diff --git a/c/src/lib/libbsp/m68k/uC5282/clock/clock.c b/c/src/lib/libbsp/m68k/uC5282/clock/clock.c index 8b10dbfd28..db98a9205e 100644 --- a/c/src/lib/libbsp/m68k/uC5282/clock/clock.c +++ b/c/src/lib/libbsp/m68k/uC5282/clock/clock.c @@ -47,11 +47,12 @@ do { \ int level; \ int preScaleCode = -2; \ - int preScaleDivisor = get_CPU_clock_speed() / 1000000; \ + int preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; \ while (preScaleDivisor) { \ preScaleDivisor >>= 1; \ preScaleCode++; \ } \ + bsp_allocate_interrupt(PIT3_IRQ_LEVEL, PIT3_IRQ_PRIORITY); \ MCF5282_INTC0_ICR58 = MCF5282_INTC_ICR_IL(PIT3_IRQ_LEVEL) | \ MCF5282_INTC_ICR_IP(PIT3_IRQ_PRIORITY); \ rtems_interrupt_disable( level ); \ diff --git a/c/src/lib/libbsp/m68k/uC5282/console/console.c b/c/src/lib/libbsp/m68k/uC5282/console/console.c index 574c1c9633..086861bd43 100644 --- a/c/src/lib/libbsp/m68k/uC5282/console/console.c +++ b/c/src/lib/libbsp/m68k/uC5282/console/console.c @@ -136,7 +136,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits, int hwfl info->stopbits = stopbits; info->hwflow = hwflow; - clock_speed = get_CPU_clock_speed(); + clock_speed = bsp_get_CPU_clock_speed(); /* determine the baud divisor value */ divisor = (clock_speed / ( 32 * baud )); if ( divisor < 2 ) @@ -396,6 +396,7 @@ IntUartInitialize(void) rtems_interrupt_disable(level); switch(chan) { case 0: + bsp_allocate_interrupt(UART0_IRQ_LEVEL, UART0_IRQ_PRIORITY); MCF5282_INTC0_ICR13 = MCF5282_INTC_ICR_IL(UART0_IRQ_LEVEL) | MCF5282_INTC_ICR_IP(UART0_IRQ_PRIORITY); MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT13 | @@ -403,6 +404,7 @@ IntUartInitialize(void) break; case 1: + bsp_allocate_interrupt(UART1_IRQ_LEVEL, UART1_IRQ_PRIORITY); MCF5282_INTC0_ICR14 = MCF5282_INTC_ICR_IL(UART1_IRQ_LEVEL) | MCF5282_INTC_ICR_IP(UART1_IRQ_PRIORITY); MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT14 | @@ -410,6 +412,7 @@ IntUartInitialize(void) break; case 2: + bsp_allocate_interrupt(UART2_IRQ_LEVEL, UART2_IRQ_PRIORITY); MCF5282_INTC0_ICR15 = MCF5282_INTC_ICR_IL(UART2_IRQ_LEVEL) | MCF5282_INTC_ICR_IP(UART2_IRQ_PRIORITY); MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT15 | diff --git a/c/src/lib/libbsp/m68k/uC5282/include/bsp.h b/c/src/lib/libbsp/m68k/uC5282/include/bsp.h index 91d4226a5b..49d4174d5f 100644 --- a/c/src/lib/libbsp/m68k/uC5282/include/bsp.h +++ b/c/src/lib/libbsp/m68k/uC5282/include/bsp.h @@ -67,7 +67,8 @@ extern rtems_configuration_table BSP_Configuration; /* functions */ -unsigned32 get_CPU_clock_speed(void); +unsigned32 bsp_get_CPU_clock_speed(void); +int bsp_allocate_interrupt(int level, int priority); unsigned const char *uC5282_gethwaddr(int a); const char *uC5282_getbenv(const char *a); diff --git a/c/src/lib/libbsp/m68k/uC5282/network/network.c b/c/src/lib/libbsp/m68k/uC5282/network/network.c index de9555dbe8..efb3809040 100644 --- a/c/src/lib/libbsp/m68k/uC5282/network/network.c +++ b/c/src/lib/libbsp/m68k/uC5282/network/network.c @@ -179,7 +179,7 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc) const unsigned char *hwaddr; rtems_status_code status; rtems_isr_entry old_handler; - unsigned32 clock_speed = get_CPU_clock_speed(); + unsigned32 clock_speed = bsp_get_CPU_clock_speed(); /* * Issue reset to FEC @@ -297,9 +297,11 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc) if (status != RTEMS_SUCCESSFUL) rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n", rtems_status_text(status)); + bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY); MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) | MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY); MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL); + bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY); MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) | MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY); MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL); diff --git a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c index f3b46b41eb..6daa606b20 100644 --- a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @@ -246,12 +246,32 @@ void bsp_start( void ) MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; } -unsigned32 get_CPU_clock_speed(void) +unsigned32 bsp_get_CPU_clock_speed(void) { extern char _CPUClockSpeed[]; return( (unsigned32)_CPUClockSpeed); } +/* + * Interrupt controller allocation + */ +int bsp_allocate_interrupt(int level, int priority) +{ + static char used[7]; + rtems_interrupt_level l; + int ret = -1; + + if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) + return ret; + rtems_interrupt_disable(l); + if ((used[level-1] & (1 << priority)) == 0) { + used[level-1] |= (1 << priority); + ret = 0; + } + rtems_interrupt_enable(l); + return ret; +} + /* * Arcturus bootloader system calls */ diff --git a/c/src/lib/libbsp/m68k/uC5282/timer/timer.c b/c/src/lib/libbsp/m68k/uC5282/timer/timer.c index 3c76c94285..40ec59eb4d 100644 --- a/c/src/lib/libbsp/m68k/uC5282/timer/timer.c +++ b/c/src/lib/libbsp/m68k/uC5282/timer/timer.c @@ -10,7 +10,7 @@ void Timer_initialize(void) { - int preScaleDivisor = get_CPU_clock_speed() / 1000000; + int preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; int div = MCF5282_TIMER_DTMR_CLK_DIV1; if (preScaleDivisor > 256) { -- cgit v1.2.3