From 54f3476e2493a957efb0e30c77226d496e7fc5a1 Mon Sep 17 00:00:00 2001 From: Daniel Cederman Date: Thu, 3 Jul 2014 11:18:55 +0200 Subject: bsp/sparc: Flush icache before first time enabling interrupts A secondary processor might miss changes done to the trap table if the instruction cache is not flushed. Once interrupts are enabled any other required cache flushes can be ordered via the cache manager. --- c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c | 9 +++++++++ cpukit/score/cpu/sparc/rtems/score/cpu.h | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c index 567eecc819..9166ad5630 100644 --- a/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c +++ b/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -80,3 +81,11 @@ void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) /* send interrupt to destination CPU */ LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_MP_IRQ; } + +void _BSP_Start_multitasking( + Context_Control *heir +) +{ + _CPU_cache_invalidate_entire_instruction(); + _CPU_Context_Restart_self( heir ); +} diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 39b78258c1..9c38b55e7d 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -1203,6 +1203,10 @@ register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + void _BSP_Start_multitasking( Context_Control *heir ) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; + #define _CPU_Start_multitasking _BSP_Start_multitasking + static inline void _CPU_SMP_Processor_event_broadcast( void ) { __asm__ volatile ( "" : : : "memory" ); -- cgit v1.2.3