From 54cb48f28bffcc0cbcbd68bd7128f8df6e75445d Mon Sep 17 00:00:00 2001 From: Jennifer Averett Date: Thu, 12 May 2005 18:25:29 +0000 Subject: 2005-05-12 Jennifer Averett * README.VME, include/bsp.h, irq/irq.h, network/GT64260eth.c, pci/detect_host_bridge.c, pci/gtpcireg.h, pci/pci.c, pci/pci.h, pci/pci_interface.c, pci/pcifinddevice.c: Submitted by Kate Feng as RTEMS-MVME5500 BSP v1.1 release. Modifications made to merge this release with the current tree. --- c/src/lib/libbsp/powerpc/mvme5500/ChangeLog | 8 + c/src/lib/libbsp/powerpc/mvme5500/README.VME | 2 +- c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h | 10 + c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h | 1 + .../libbsp/powerpc/mvme5500/network/GT64260eth.c | 256 ++++++-------- .../powerpc/mvme5500/pci/detect_host_bridge.c | 17 +- c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h | 12 +- c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c | 384 ++++++++++++--------- c/src/lib/libbsp/powerpc/mvme5500/pci/pci.h | 167 +-------- .../libbsp/powerpc/mvme5500/pci/pci_interface.c | 37 +- .../libbsp/powerpc/mvme5500/pci/pcifinddevice.c | 52 +-- 11 files changed, 450 insertions(+), 496 deletions(-) diff --git a/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog b/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog index ae30bf081f..8ad5ad1603 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog +++ b/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog @@ -1,3 +1,11 @@ +2005-05-12 Jennifer Averett + + * README.VME, include/bsp.h, irq/irq.h, network/GT64260eth.c, + pci/detect_host_bridge.c, pci/gtpcireg.h, pci/pci.c, pci/pci.h, + pci/pci_interface.c, pci/pcifinddevice.c: + Submitted by Kate Feng as RTEMS-MVME5500 BSP v1.1 release. + Modifications made to merge this release with the current tree. + 2005-05-10 Jennifer Averett * network/GT64260eth.c: Fixed warning. diff --git a/c/src/lib/libbsp/powerpc/mvme5500/README.VME b/c/src/lib/libbsp/powerpc/mvme5500/README.VME index 7312f682eb..f669f94d1b 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/README.VME +++ b/c/src/lib/libbsp/powerpc/mvme5500/README.VME @@ -6,7 +6,7 @@ command following the out_xx() function (e.g. out_be16()) if mvme5500 is used as the SBC. The mechanism is a hardware hook to help software synchronize between the CPU and PCI activities. The PCI sync is implemented in pci/pci_interface.c. For more example of the usage,one -can refrence the drvOMS58.cc file that is posted in synAppRTEMS of +can reference the drvOMS58.cc file that is posted in synAppRTEMS of http://www.nsls.bnl.gov/organization/UserScience/Detectors/Software/Default.htm. diff --git a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h index 842472e983..2c799557d9 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h @@ -43,6 +43,16 @@ #define PCI1_MEM_BASE 0xe0000000 #define PCI1_MEM_SIZE 0x10000000 +/* Needed for hot adding via PMCspan on the PCI0 local bus. + * This is board dependent, only because mvme5500 + * supports hot adding and has more than one local PCI + * bus. + */ +#define BSP_MAX_PCI_BUS_ON_PCI0 8 +#define BSP_MAX_PCI_BUS_ON_PCI1 2 +#define BSP_MAX_PCI_BUS (BSP_MAX_PCI_BUS_ON_PCI0+BSP_MAX_PCI_BUS_ON_PCI1) + + /* The glues to Till's vmeUniverse, although the name does not * actually reflect the relevant architect of the MVME5500. * Till TODO ? : BSP_PCI_DO_EOI instead ? diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h index 62fc34e279..14eeca53a6 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h @@ -125,6 +125,7 @@ typedef enum { BSP_ISA_UART_COM2_IRQ = BSP_GPP_IRQ_LOWEST_OFFSET, BSP_ISA_UART_COM1_IRQ = BSP_GPP_IRQ_LOWEST_OFFSET, BSP_GPP8_IRQ_OFFSET = BSP_GPP_IRQ_LOWEST_OFFSET+8, + BSP_GPP_PMC1_INTA = BSP_GPP8_IRQ_OFFSET, BSP_GPP16_IRQ_OFFSET = BSP_GPP_IRQ_LOWEST_OFFSET+16, BSP_GPP24_IRQ_OFFSET = BSP_GPP_IRQ_LOWEST_OFFSET+24, BSP_GPP_VME_VLINT0 = BSP_GPP_IRQ_LOWEST_OFFSET+12, diff --git a/c/src/lib/libbsp/powerpc/mvme5500/network/GT64260eth.c b/c/src/lib/libbsp/powerpc/mvme5500/network/GT64260eth.c index fe19492c4e..9b5f748644 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/network/GT64260eth.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/network/GT64260eth.c @@ -131,16 +131,16 @@ static void GTeth_ifstart (struct ifnet *); static void GTeth_ifchange(struct GTeth_softc *sc); static void GTeth_init_rx_ring(struct GTeth_softc *sc); static void GT64260eth_daemon(void *arg); -static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m,enum GTeth_txprio); -static unsigned GTeth_txq_done(struct GTeth_softc *sc, enum GTeth_txprio txprio); -static void GTeth_tx_cleanup(struct GTeth_softc *sc, enum GTeth_txprio, int); -static void GTeth_tx_start(struct GTeth_softc *sc, enum GTeth_txprio); -static void GTeth_tx_stop(struct GTeth_softc *sc, enum GTeth_whack_op op); -static void GTeth_rx_cleanup(struct GTeth_softc *sc, enum GTeth_rxprio); -static int GT64260eth_rx(struct GTeth_softc *sc, enum GTeth_rxprio); +static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m); +static unsigned GTeth_txq_done(struct GTeth_softc *sc); +static void GTeth_tx_cleanup(struct GTeth_softc *sc); +static void GTeth_tx_start(struct GTeth_softc *sc); +static void GTeth_tx_stop(struct GTeth_softc *sc); +static void GTeth_rx_cleanup(struct GTeth_softc *sc); +static int GT64260eth_rx(struct GTeth_softc *sc); static void GTeth_rx_setup(struct GTeth_softc *sc); -static void GTeth_rxprio_setup(struct GTeth_softc *sc, enum GTeth_rxprio); -static void GTeth_rx_stop(struct GTeth_softc *dc, enum GTeth_whack_op op); +static void GTeth_rxprio_setup(struct GTeth_softc *sc); +static void GTeth_rx_stop(struct GTeth_softc *dc); static void GT64260eth_isr(); static int GTeth_hash_compute(struct GTeth_softc *sc,unsigned char eaddr[ETHER_ADDR_LEN]); static int GTeth_hash_entry_op(struct GTeth_softc *sc, enum GTeth_hash_op op, @@ -150,7 +150,6 @@ static int GTeth_hash_fill(struct GTeth_softc *sc); static void GTeth_hash_init(struct GTeth_softc *sc); static struct GTeth_softc *root_GT64260eth_dev = NULL; -static int GTeth_MissedFrame_err=0; static void GT64260eth_irq_on(const rtems_irq_connect_data *irq) { @@ -160,7 +159,7 @@ static void GT64260eth_irq_on(const rtems_irq_connect_data *irq) printk("GT64260eth_irq_on\n"); outl(0x30883444,ETH0_EIMR); /* MOTLoad default interrupt mask */ return; - } + } } static void GT64260eth_irq_off(const rtems_irq_connect_data *irq) @@ -186,17 +185,27 @@ static void GT64260eth_isr() cause = inl(ETH0_EICR); outl( ~cause,ETH0_EICR); /* clear the ICR */ - if (cause & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { + /* ETH_IR_RxBuffer_3|ETH_IR_RxError_3 */ + if (cause & 0x880000) { sc->stats.rxInterrupts++; events |= RX_EVENT; } /* If there is an error, we want to continue to next descriptor */ - if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh|ETH_IR_TxErrorHigh)) { + /* ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh|ETH_IR_TxErrorHigh */ + if (cause & 0x444) { sc->stats.txInterrupts++; events |= TX_EVENT; - if ((sc->txq_nactive) && ((inl(ETH0_ESDCMR)Ð_ESDCMR_TXDH)==0)) - outl(ETH_ESDCMR_TXDH | ETH_ESDCMR_ERD,ETH0_ESDCMR); - } + /* It seems to be unnecessary. However, it's there + * to be on the safe side due to the datasheet. + * So far, it does not seem to affect the network performance + * based on the EPICS catime. + */ + /* ETH_ESDCMR_TXDH | ETH_ESDCMR_ERD = 0x800080 */ + if ((sc->txq_nactive > 1)&& ((inl(ETH0_ESDCMR)Ð_ESDCMR_TXDH)==0)) + outl(0x800080,ETH0_ESDCMR); + + + } if ( (!cause) || (cause & 0x803d00)) { sc->intr_errsts[sc->intr_err_ptr2++]=cause; sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */ @@ -235,7 +244,7 @@ static void GT64260eth_init_hw(struct GTeth_softc *sc) #endif #ifndef GE_NOTX - GTeth_tx_start(sc, GE_TXPRIO_HI); + GTeth_tx_start(sc); #endif sc->sc_pcr |= ETH_EPCR_HS_512; @@ -286,10 +295,10 @@ static void GT64260eth_stop_hw(struct GTeth_softc *sc) sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING; #ifndef GE_NOTX - GTeth_tx_stop(sc, GE_WHACK_STOP); + GTeth_tx_stop(sc); #endif #ifndef GE_NORX - GTeth_rx_stop(sc, GE_WHACK_STOP); + GTeth_rx_stop(sc); #endif sc->sc_hashtable = NULL; if (GTeth_debug>0) printk(")"); @@ -523,7 +532,6 @@ static void GT64260eth_stats(struct GTeth_softc *sc) printf(" Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts); printf(" Receive Packets:%-8lu\n", ifp->if_ipackets); printf(" Receive errors:%-8lu\n", ifp->if_ierrors); - printf(" Missed Frame errors:%-8u\n", GTeth_MissedFrame_err); printf(" Framing Errors:%-8lu\n", sc->stats.frame_errors); printf(" Crc Errors:%-8lu\n", sc->stats.crc_errors); printf(" Oversized Frames:%-8lu\n", sc->stats.length_errors); @@ -536,11 +544,6 @@ static void GT64260eth_stats(struct GTeth_softc *sc) printf(" Active Txqs:%-8u\n", sc->txq_nactive); } -void GT64260eth_err() -{ - printf(" Missed Frame errors:%-8u\n", GTeth_MissedFrame_err); -} - static int GTeth_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct GTeth_softc *sc = ifp->if_softc; @@ -677,39 +680,23 @@ static void GTeth_init_rx_ring(struct GTeth_softc *sc) } } -static void GTeth_rxprio_setup(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) +void GTeth_rxprio_setup(struct GTeth_softc *sc) { - if (GTeth_debug>0) printk("GTeth_rxprio_setup(\n"); GTeth_init_rx_ring(sc); - sc->rxq_intrbits = ETH_IR_RxBuffer | ETH_IR_RxError; - - switch (rxprio) { - case GE_RXPRIO_HI: - sc->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; - break; - case GE_RXPRIO_MEDHI: - sc->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; - break; - case GE_RXPRIO_MEDLO: - sc->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; - break; - case GE_RXPRIO_LO: - sc->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; - break; - } - if (GTeth_debug>0) printk(")"); + sc->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError|ETH_IR_RxBuffer_3|ETH_IR_RxError_3; } -static int GT64260eth_rx(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) +static int GT64260eth_rx(struct GTeth_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; int nloops=0; +#ifdef GT_DEBUG if (GTeth_rx_debug>0) printk("GT64260eth_rx("); - if (GTeth_rx_debug>5) printk("(%d)", rxprio); +#endif while (sc->rxq_active > 0) { volatile struct GTeth_desc *rxd = &sc->rxq_desc[sc->rxq_fi]; @@ -749,8 +736,6 @@ static int GT64260eth_rx(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) * is new packet in the descriptor/buffer */ - if (GTeth_rx_debug>0) printk("desc%d: cmdsts=%x, len=%d\n", - sc->rxq_fi,cmdsts,byteCount); nloops++; /* * If this is not a single buffer packet with no errors @@ -758,32 +743,24 @@ static int GT64260eth_rx(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) * ignore it and go to the next packet. */ if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != - (RX_CMD_F|RX_CMD_L) || - byteCount > sc->sc_max_frame_length) { - if (GTeth_rx_debug>0) printk("Rx Error"); - --sc->rxq_active; - ifp->if_ipackets++; - ifp->if_ierrors++; + (RX_CMD_F|RX_CMD_L) || + byteCount > sc->sc_max_frame_length) { + --sc->rxq_active; + ifp->if_ipackets++; + ifp->if_ierrors++; if (cmdsts & RX_STS_OR) sc->stats.or_errors++; if (cmdsts & RX_STS_CE) sc->stats.crc_errors++; - if (cmdsts & RX_STS_MFL) sc->stats.length_errors++; - if (cmdsts & RX_STS_SF) sc->stats.frame_errors++; - /* if (cmdsts & RX_STS_M) GTeth_MissedFrame_err++;*/ + if (cmdsts & RX_STS_MFL) sc->stats.length_errors++; + if (cmdsts & RX_STS_SF) sc->stats.frame_errors++; if ((cmdsts & RX_STS_LC) || (cmdsts & RX_STS_COL)) - ifp->if_collisions++; - goto give_it_back; + ifp->if_collisions++; + goto give_it_back; } - m = sc->rxq_mbuf[sc->rxq_fi]; - sc->rxq_mbuf[sc->rxq_fi] = NULL; m->m_len = m->m_pkthdr.len = byteCount - sizeof(struct ether_header); eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - if (GTeth_rx_debug>20) { - if ( m->m_flags & M_BCAST ) printk("desc%d broadcast\n",sc->rxq_fi); - if ( m->m_flags & M_MCAST ) printk("multicast "); - } ifp->if_ipackets++; ifp->if_ibytes+=byteCount; @@ -803,7 +780,9 @@ static int GT64260eth_rx(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) sc->rxq_active++; } /* while (sc->rxq_active > 0) */ +#ifdef GT_DEBUG if (GTeth_rx_debug>0) printk(")"); +#endif return nloops; } @@ -812,7 +791,7 @@ static void GTeth_rx_setup(struct GTeth_softc *sc) if (GTeth_rx_debug>0) printk("GTeth_rx_setup("); - GTeth_rxprio_setup(sc, GE_RXPRIO_HI); + GTeth_rxprio_setup(sc); if ((sc->sc_flags & GE_RXACTIVE) == 0) { /* First Rx Descriptor Pointer 3 */ @@ -829,13 +808,11 @@ static void GTeth_rx_setup(struct GTeth_softc *sc) if (GTeth_rx_debug>0) printk(")\n"); } -static void GTeth_rx_cleanup(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) +static void GTeth_rx_cleanup(struct GTeth_softc *sc) { int i; if (GTeth_rx_debug>0) printk( "GTeth_rx_cleanup("); - if (sc->rxq_curpkt) - m_freem(sc->rxq_curpkt); for (i=0; i< RX_RING_SIZE; i++) { if (sc->rxq_mbuf[i]) { @@ -846,7 +823,7 @@ static void GTeth_rx_cleanup(struct GTeth_softc *sc, enum GTeth_rxprio rxprio) if (GTeth_rx_debug>0) printk(")"); } -static void GTeth_rx_stop(struct GTeth_softc *sc, enum GTeth_whack_op op) +static void GTeth_rx_stop(struct GTeth_softc *sc) { if (GTeth_rx_debug>0) printk( "GTeth_rx_stop("); sc->sc_flags &= ~GE_RXACTIVE; @@ -857,7 +834,7 @@ static void GTeth_rx_stop(struct GTeth_softc *sc, enum GTeth_whack_op op) do { rtems_bsp_delay(10); } while (inl(ETH0_ESDCMR) & ETH_ESDCMR_AR); - GTeth_rx_cleanup(sc, GE_RXPRIO_HI); + GTeth_rx_cleanup(sc); if (GTeth_rx_debug>0) printk(")"); } @@ -929,14 +906,12 @@ static int txq_high_limit(struct GTeth_softc *sc) return 0; } -static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m, enum GTeth_txprio txprio) +static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m) { volatile struct GTeth_desc *txd = &sc->txq_desc[sc->txq_lo]; unsigned intrmask = sc->sc_intrmask; unsigned index= sc->txq_lo; - if (GTeth_debug>0) printk("sendpacket("); - /* * The end-of-list descriptor we put on last time is the starting point * for this packet. The GT is supposed to terminate list processing on @@ -987,7 +962,8 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m, enum GTe txd->ed_bufptr = (unsigned) mtod(m, void*); txd->ed_lencnt = m->m_len << 16; - txd->ed_cmdsts = TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O|TX_CMD_F|TX_CMD_EI; + /*txd->ed_cmdsts = TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O|TX_CMD_F|TX_CMD_EI;*/ + txd->ed_cmdsts = 0x80c70000; #ifdef GT_DEBUG printk("len = %d, cmdsts 0x%x ", m->m_len,txd->ed_cmdsts); @@ -995,13 +971,14 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m, enum GTe /* * Tell the SDMA engine to "Fetch!" - * Start Tx high and Tx low. + * Start Tx high. */ - outl(ETH_ESDCMR_TXDH,ETH0_ESDCMR); sc->txq_nactive++; + outl(0x800080, ETH0_ESDCMR); /* ETH_ESDCMR_TXDH| ETH_ESDCMR_ERD */ if ( ++sc->txq_lo == TX_RING_SIZE) sc->txq_lo = 0; sc->txq_free--; +#if 0 /* * Since we have put an item into the packet queue, we now want * an interrupt when the transmit queue finishes processing the @@ -1012,6 +989,7 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m, enum GTe sc->sc_intrmask = intrmask; outl(sc->sc_intrmask, ETH0_EIMR); } +#endif #if 0 printk("EICR= %x, EIMR= %x ", inl(ETH0_EICR), inl(ETH0_EIMR)); @@ -1020,11 +998,10 @@ static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m, enum GTe printk("pcr %x, pcxr %x DMA dcr %x cmr %x\n", inl(ETH0_EPCR), inl(ETH0_EPCXR), inl(ETH0_ESDCR), inl(ETH0_ESDCMR)); #endif - if (GTeth_debug>0) printk(")"); return 1; } -static unsigned GTeth_txq_done(struct GTeth_softc *sc, enum GTeth_txprio txprio) +static unsigned GTeth_txq_done(struct GTeth_softc *sc) { if (GTeth_debug>0) printk("Txdone(" ); @@ -1071,7 +1048,7 @@ static unsigned GTeth_txq_done(struct GTeth_softc *sc, enum GTeth_txprio txprio) return(1); } -static void GTeth_tx_start(struct GTeth_softc *sc, enum GTeth_txprio txprio) +static void GTeth_tx_start(struct GTeth_softc *sc) { int i; volatile struct GTeth_desc *txd; @@ -1117,79 +1094,45 @@ static void GTeth_tx_start(struct GTeth_softc *sc, enum GTeth_txprio txprio) printk("next desc. @ 0x%x\n",txd->ed_nxtptr); #endif } - - switch (txprio) { - case GE_TXPRIO_HI: - sc->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; - sc->txq_esdcmrbits = ETH_ESDCMR_TXDH; /* Start Tx high */ - sc->txq_epsrbits = ETH_EPSR_TxHigh; - /* offset to current tx desc ptr reg */ - sc->txq_ectdp = (caddr_t)ETH0_ECTDP1; - /* Current Tx Desc Pointer 1 */ - outl(sc->txq_desc_busaddr,ETH0_ECTDP1); -#ifdef GT_DEBUG - printk("ETH0_ECTDP1 %x",inl(ETH0_ECTDP1)); -#endif - break; - - case GE_TXPRIO_LO: - sc->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; - sc->txq_esdcmrbits = ETH_ESDCMR_TXDL; /* Start TX low */ - sc->txq_epsrbits = ETH_EPSR_TxLow; - sc->txq_ectdp = (caddr_t)ETH0_ECTDP0; - /* Current Tx Desc Pointer 0 */ - outl(sc->txq_desc_busaddr,ETH0_ECTDP0); -#ifdef GT_DEBUG - printk("ETH0_ECTDP1 %x",inl(ETH0_ECTDP0)); -#endif - break; - - default: - printk("Invalid Txq prio\n"); - break; - } + sc->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; + sc->txq_esdcmrbits = ETH_ESDCMR_TXDH; /* Start Tx high */ + sc->txq_epsrbits = ETH_EPSR_TxHigh; + /* offset to current tx desc ptr reg */ + sc->txq_ectdp = (caddr_t)ETH0_ECTDP1; + /* Current Tx Desc Pointer 1 */ + outl(sc->txq_desc_busaddr,ETH0_ECTDP1); + #ifdef GT_DEBUG printk(")\n"); #endif } -static void GTeth_tx_cleanup(struct GTeth_softc *sc,enum GTeth_txprio txprio,int flush) +static void GTeth_tx_cleanup(struct GTeth_softc *sc) { int i; - if (GTeth_debug>0) printk( "GTeth_tx_cleanup("); - - if (!flush) { - if (GTeth_debug>0) printk("--"); - return; - } for (i=0; i< TX_RING_SIZE; i++) { if (sc->txq_mbuf[i]) { m_freem(sc->txq_mbuf[i]); sc->txq_mbuf[i]=0; } } - if (GTeth_debug>0) printk(")"); } -static void GTeth_tx_stop(struct GTeth_softc *sc, enum GTeth_whack_op op) +static void GTeth_tx_stop(struct GTeth_softc *sc) { - if (GTeth_debug>0) printk("GTeth_tx_stop( "); - /* SDMA command register : stop Tx high and low */ outl(ETH_ESDCMR_STDH|ETH_ESDCMR_STDL, ETH0_ESDCMR); - GTeth_txq_done(sc, GE_TXPRIO_HI); + GTeth_txq_done(sc); sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| - ETH_IR_TxEndLow |ETH_IR_TxBufferLow); - GTeth_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); + ETH_IR_TxEndLow |ETH_IR_TxBufferLow); + GTeth_tx_cleanup(sc); sc->arpcom.ac_if.if_timer = 0; - if (GTeth_debug>0) printk(")"); } - /* TOCHECK : Should it be about rx or tx ? */ static void GTeth_ifchange(struct GTeth_softc *sc) { @@ -1227,7 +1170,9 @@ static int GTeth_hash_compute(struct GTeth_softc *sc,unsigned char eaddr[ETHER_A add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); - if (GTeth_debug>0) printk("eaddr= %s add1:%x add0:%x\n", ether_sprintf(eaddr), add1, add0); +#ifdef GT_DEBUG + printk("eaddr= %s add1:%x add0:%x\n", ether_sprintf1(eaddr), add1, add0); +#endif /* * hashResult is the 15 bits Hash entry address. @@ -1250,7 +1195,9 @@ static int GTeth_hash_compute(struct GTeth_softc *sc,unsigned char eaddr[ETHER_A * hashResult[14:9] = ethernetADD[7:2] */ result |= (add0 & ~3) << 7; /* excess bits will be masked */ - if (GTeth_debug>0) printk("hash result %x ", result & 0x7fff); +#ifdef GT_DEBUG + printk("hash result %x ", result & 0x7fff); +#endif } else { #define TRIBITFLIP 073516240 /* yes its in octal */ /* @@ -1274,9 +1221,14 @@ static int GTeth_hash_compute(struct GTeth_softc *sc,unsigned char eaddr[ETHER_A */ result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; - if (GTeth_debug>5) printk("1(%#x)", result); +#ifdef GT_DEBUG + printk("1(%#x)", result); +#endif } - if (GTeth_debug>0) printk(")"); +#ifdef GT_DEBUG + printk(")"); +#endif + /* 1/2K address filtering (MOTLoad default )? ->16KB memory required * or 8k address filtering ? -> 256KB memory required */ @@ -1292,15 +1244,18 @@ static int GTeth_hash_entry_op(struct GTeth_softc *sc, enum GTeth_hash_op op, int hash; int maybe_hash = 0; - if (GTeth_debug>0) printk("GTeth_hash_entry_op(prio %d ", prio); +#ifdef GT_DEBUG + printk("GTeth_hash_entry_op(prio %d ", prio); +#endif hash = GTeth_hash_compute(sc, eaddr); if (sc->sc_hashtable == NULL) { rtems_panic("hashtable == NULL!"); } - if (GTeth_debug>0) printk("Hash computed %x eaddr %s\n", hash,ether_sprintf(eaddr)); - +#ifdef GT_DEBUG + printk("Hash computed %x eaddr %s\n", hash,ether_sprintf1(eaddr)); +#endif /* * Assume we are going to insert so create the hash entry we @@ -1320,13 +1275,15 @@ static int GTeth_hash_entry_op(struct GTeth_softc *sc, enum GTeth_hash_op op, */ hash &= (sc->sc_hashmask / sizeof(he)); +#ifdef GT_DEBUG if (GTeth_debug>0) { unsigned val1, val2; val1= he & 0xffffffff; val2= (he >>32) & 0xffffffff; - printk("Hash addr value %x%x, entry %x\n",val2,val1, hash); + printk("Hash addr value %x%x, entry %x\n",val2,val1, hash); } +#endif for (limit = HSH_LIMIT; limit > 0 ; --limit) { /* @@ -1424,7 +1381,9 @@ static int GTeth_hash_fill(struct GTeth_softc *sc) struct ether_multi *enm; int error; - if (GTeth_debug>0) printk( "GTeth_hash_fill("); +#ifdef GT_DEBUG + printk( "GTeth_hash_fill("); +#endif error = GTeth_hash_entry_op(sc,GE_HASH_ADD,GE_RXPRIO_HI,sc->arpcom.ac_enaddr); if (error) { @@ -1452,7 +1411,9 @@ static int GTeth_hash_fill(struct GTeth_softc *sc) } ETHER_NEXT_MULTI(step, enm); } - if (GTeth_debug>0) printk(")\n"); +#ifdef GT_DEBUG + printk(")\n"); +#endif return error; } @@ -1475,8 +1436,9 @@ static void GTeth_hash_init(struct GTeth_softc *sc) sc->sc_hashmask = HASH_DRAM_SIZE - 1; memset((void *)sc->sc_hashtable, 0,HASH_DRAM_SIZE); - if (GTeth_debug>0) - printk("hashtable addr:%x, mask %x)\n", sc->sc_hashtable,sc->sc_hashmask); +#ifdef GT_DEBUG + printk("hashtable addr:%x, mask %x)\n", sc->sc_hashtable,sc->sc_hashmask); +#endif } static void GT64260eth_error(struct GTeth_softc *sc) @@ -1548,29 +1510,33 @@ static void GT64260eth_daemon(void *arg) if (KILL_EVENT & events) break; #ifndef GE_NORX - if (events & RX_EVENT) GT64260eth_rx(sc,GE_RXPRIO_HI); + if (events & RX_EVENT) GT64260eth_rx(sc); +#endif +#if 0 + printk("%x ", inb(ETH0_EPSR)); + if ( ((i++) % 15)==0) printk("\n"); #endif /* clean up and try sending packets */ do { -#if 1 +#if 0 if (gpp_int_error!=0) { printk("GPP interrupt error %d\n", gpp_int_error); gpp_int_error=0; } #endif - if (sc->txq_nactive) GTeth_txq_done(sc, GE_TXPRIO_HI); + if (sc->txq_nactive) GTeth_txq_done(sc); while (sc->txq_free>0) { if (sc->txq_free>TXQ_HiLmt_OFF) { m=0; IF_DEQUEUE(&ifp->if_snd,m); if (m==0) break; - GT64260eth_sendpacket(sc, m, GE_TXPRIO_HI); + GT64260eth_sendpacket(sc, m); } else { - if (txq_high_limit(sc)) - break; + GTeth_txq_done(sc); + break; } } /* we leave this loop diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c index c36191e33e..4615464491 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c @@ -28,18 +28,18 @@ unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet) { unsigned int pcidata, pcidata1; - int PciNumber; + int PciLocal, busNumber=0; /* On the mvme5500 board, the GT64260B system controller had the MCP * signal pulled up high. Thus, the MCP signal is not used as it is * on other boards such as mvme2307. */ if (enableMCP) return(-1); - for (PciNumber=0; PciNumber<1; PciNumber++) { - PCIx_read_config_dword(PciNumber, 0, + for (PciLocal=0; PciLocal<1; PciLocal++ ) { + pci_read_config_dword(busNumber, 0, 0, - PCI0_COMMAND+(PciNumber * 0x80), + PCI_COMMAND, &pcidata); if (!quiet) @@ -52,21 +52,22 @@ unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet) pcidata1= pcidata; pcidata1 |= PCI_STATUS_CLRERR_MASK; pcidata1 |= 0x140; - PCIx_write_config_dword(PciNumber, 0, + pci_write_config_dword(busNumber, 0, 0, - PCI0_COMMAND+(PciNumber * 0x80), + PCI_COMMAND, pcidata1); - PCIx_read_config_dword(PciNumber, 0, + pci_read_config_dword(busNumber, 0, 0, - PCI0_COMMAND+(PciNumber * 0x80), + PCI_COMMAND, &pcidata1); if (!quiet) printk("After _BSP_clear_hostbridge_errors(): sts 0x%x\n", pcidata1); if (pcidata1 & HOSTBRIDGET_ERROR) printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n"); + busNumber += BSP_MAX_PCI_BUS_ON_PCI0; } return(pcidata & HOSTBRIDGET_ERROR); } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h b/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h index d96defdb96..7548a9304c 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h @@ -38,6 +38,16 @@ */ #define PCI_ARBCTL_EN (1<<31) +#define PCI_COMMAND_SB_DIS 0x2000 /* PCI configuration read will stop + * acting as sync barrier transactin + */ + +#define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4 + +#define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 + +#define PCI_STATUS_CLRERR_MASK 0xf9000000 /* */ + #define PCI_BARE_IntMemEn 0x200 #define PCI_ACCCTLBASEL_PrefetchEn 0x0001000 @@ -82,8 +92,6 @@ #define PCI_SNOOP_TOP1 0x1f18 #define PCI0_CMD_CNTL 0xc00 -#define PCI0_CONFIG_ADDR 0xcf8 -#define PCI0_CONFIG_DATA 0xcfc #define PCI1_P2P_CONFIG 0x1d94 #define PCI1_CMD_CNTL 0xc80 diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c index 3afb214ea4..6d9f842426 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c @@ -11,15 +11,16 @@ * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. + * http://www.rtems.com/rtems/license.html. * - * $Id$ + * pci.c,v 1.2 2002/05/14 17:10:16 joel Exp * * Copyright 2004, Brookhaven National Laboratory and * Shuchen K. Feng, , 2004 * - modified and added support for MVME5500 board * - added 2nd PCI support for the mvme5500/GT64260 PCI bridge - * + * - added bus support for the expansion of PMCSpan, thanks to + * Peter Dufault (dufault@hda.com) for inputs. */ #define PCI_MAIN @@ -34,18 +35,33 @@ #include #define PCI_DEBUG 0 -#define PCI_PRINT 1 +#define PCI_PRINT 0 + +/* allow for overriding these definitions */ +#ifndef PCI_CONFIG_ADDR +#define PCI_CONFIG_ADDR 0xcf8 +#endif +#ifndef PCI_CONFIG_DATA +#define PCI_CONFIG_DATA 0xcfc +#endif + +#ifndef PCI1_CONFIG_ADDR +#define PCI1_CONFIG_ADDR 0xc78 +#endif +#ifndef PCI1_CONFIG_DATA +#define PCI1_CONFIG_DATA 0xc7c +#endif #define PCI_INVALID_VENDORDEVICEID 0xffffffff #define PCI_MULTI_FUNCTION 0x80 #define HOSTBRIDGET_ERROR 0xf0000000 -typedef unsigned char unchar; - -#define MAX_NUM_PCI_DEVICES 20 +/* define a shortcut */ +#define pci BSP_pci_configuration +typedef unsigned char unchar; static int numPCIDevs=0; -extern void PCI_interface(), pciAccessInit(); +extern void pci_interface(); /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for * PCI Configuration Address Register @@ -60,145 +76,196 @@ unchar ucMaxPCIBus=0; /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1. */ -int PCIx_read_config_byte(int npci, unchar bus, unchar dev, -unchar func, unchar offset, unchar *val) +static int direct_pci_read_config_byte(unchar bus,unchar dev,unchar func, +unchar offset,unchar *val) { + volatile unsigned char *config_addr, *config_data; + + if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { + bus-=BSP_MAX_PCI_BUS_ON_PCI0; + config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; + config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; + } + else { + config_addr = pci.pci_config_addr; + config_data = pci.pci_config_data; + } *val = 0xff; if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; - outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); - *val = inb(BSP_pci_config[npci].pci_config_data + (offset&3)); +#if 0 + printk("addr %x, data %x, pack %x \n", config_addr, + config_data,pciConfigPack(bus,dev,func,offset)); +#endif + outl(pciConfigPack(bus,dev,func,offset),config_addr); + *val = inb(config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; } -int PCIx_read_config_word(int npci, unchar bus, unchar dev, +static int direct_pci_read_config_word(unchar bus, unchar dev, unchar func, unchar offset, unsigned short *val) { + volatile unsigned char *config_addr, *config_data; + + if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { + bus-=BSP_MAX_PCI_BUS_ON_PCI0; + config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; + config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; + } + else { + config_addr = (volatile unsigned char*) pci.pci_config_addr; + config_data = (volatile unsigned char*) pci.pci_config_data; + } + *val = 0xffff; if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; - outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); - *val = inw(BSP_pci_config[npci].pci_config_data + (offset&2)); +#if 0 + printk("addr %x, data %x, pack %x \n", config_addr, + config_data,pciConfigPack(bus,dev,func,offset)); +#endif + outl(pciConfigPack(bus,dev,func,offset),config_addr); + *val = inw(config_data + (offset&2)); return PCIBIOS_SUCCESSFUL; } -int PCIx_read_config_dword(int npci, unchar bus, unchar dev, +static int direct_pci_read_config_dword(unchar bus, unchar dev, unchar func, unchar offset, unsigned int *val) { + volatile unsigned char *config_addr, *config_data; + + if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { + bus-=BSP_MAX_PCI_BUS_ON_PCI0; + config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; + config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; + } + else { + config_addr = (volatile unsigned char*) pci.pci_config_addr; + config_data = (volatile unsigned char*) pci.pci_config_data; + } + *val = 0xffffffff; if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; #if 0 - printk("addr %x, data %x, pack %x \n", BSP_pci_config[npci].pci_config_addr, - BSP_pci_config[npci].pci_config_data,pciConfigPack(bus,dev,func,offset)); + printk("addr %x, data %x, pack %x \n", config_addr, + pci.pci_config_data,pciConfigPack(bus,dev,func,offset)); #endif - outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); - *val = inl(BSP_pci_config[npci].pci_config_data); + outl(pciConfigPack(bus,dev,func,offset),config_addr); + *val = inl(config_data); return PCIBIOS_SUCCESSFUL; } -int PCIx_write_config_byte(int npci, unchar bus, unchar dev, -unchar func, unchar offset, unchar val) +static int direct_pci_write_config_byte(unchar bus, unchar dev,unchar func, unchar offset, unchar val) { + volatile unsigned char *config_addr, *config_data; + + if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { + bus-=BSP_MAX_PCI_BUS_ON_PCI0; + config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; + config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; + } + else { + config_addr = pci.pci_config_addr; + config_data = pci.pci_config_data; + } + if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; +#if 0 + printk("addr %x, data %x, pack %x \n", config_addr, + config_data,pciConfigPack(bus,dev,func,offset)); +#endif - outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); - outb(val, BSP_pci_config[npci].pci_config_data + (offset&3)); + outl(pciConfigPack(bus,dev,func,offset), config_addr); + outb(val, config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; } -int PCIx_write_config_word(int npci, unchar bus, unchar dev, -unchar func, unchar offset, unsigned short val) +static int direct_pci_write_config_word(unchar bus, unchar dev,unchar func, unchar offset, unsigned short val) { + volatile unsigned char *config_addr, *config_data; + + if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { + bus-=BSP_MAX_PCI_BUS_ON_PCI0; + config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; + config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; + } + else { + config_addr = (volatile unsigned char*) pci.pci_config_addr; + config_data = (volatile unsigned char*) pci.pci_config_data; + } + if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; - outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); - outw(val, BSP_pci_config[npci].pci_config_data + (offset&3)); +#if 0 + printk("addr %x, data %x, pack %x \n", config_addr, + config_data,pciConfigPack(bus,dev,func,offset)); +#endif + outl(pciConfigPack(bus,dev,func,offset),config_addr); + outw(val, config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; } -int PCIx_write_config_dword(int npci,unchar bus,unchar dev, -unchar func, unchar offset, unsigned int val) +static int direct_pci_write_config_dword(unchar bus,unchar dev,unchar func, unchar offset, unsigned int val) { + volatile unsigned char *config_addr, *config_data; + + if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { + bus-=BSP_MAX_PCI_BUS_ON_PCI0; + config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR; + config_data = (volatile unsigned char *) PCI1_CONFIG_DATA; + } + else { + config_addr = (volatile unsigned char*) pci.pci_config_addr; + config_data = (volatile unsigned char*) pci.pci_config_data; + } + if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; #if 0 - printk("addr %x, data %x, pack %x \n", BSP_pci_config[npci].pci_config_addr, - BSP_pci_config[npci].pci_config_data,pciConfigPack(bus,dev,func,offset)); + printk("addr %x, data %x, pack %x \n", config_addr, + config_data,pciConfigPack(bus,dev,func,offset)); #endif - outl(pciConfigPack(bus,dev,func,offset),BSP_pci_config[npci].pci_config_addr); - outl(val,BSP_pci_config[npci].pci_config_data); + outl(pciConfigPack(bus,dev,func,offset),config_addr); + outl(val,config_data); return PCIBIOS_SUCCESSFUL; } -/* backwards compatible with other PPC board for the vmeUniverse.c - * Note: We must override the default with these in pci.h - */ -int pci_bsp_read_config_byte(unchar bus, unchar dev,unchar func,unchar offset, -unchar *val) -{ - return(PCIx_read_config_byte(0, bus, dev, func, offset, val)); -} - -int pci_bsp_read_config_word(unchar bus, unchar dev, -unchar func, unchar offset, unsigned short *val) -{ - return(PCIx_read_config_word(0, bus, dev, func, offset, val)); -} - -int pci_bsp_read_config_dword(unchar bus, unchar dev, -unchar func, unchar offset, unsigned int *val) -{ - return(PCIx_read_config_dword(0, bus, dev, func, offset, val)); -} - -int pci_bsp_write_config_byte(unchar bus, unchar dev, -unchar func, unchar offset, unchar val) -{ - return(PCIx_write_config_byte(0, bus, dev, func, offset, val)); -} - -int pci_bsp_write_config_word(unchar bus, unchar dev, -unchar func, unchar offset, unsigned short val) -{ - return(PCIx_write_config_word(0, bus, dev, func, offset, val)); -} - -int pci_bsp_write_config_dword(unchar bus,unchar dev, -unchar func, unchar offset, unsigned int val) -{ - return(PCIx_write_config_dword(0, bus, dev, func, offset, val)); -} +const pci_config_access_functions pci_direct_functions = { + direct_pci_read_config_byte, + direct_pci_read_config_word, + direct_pci_read_config_dword, + direct_pci_write_config_byte, + direct_pci_write_config_word, + direct_pci_write_config_dword +}; -pci_bsp_config BSP_pci_config[2] = { - {PCI0_CONFIG_ADDR,PCI0_CONFIG_DATA/*,&pci_functions*/}, - {PCI1_CONFIG_ADDR,PCI1_CONFIG_DATA/*,&pci_functions*/} -}; +pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR, + (volatile unsigned char*)PCI_CONFIG_DATA, + &pci_direct_functions}; /* - * This routine determines the maximum bus number in the system + * This routine determines the maximum bus number in the system. + * The PCI_SUBORDINATE_BUS is not supported in GT6426xAB. Thus, + * it's not used. + * */ int pci_initialize() { - int PciNumber; + int deviceFound; unchar ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs; unsigned int ulHeader; - unsigned int pcidata, ulDeviceID; -#if PCI_DEBUG - unsigned int data, pcidata, ulClass; - unsigned short sdata; -#endif + unsigned int pcidata, ulClass, ulDeviceID; - PCI_interface(); + pci_interface(); /* - * Scan PCI0 and PCI1 bus0 + * Scan PCI0 and PCI1 buses */ - for (PciNumber=0; PciNumber < 2; PciNumber++) { - pciAccessInit(PciNumber); - for (ucBusNumber=0; ucBusNumber< 2; ucBusNumber++) { + for (ucBusNumber=0; ucBusNumber MAX_NUM_PCI_DEVICES) { - BSP_panic("Too many PCI devices found; increase MAX_NUM_PCI_DEVICES in pcicache.c\n"); + if (++numPCIDevs > PCI_MAX_DEVICES) { + BSP_panic("Too many PCI devices found; increase PCI_MAX_DEVICES in pci.h\n"); } + if (!deviceFound) deviceFound=1; switch(ulDeviceID) { case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)): #if PCI_PRINT - printk("Marvell GT6426xA/B hostbridge detected at PCI%d bus%d slot%d\n", - PciNumber,ucBusNumber,ucSlotNumber); + printk("Marvell GT6426xA/B hostbridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); #endif - ucMaxPCIBus ++; break; case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)): #if PCI_PRINT - printk("PLX PCI6154 PCI-PCI bridge detected at PCI%d bus%d slot%d\n", - PciNumber,ucBusNumber,ucSlotNumber); + printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); #endif - ucMaxPCIBus ++; break; case PCI_VENDOR_ID_TUNDRA: #if PCI_PRINT - printk("TUNDRA PCI-VME bridge detected at PCI%d bus%d slot%d\n", - PciNumber,ucBusNumber,ucSlotNumber); + printk("TUNDRA PCI-VME bridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); #endif - ucMaxPCIBus ++; break; case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)): #if PCI_PRINT - printk("INTEL 82544EI COPPER network controller detected at PCI%d bus%d slot%d\n", - PciNumber,ucBusNumber,ucSlotNumber); + printk("INTEL 82544EI COPPER network controller detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); #endif - ucMaxPCIBus ++; break; - default : -#if PCI_PRINT - printk("PCI%d Bus%d Slot%d DeviceID 0x%x \n", - PciNumber,ucBusNumber,ucSlotNumber, ulDeviceID); + case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)): + #if PCI_PRINT + printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n", + ucBusNumber,ucSlotNumber); #endif + break; + default : + printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n", + ucBusNumber,ucSlotNumber, ulDeviceID); break; } + #if PCI_DEBUG - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_BASE_ADDRESS_0, + PCI_BASE_ADDRESS_0, &data); - printk("PCI%d_BASE_ADDRESS_0 0x%x \n",PciNumber, data); - PCIx_read_config_dword(PciNumber, ucBusNumber, + printk("Bus%d BASE_ADDRESS_0 0x%x \n",ucBusNumber, data); + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_BASE_ADDRESS_1, + PCI_BASE_ADDRESS_1, &data); - printk("PCI%d_BASE_ADDRESS_1 0x%x \n",PciNumber, data); - PCIx_read_config_dword(PciNumber, ucBusNumber, + printk("Bus%d BASE_ADDRESS_1 0x%x \n",ucBusNumber, data); + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_BASE_ADDRESS_2, + PCI_BASE_ADDRESS_2, &data); - printk("PCI%d_BASE_ADDRESS_2 0x%x \n",PciNumber, data); + printk("Bus%d BASE_ADDRESS_2 0x%x \n", ucBusNumber, data); - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_BASE_ADDRESS_3, + PCI_BASE_ADDRESS_3, &data); - printk("PCI%d_BASE_ADDRESS_3 0x%x \n",PciNumber, data); + printk("Bus%d BASE_ADDRESS_3 0x%x \n", ucBusNumber, data); - PCIx_read_config_word(PciNumber, ucBusNumber, + pci_read_config_word(ucBusNumber, ucSlotNumber, 0, - PCI0_INTERRUPT_LINE, + PCI_INTERRUPT_LINE, &sdata); - printk("PCI%d_INTERRUPT_LINE 0x%x \n",PciNumber, sdata); + printk("Bus%d INTERRUPT_LINE 0x%x \n", ucBusNumber, sdata); /* We always enable internal memory. */ - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_MEM_BASE_ADDR, + PCI_MEM_BASE_ADDR, &pcidata); - printk("PCI%d_MEM_BASE_ADDR 0x%x \n", PciNumber,pcidata); + printk("Bus%d MEM_BASE_ADDR 0x%x \n", ucBusNumber,pcidata); /* We always enable internal IO. */ - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_IO_BASE_ADDR, + PCI_IO_BASE_ADDR, &pcidata); - printk("PCI%d_IO_BASE_ADDR 0x%x \n", PciNumber,pcidata); + printk("Bus%d IO_BASE_ADDR 0x%x \n", ucBusNumber,pcidata); #endif - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_CACHE_LINE_SIZE, + PCI_CACHE_LINE_SIZE, &ulHeader); if ((ulHeader>>16)&PCI_MULTI_FUNCTION) ucNumFuncs=PCI_MAX_FUNCTIONS; @@ -308,41 +377,38 @@ int pci_initialize() ucNumFuncs=1; #if PCI_DEBUG - printk("PCI%d Slot 0x%x HEADER/LAT/CACHE 0x%x \n", - PciNumber,ucSlotNumber, ulHeader); + printk("Bus%d Slot 0x%x HEADER/LAT/CACHE 0x%x \n", + ucBusNumber, ucSlotNumber, ulHeader); +#endif for (ucFnNumber=1;ucFnNumber MAX_NUM_PCI_DEVICES) { - BSP_panic("Too many PCI devices found; increase MAX_NUM_PCI_DEVICES in pcicache.c\n"); - } /* This slot/function has a device fitted.*/ - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, ucFnNumber, - PCI0_CLASS_REVISION, - &ulClass); - printk("PCI%d Slot 0x%x Func %d classID 0x%x \n",PciNumber,ucSlotNumber, + PCI_CLASS_REVISION, + &ulClass); +#if PCI_DEBUG + printk("Bus%d Slot 0x%x Func %d classID 0x%x \n",ucBusNumber,ucSlotNumber, ucFnNumber, ulClass); +#endif - ulClass >>= 16; - if (ulClass == PCI_CLASS_GT6426xAB) - printk("GT64260-PCI%d bridge found \n", PciNumber); } -#endif - PCIx_read_config_dword(PciNumber, ucBusNumber, + + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_COMMAND, + PCI_COMMAND, &pcidata); #if PCI_DEBUG printk("MOTLoad command staus 0x%x, ", pcidata); @@ -352,26 +418,32 @@ int pci_initialize() pcidata |= PCI_STATUS_CLRERR_MASK; /* Enable bus,I/O and memory master access. */ pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY); - PCIx_write_config_dword(PciNumber, ucBusNumber, + pci_write_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_COMMAND, + PCI_COMMAND, pcidata); - PCIx_read_config_dword(PciNumber, ucBusNumber, + pci_read_config_dword(ucBusNumber, ucSlotNumber, 0, - PCI0_COMMAND, + PCI_COMMAND, &pcidata); #if PCI_DEBUG printk("Now command/staus 0x%x\n", pcidata); #endif - } - } - } /* PCI number */ + if (deviceFound) ucMaxPCIBus++; + } /* for (ucBusNumber=0; ucBusNumber -#define PCI0_VENDOR_ID 0x00 /* 16 bits */ -#define PCI0_DEVICE_ID 0x02 /* 16 bits */ -#define PCI0_COMMAND 0x04 /* 16 bits */ - -#define PCI_COMMAND_SB_DIS 0x2000 /* PCI configuration read will stop - * acting as sync barrier transaction - */ -#define PCI_STATUS_CLRERR_MASK 0xf9000000 /* */ - -#define PCI0_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 - revision */ -#define PCI0_REVISION_ID 0x08 /* Revision ID */ -#define PCI0_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ -#define PCI0_CLASS_DEVICE 0x0a /* Device class */ - -#define PCI0_CACHE_LINE_SIZE 0x0c /* 8 bits */ -#define PCI0_LATENCY_TIMER 0x0d /* 8 bits */ -#define PCI0_HEADER_TYPE 0x0e /* 8 bits */ - -#define PCI0_CAPABILITY_LIST_POINTER 0x34 - -/* 0x38-0x3b are reserved */ -#define PCI0_INTERRUPT_LINE 0x3c /* 8 bits */ -#define PCI0_INTERRUPT_PIN 0x3d /* 8 bits */ -#define PCI0_MIN_GNT 0x3e /* 8 bits */ -#define PCI0_MAX_LAT 0x3f /* 8 bits */ - -/* - * Under PCI1, each device has 256 bytes of configuration address space, - * of which the first 64 bytes are standardized as follows: - */ -#define PCI1_VENDOR_ID 0x80 /* 16 bits */ -#define PCI1_DEVICE_ID 0x82 /* 16 bits */ -#define PCI1_COMMAND 0x84 /* 16 bits */ -#define PCI1_STATUS 0x86 /* 16 bits */ -#define PCI1_CLASS_REVISION 0x88 /* High 24 bits are class, low 8 - revision */ -#define PCI1_REVISION_ID 0x88 /* Revision ID */ -#define PCI1_CLASS_PROG 0x89 /* Reg. Level Programming Interface */ -#define PCI1_CLASS_DEVICE 0x8a /* Device class */ - -#define PCI1_CACHE_LINE_SIZE 0x8c /* 8 bits */ -#define PCI1_LATENCY_TIMER 0x8d /* 8 bits */ -#define PCI1_HEADER_TYPE 0x8e /* 8 bits */ -#define PCI1_BIST 0x8f /* 8 bits */ - -#define PCI1_BASE_ADDRESS_0 0x90 /* 32 bits */ -#define PCI1_BASE_ADDRESS_1 0x94 /* 32 bits [htype 0,1 only] */ -#define PCI1_BASE_ADDRESS_2 0x98 /* 32 bits [htype 0 only] */ -#define PCI1_BASE_ADDRESS_3 0x9c /* 32 bits */ -#define PCI1_MEM_BASE_ADDR 0xa0 /* 32 bits */ -#define PCI1_IO_BASE_ADDR 0xa4 /* 32 bits */ - -/* Header type 0 (normal devices) */ -#define PCI1_CARDBUS_CIS 0xa8 -#define PCI1_SUBSYSTEM_VENDOR_ID 0xac -#define PCI1_SUBSYSTEM_ID 0xae -#define PCI1_ROM_ADDRESS 0xb0 /* Bits 31..11 are address, 10..1 reserved */ -#define PCI1_CAPABILITY_LIST_POINTER 0xb4 - -/* 0xb8-0xbb are reserved */ -#define PCI1_INTERRUPT_LINE 0xbc /* 8 bits */ -#define PCI1_INTERRUPT_PIN 0xbd /* 8 bits */ -#define PCI1_MIN_GNT 0xbe /* 8 bits */ -#define PCI1_MAX_LAT 0xbf /* 8 bits */ +#define PCI_CAPABILITY_LIST_POINTER 0x34 /* */ /* Device classes and subclasses */ -#define PCI_CLASS_GT6426xAB 0x0580 /* */ - +#define PCI_CLASS_GT6426xAB_BRIDGE_PCI 0x0580 /* */ + /* * Vendor and card ID's: sort these numerically according to vendor * (and according to card ID within vendor). Send all updates to @@ -107,82 +42,18 @@ #define PCI_VENDOR_ID_PLX2 0x3388 /* */ #define PCI_DEVICE_ID_PLX2_PCI6154_HB2 0x26 /* */ -#define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008 /* */ - -typedef struct { - unsigned int pci_config_addr; - unsigned int pci_config_data; - /* const pci_config_access_functions* pci_functions;*/ -} pci_bsp_config; - -extern pci_bsp_config BSP_pci_config[2]; - -#ifndef PCI_MAIN -extern int PCIx_read_config_byte(); -extern int PCIx_read_config_word(); -extern int PCIx_read_config_dword(); -extern int PCIx_write_config_byte(); -extern int PCIx_write_config_word(); -extern int PCIx_write_config_dword(); -#endif - -extern int pci_bsp_read_config_byte( - unsigned char bus, - unsigned char dev, - unsigned char func, - unsigned char offset, - unsigned char *val -); - -extern int pci_bsp_read_config_word( - unsigned char bus, - unsigned char dev, - unsigned char func, - unsigned char offset, - unsigned short *val -); - -extern int pci_bsp_read_config_dword( - unsigned char bus, - unsigned char dev, - unsigned char func, - unsigned char offset, - unsigned int *val -); - -extern int pci_bsp_write_config_byte( - unchar bus, - unchar dev, - unchar func, - unchar offset, - unchar val -); - -extern int pci_bsp_write_config_word( - unchar bus, - unchar dev, - unchar func, - unchar offset, - unsigned short val -); - -extern int pci_bsp_write_config_dword( - unchar bus, - unchar dev, - unchar func, - unchar offset, - unsigned int val -); - - -/* - * Override the default pci_read_config... for vmeUniverse.c - */ -#define BSP_PCI_CONFIG_IN_LONG pci_bsp_read_config_dword -#define BSP_PCI_CONFIG_IN_BYTE pci_bsp_read_config_byte +#define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008 /* */ +struct _pin_routes +{ + int pin, int_name[4]; +}; +struct _int_map +{ + int bus, slot, opts; + struct _pin_routes pin_route[5]; +}; -int BSP_PCIxFindDevice(unsigned short vendorid, unsigned short deviceid, - int instance, int pciNum, int *pbus, int *pdev, int *pfun ); +void FixupPCI( struct _int_map *, int (*swizzler)(int,int) ); -#endif /* BSP_PCI_H */ +#endif /* RTEMS_PCI_H */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c index b44d5d3f78..c1a56775d4 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c @@ -82,7 +82,9 @@ #define ADDR_PIPELINE 0x00020000 -void PCI_interface() +void pciAccessInit(); + +void pci_interface() { unsigned int data; @@ -113,31 +115,32 @@ void PCI_interface() outl(0xc0060002, DLOCK_ORDER_REG); outl(0x07fff600, CNT_SYNC_REG); #else - outl(inl(PCI0_CMD_CNTL)|PCI_COMMAND_SB_DIS, PCI0_CMD_CNTL); + outl(inl(PCI_CMD_CNTL)|PCI_COMMAND_SB_DIS, PCI_CMD_CNTL); #endif /* asserts SERR upon various detection */ outl(0x3fffff, 0xc28); + pciAccessInit(); } - /* Use MOTLoad default for Writeback Priority and Buffer Depth */ -void pciAccessInit(int PciNum) +void pciAccessInit() { - unsigned int data; - - /* MOTLoad combines the two banks of SDRAM into - * one PCI access control because the top = 0x1ff - */ - data = inl(GT_SCS0_Low_Decode) & 0xfff; - data |= PCI_ACCCTLBASEL_VALUE; - data &= ~0x300000; - outl(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciNum * 0x80)); + unsigned int PciLocal, data; + + for (PciLocal=0; PciLocal < 2; PciLocal++) { + /* MOTLoad combines the two banks of SDRAM into + * one PCI access control because the top = 0x1ff + */ + data = inl(GT_SCS0_Low_Decode) & 0xfff; + data |= PCI_ACCCTLBASEL_VALUE; + data &= ~0x300000; + outl(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)); #if PCI_DEBUG - printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciNum,inl(PCI0_ACCESS_CNTL_BASE0_LOW+(PciNum * 0x80))); + printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,inl(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); #endif - + } } /* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers @@ -166,6 +169,8 @@ void CPU1_PciEnhanceSync(unsigned int syncVal) void pciToCpuSync(int pci_num) { unsigned char data; + unsigned char bus=0; - PCIx_read_config_byte(pci_num, 0,0,0,4, &data); + if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0; + pci_read_config_byte(bus,0,0,4, &data); } diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c b/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c index 67160781a3..c3b677d015 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c +++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c @@ -6,29 +6,42 @@ * (we assume, the firmware configured the PCI bus[es] for us) * * - * Kate Feng , modified it to support - * the mvme5500 board and provided glues to Till's vmeUniverse.c. - * + * Kate Feng , modified it to support the mvme5500 board. + * */ #define PCI_INVALID_VENDORDEVICEID 0xffffffff #define PCI_MULTI_FUNCTION 0x80 -/*#define PCI_DEBUG*/ #include #include +#include + +int BSP_pciDebug=0; + +int BSP_pciFindDevicePrint(unsigned short vendorid, unsigned short deviceid, + int instance, int *pbus, int *pdev, int *pfun ) +{ + int x; + + BSP_pciDebug = 1; + x=pci_find_device(vendorid, deviceid, instance, pbus, pdev, pfun ); + BSP_pciDebug = 0; + + return 0; +} -int BSP_PCIxFindDevice(unsigned short vendorid, unsigned short deviceid, - int instance, int pciNum, int *pbus, int *pdev, int *pfun ) +int pci_find_device( unsigned short vendorid, unsigned short deviceid, + int instance, int *pbus, int *pdev, int *pfun ) { unsigned int d; unsigned short s; unsigned char bus,dev,fun,hd; - for (bus=0; bus<2; bus++) { + for (bus=0; bus= BSP_MAX_PCI_BUS_ON_PCI0)? 1:0, + (bus>= BSP_MAX_PCI_BUS_ON_PCI0)? bus-BSP_MAX_PCI_BUS_ON_PCI0:bus, + dev, fun); + } + + (void)pci_read_config_word(bus,dev,fun,PCI_VENDOR_ID,&s); if (vendorid != s) continue; - (void)PCIx_read_config_word(pciNum, bus,dev,fun,PCI0_DEVICE_ID,&s); + (void)pci_read_config_word(bus,dev,fun,PCI_DEVICE_ID,&s); if (deviceid == s) { if (instance--) continue; *pbus=bus; *pdev=dev; *pfun=fun; @@ -57,10 +75,4 @@ int BSP_PCIxFindDevice(unsigned short vendorid, unsigned short deviceid, return -1; } -int pci_find_device( unsigned short vendorid, unsigned short deviceid, - int instance, int *pbus, int *pdev, int *pfun ) -{ - return(BSP_PCIxFindDevice(vendorid,deviceid,instance,0,pbus,pdev,pfun)); -} - /* eof */ -- cgit v1.2.3