From 4ef40152f3721981be60068bff0946d724bd73ed Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 18 Feb 1999 15:09:27 +0000 Subject: MPC860 support submitted by Jay Monkman . --- c/src/exec/score/cpu/powerpc/Makefile.in | 2 +- c/src/exec/score/cpu/powerpc/cpu.c | 175 +++++++++++++++++++++++++++++++ c/src/exec/score/cpu/powerpc/cpu.h | 6 +- c/src/exec/score/cpu/powerpc/ppc.h | 75 +++++++++++++ 4 files changed, 256 insertions(+), 2 deletions(-) diff --git a/c/src/exec/score/cpu/powerpc/Makefile.in b/c/src/exec/score/cpu/powerpc/Makefile.in index ca5f5e85f4..1324bd1e96 100644 --- a/c/src/exec/score/cpu/powerpc/Makefile.in +++ b/c/src/exec/score/cpu/powerpc/Makefile.in @@ -19,7 +19,7 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES=$(srcdir)/cpu.h $(srcdir)/ppc.h $(srcdir)/ppctypes.h # H_FILES that get installed externally -EXTERNAL_H_FILES = $(srcdir)/asm.h +EXTERNAL_H_FILES = $(srcdir)/asm.h $(srcdir)/mpc860.h # Assembly source names, if any, go here -- minus the .S # Normally cpu_asm and rtems are assembly files diff --git a/c/src/exec/score/cpu/powerpc/cpu.c b/c/src/exec/score/cpu/powerpc/cpu.c index da6ecf4d19..9bd4e13add 100644 --- a/c/src/exec/score/cpu/powerpc/cpu.c +++ b/c/src/exec/score/cpu/powerpc/cpu.c @@ -405,6 +405,15 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = { 0x48000002 /* ba PROC (_ISR_Handler) */ }; +#ifdef mpc860 +const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = { + 0x7c0803ac, /* mtlr %r0 */ + 0x81210028, /* lwz %r9, IP_9(%r1) */ + 0x38000000, /* li %r0, PPC_IRQ */ + 0x48000002 /* b PROC (_ISR_Handler) */ +}; +#endif /* mpc860 */ + unsigned32 ppc_exception_vector_addr( unsigned32 vector ); @@ -483,11 +492,31 @@ void _CPU_ISR_install_raw_handler( *old_handler = (proc_ptr) u32_handler; } else +/* There are two kinds of handlers for the MPC860. One is the 'standard' + * one like above. The other is for the cascaded interrupts from the SIU + * and CPM. Therefore we must check for the alternate one if the standard + * one is not present + */ +#ifdef mpc860 + if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) { + /* + * Set u32_handler = to target address + */ + u32_handler = slot->b_Handler & 0x03fffffc; + *old_handler = (proc_ptr) u32_handler; + } else +#endif /* mpc860 */ + *old_handler = 0; /* * Copy the template to the slot and then fix it. */ +#ifdef mpc860 + if (vector > PPC_STD_IRQ_LAST) + *slot = _CPU_Trap_slot_template_m860; + else +#endif /* mpc860 */ *slot = _CPU_Trap_slot_template; u32_handler = (unsigned32) new_handler; @@ -642,6 +671,152 @@ unsigned32 ppc_exception_vector_addr( case PPC_IRQ_SYS_MGT: Offset = 0x1400; break; + +#elif defined(mpc860) + case PPC_IRQ_IRQ0: + Offset = 0x1000; + break; + case PPC_IRQ_LVL0: + Offset = 0x1040; + break; + case PPC_IRQ_IRQ1: + Offset = 0x1080; + break; + case PPC_IRQ_LVL1: + Offset = 0x10c0; + break; + case PPC_IRQ_IRQ2: + Offset = 0x1100; + break; + case PPC_IRQ_LVL2: + Offset = 0x1140; + break; + case PPC_IRQ_IRQ3: + Offset = 0x1180; + break; + case PPC_IRQ_LVL3: + Offset = 0x11c0; + break; + case PPC_IRQ_IRQ4: + Offset = 0x1200; + break; + case PPC_IRQ_LVL4: + Offset = 0x1240; + break; + case PPC_IRQ_IRQ5: + Offset = 0x1280; + break; + case PPC_IRQ_LVL5: + Offset = 0x12c0; + break; + case PPC_IRQ_IRQ6: + Offset = 0x1300; + break; + case PPC_IRQ_LVL6: + Offset = 0x1340; + break; + case PPC_IRQ_IRQ7: + Offset = 0x1380; + break; + case PPC_IRQ_LVL7: + Offset = 0x13c0; + break; + case PPC_IRQ_CPM_RESERVED_0: + Offset = 0x1400; + break; + case PPC_IRQ_CPM_PC4: + Offset = 0x1410; + break; + case PPC_IRQ_CPM_PC5: + Offset = 0x1420; + break; + case PPC_IRQ_CPM_SMC2: + Offset = 0x1430; + break; + case PPC_IRQ_CPM_SMC1: + Offset = 0x1440; + break; + case PPC_IRQ_CPM_SPI: + Offset = 0x1450; + break; + case PPC_IRQ_CPM_PC6: + Offset = 0x1460; + break; + case PPC_IRQ_CPM_TIMER4: + Offset = 0x1470; + break; + case PPC_IRQ_CPM_RESERVED_8: + Offset = 0x1480; + break; + case PPC_IRQ_CPM_PC7: + Offset = 0x1490; + break; + case PPC_IRQ_CPM_PC8: + Offset = 0x14a0; + break; + case PPC_IRQ_CPM_PC9: + Offset = 0x14b0; + break; + case PPC_IRQ_CPM_TIMER3: + Offset = 0x14c0; + break; + case PPC_IRQ_CPM_RESERVED_D: + Offset = 0x14d0; + break; + case PPC_IRQ_CPM_PC10: + Offset = 0x14e0; + break; + case PPC_IRQ_CPM_PC11: + Offset = 0x14f0; + break; + case PPC_IRQ_CPM_I2C: + Offset = 0x1500; + break; + case PPC_IRQ_CPM_RISC_TIMER: + Offset = 0x1510; + break; + case PPC_IRQ_CPM_TIMER2: + Offset = 0x1520; + break; + case PPC_IRQ_CPM_RESERVED_13: + Offset = 0x1530; + break; + case PPC_IRQ_CPM_IDMA2: + Offset = 0x1540; + break; + case PPC_IRQ_CPM_IDMA1: + Offset = 0x1550; + break; + case PPC_IRQ_CPM_SDMA_ERROR: + Offset = 0x1560; + break; + case PPC_IRQ_CPM_PC12: + Offset = 0x1570; + break; + case PPC_IRQ_CPM_PC13: + Offset = 0x1580; + break; + case PPC_IRQ_CPM_TIMER1: + Offset = 0x1590; + break; + case PPC_IRQ_CPM_PC14: + Offset = 0x15a0; + break; + case PPC_IRQ_CPM_SCC4: + Offset = 0x15b0; + break; + case PPC_IRQ_CPM_SCC3: + Offset = 0x15c0; + break; + case PPC_IRQ_CPM_SCC2: + Offset = 0x15d0; + break; + case PPC_IRQ_CPM_SCC1: + Offset = 0x15e0; + break; + case PPC_IRQ_CPM_PC15: + Offset = 0x15f0; + break; #endif } diff --git a/c/src/exec/score/cpu/powerpc/cpu.h b/c/src/exec/score/cpu/powerpc/cpu.h index 1240f68451..42d1b59bcd 100644 --- a/c/src/exec/score/cpu/powerpc/cpu.h +++ b/c/src/exec/score/cpu/powerpc/cpu.h @@ -474,7 +474,7 @@ typedef struct { void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); boolean exceptions_in_RAM; /* TRUE if in RAM */ -#if defined(ppc403) +#if (defined(ppc403) || defined(mpc860)) unsigned32 serial_per_sec; /* Serial clocks per second */ boolean serial_external_clock; boolean serial_xon_xoff; @@ -484,6 +484,10 @@ typedef struct { unsigned32 timer_least_valid; /* Least valid number from timer */ boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ #endif + +#if (defined(mpc860)) + unsigned32 clock_speed; /* Speed of CPU in Hz */ +#endif } rtems_cpu_table; /* diff --git a/c/src/exec/score/cpu/powerpc/ppc.h b/c/src/exec/score/cpu/powerpc/ppc.h index a4b091c430..4c37f8c6c7 100644 --- a/c/src/exec/score/cpu/powerpc/ppc.h +++ b/c/src/exec/score/cpu/powerpc/ppc.h @@ -7,6 +7,8 @@ * * COPYRIGHT (c) 1995 by i-cubed ltd. * + * MPC860 support code was added by Jay Monkman + * * To anyone who acknowledges that this file is provided "AS IS" * without any express or implied warranty: * permission to use, copy, modify, and distribute this file @@ -177,6 +179,27 @@ extern "C" { #define PPC_I_CACHE 16384 #define PPC_D_CACHE 16384 +#elif defined(mpc860) +/* + * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 + */ +#define CPU_MODEL_NAME "PowerPC MPC860" + +#define PPC_ALIGNMENT 4 +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 4096 +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_INTERRUPT_MAX 64 +#define PPC_HAS_FPU 0 +#define PPC_HAS_DOUBLE 0 +#define PPC_USE_MULTIPLE 1 +#define PPC_USE_SPRG 1 + +#define PPC_MSR_0 0x00009000 +#define PPC_MSR_1 0x00001000 +#define PPC_MSR_2 0x00001000 +#define PPC_MSR_3 0x00000000 + #else #error "Unsupported CPU Model" @@ -413,6 +436,58 @@ extern "C" { #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ #define PPC_IRQ_LAST PPC604_IRQ_SYS_MGT +#elif defined(mpc860) +#define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 1) +#define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 2) +#define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 3) +#define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 4) +#define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 5) +#define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 6) +#define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 7) +#define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 8) +#define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 9) +#define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 10) +#define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 11) +#define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 12) +#define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 13) +#define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 14) +#define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 15) +#define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 16) +#define PPC_IRQ_CPM_RESERVED_0 (PPC_STD_IRQ_LAST + 17) +#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 18) +#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 19) +#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 20) +#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 21) +#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 22) +#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 23) +#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 24) +#define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 25) +#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 26) +#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 27) +#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 28) +#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 29) +#define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 30) +#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 31) +#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 32) +#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 33) +#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 34) +#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 35) +#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 36) +#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 37) +#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 38) +#define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 39) +#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 40) +#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 41) +#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 42) +#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 43) +#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 44) +#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 45) +#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 46) +#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 47) +#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 48) + +#define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 + #endif /* -- cgit v1.2.3