From 4a238002e71ec018723229f8669363a5ffb7302e Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 18 Nov 1999 21:22:58 +0000 Subject: Patch from "John M. Mills" with subsequent cleanup from Ralf Corsepius that adds initial Hitachi SH-2 support to RTEMS. Ralf's comments are: Changes: ------ 1. SH-Port: * Many files renamed. * CONSOLE_DEVNAME and MHZ defines removed from libcpu. * console.c moved to libbsp/sh/shared, build in libbsp/sh//console applying VPATH. * CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h * MHZ define replaced with HZ (extendent resolution) in custom/*.cfg * -DHZ=HZ used in bspstart.c, only * Makefile variable HZ used in bsp-dependent directories only. 2. SH1-Port * clock-driver rewritten to provide better resolution for odd CPU frequencies. This driver is only partially tested on hardware, ie. sightly experimental, but I don't expect severe problems with it. * Polling SCI-driver added. This driver is experimental and completly untested yet. Therefore it is not yet used for the console (/dev/console is still pointing to /dev/null, cf. gensh1/bsp.h). * minor changes to the timer driver * SH1 specific delay()/CPU_delay() now is implemented as a function 3. SH2-Port * Merged * IMO, the code is still in its infancy. Therefore I have interspersed comments (FIXME) it for items which I think John should look after. * sci and console drivers partially rewritten and extended (John, I hope you don't mind). * Copyright notices are not yet adapted --- c/configure.in | 2 + c/src/exec/score/cpu/sh/cpu.c | 2 +- c/src/exec/score/cpu/sh/cpu_asm.c | 13 +- c/src/exec/score/cpu/sh/cpu_isps.c | 252 ---------------- c/src/exec/score/cpu/sh/ispsh7032.c | 8 +- c/src/exec/score/cpu/sh/rtems/score/Makefile.in | 3 +- c/src/exec/score/cpu/sh/rtems/score/cpu.h | 9 +- c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h | 165 ---------- c/src/exec/score/cpu/sh/rtems/score/iosh7030.h | 223 -------------- c/src/exec/score/cpu/sh/rtems/score/sh.h | 9 + c/src/exec/score/cpu/sh/wrap/Makefile.in | 2 +- c/src/lib/libbsp/sh/gensh1/Makefile.in | 2 +- c/src/lib/libbsp/sh/gensh1/README | 8 +- c/src/lib/libbsp/sh/gensh1/include/bsp.h | 63 +--- c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in | 2 +- c/src/lib/libbsp/sh/gensh1/startup/bspstart.c | 4 +- c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in | 10 +- c/src/lib/libbsp/sh/gensh2/Makefile.in | 27 ++ c/src/lib/libbsp/sh/gensh2/README | 51 ++++ c/src/lib/libbsp/sh/gensh2/bsp_specs | 22 ++ c/src/lib/libbsp/sh/gensh2/console/Makefile.in | 71 +++++ c/src/lib/libbsp/sh/gensh2/include/Makefile.in | 43 +++ c/src/lib/libbsp/sh/gensh2/include/bsp.h | 139 +++++++++ c/src/lib/libbsp/sh/gensh2/include/coverhd.h | 130 ++++++++ c/src/lib/libbsp/sh/gensh2/scitab/Makefile.in | 74 +++++ c/src/lib/libbsp/sh/gensh2/start/Makefile.in | 70 +++++ c/src/lib/libbsp/sh/gensh2/start/start.S | 198 ++++++++++++ c/src/lib/libbsp/sh/gensh2/start/start.ram | 199 ++++++++++++ c/src/lib/libbsp/sh/gensh2/start/start.rom | 94 ++++++ c/src/lib/libbsp/sh/gensh2/startup/Makefile.in | 77 +++++ c/src/lib/libbsp/sh/gensh2/startup/bspclean.c | 43 +++ c/src/lib/libbsp/sh/gensh2/startup/bspstart.c | 138 +++++++++ c/src/lib/libbsp/sh/gensh2/startup/hw_init.c | 140 +++++++++ c/src/lib/libbsp/sh/gensh2/startup/linkcmds | 216 +++++++++++++ c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram | 216 +++++++++++++ c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom | 217 +++++++++++++ c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.in | 69 +++++ c/src/lib/libcpu/sh/sh7032/Makefile.in | 2 +- c/src/lib/libcpu/sh/sh7032/clock/Makefile.in | 2 +- c/src/lib/libcpu/sh/sh7032/clock/ckinit.c | 94 +++++- c/src/lib/libcpu/sh/sh7032/console/Makefile.in | 71 ----- c/src/lib/libcpu/sh/sh7032/console/console.c | 153 ---------- c/src/lib/libcpu/sh/sh7032/include/Makefile.in | 4 +- c/src/lib/libcpu/sh/sh7032/include/ioqueue.h | 77 ----- c/src/lib/libcpu/sh/sh7032/include/sci.h | 6 - c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h | 2 +- c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h | 2 +- c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c | 13 +- c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c | 8 +- c/src/lib/libcpu/sh/sh7032/timer/Makefile.in | 2 +- c/src/lib/libcpu/sh/sh7032/timer/timer.c | 40 ++- c/src/lib/libcpu/sh/sh7045/Makefile.in | 25 ++ c/src/lib/libcpu/sh/sh7045/clock/Makefile.in | 71 +++++ c/src/lib/libcpu/sh/sh7045/clock/ckinit.c | 308 +++++++++++++++++++ c/src/lib/libcpu/sh/sh7045/include/Makefile.in | 46 +++ c/src/lib/libcpu/sh/sh7045/include/io_types.h | 87 ++++++ c/src/lib/libcpu/sh/sh7045/include/null.h | 72 +++++ c/src/lib/libcpu/sh/sh7045/include/sci.h | 85 ++++++ c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h | 118 ++++++++ c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h | 91 ++++++ c/src/lib/libcpu/sh/sh7045/null/Makefile.in | 70 +++++ c/src/lib/libcpu/sh/sh7045/null/close.c | 38 +++ c/src/lib/libcpu/sh/sh7045/null/cntrl.c | 38 +++ c/src/lib/libcpu/sh/sh7045/null/init.c | 53 ++++ c/src/lib/libcpu/sh/sh7045/null/open.c | 38 +++ c/src/lib/libcpu/sh/sh7045/null/read.c | 38 +++ c/src/lib/libcpu/sh/sh7045/null/write.c | 44 +++ c/src/lib/libcpu/sh/sh7045/sci/Makefile.in | 71 +++++ c/src/lib/libcpu/sh/sh7045/sci/sci.c | 384 ++++++++++++++++++++++++ c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c | 13 +- c/src/lib/libcpu/sh/sh7045/timer/Makefile.in | 71 +++++ c/src/lib/libcpu/sh/sh7045/timer/timer.c | 208 +++++++++++++ cpukit/score/cpu/sh/cpu.c | 2 +- cpukit/score/cpu/sh/rtems/score/cpu.h | 9 +- cpukit/score/cpu/sh/rtems/score/sh.h | 9 + make/custom/gensh1.cfg | 16 +- make/custom/gensh2.cfg | 86 ++++++ 77 files changed, 4509 insertions(+), 1069 deletions(-) delete mode 100644 c/src/exec/score/cpu/sh/cpu_isps.c delete mode 100644 c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h delete mode 100644 c/src/exec/score/cpu/sh/rtems/score/iosh7030.h create mode 100644 c/src/lib/libbsp/sh/gensh2/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh2/README create mode 100644 c/src/lib/libbsp/sh/gensh2/bsp_specs create mode 100644 c/src/lib/libbsp/sh/gensh2/console/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh2/include/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh2/include/bsp.h create mode 100644 c/src/lib/libbsp/sh/gensh2/include/coverhd.h create mode 100644 c/src/lib/libbsp/sh/gensh2/scitab/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh2/start/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh2/start/start.S create mode 100644 c/src/lib/libbsp/sh/gensh2/start/start.ram create mode 100644 c/src/lib/libbsp/sh/gensh2/start/start.rom create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/bspclean.c create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/bspstart.c create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/hw_init.c create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/linkcmds create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram create mode 100644 c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom create mode 100644 c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.in delete mode 100644 c/src/lib/libcpu/sh/sh7032/console/Makefile.in delete mode 100644 c/src/lib/libcpu/sh/sh7032/console/console.c delete mode 100644 c/src/lib/libcpu/sh/sh7032/include/ioqueue.h create mode 100644 c/src/lib/libcpu/sh/sh7045/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7045/clock/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7045/clock/ckinit.c create mode 100644 c/src/lib/libcpu/sh/sh7045/include/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7045/include/io_types.h create mode 100644 c/src/lib/libcpu/sh/sh7045/include/null.h create mode 100644 c/src/lib/libcpu/sh/sh7045/include/sci.h create mode 100644 c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h create mode 100644 c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h create mode 100644 c/src/lib/libcpu/sh/sh7045/null/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7045/null/close.c create mode 100644 c/src/lib/libcpu/sh/sh7045/null/cntrl.c create mode 100644 c/src/lib/libcpu/sh/sh7045/null/init.c create mode 100644 c/src/lib/libcpu/sh/sh7045/null/open.c create mode 100644 c/src/lib/libcpu/sh/sh7045/null/read.c create mode 100644 c/src/lib/libcpu/sh/sh7045/null/write.c create mode 100644 c/src/lib/libcpu/sh/sh7045/sci/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7045/sci/sci.c create mode 100644 c/src/lib/libcpu/sh/sh7045/timer/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7045/timer/timer.c create mode 100644 make/custom/gensh2.cfg diff --git a/c/configure.in b/c/configure.in index 2df416b8b4..5bae4f4081 100644 --- a/c/configure.in +++ b/c/configure.in @@ -100,6 +100,8 @@ AC_SUBST(RTEMS_BSP_LIST) AC_CONFIG_SUBDIRS(make) +AC_CONFIG_SUBDIRS(make) + AC_OUTPUT( Makefile ) diff --git a/c/src/exec/score/cpu/sh/cpu.c b/c/src/exec/score/cpu/sh/cpu.c index cc07552cf0..06f7b9c3d7 100644 --- a/c/src/exec/score/cpu/sh/cpu.c +++ b/c/src/exec/score/cpu/sh/cpu.c @@ -30,7 +30,7 @@ #include -/* referenced in start.s */ +/* referenced in start.S */ extern proc_ptr vectab[] ; proc_ptr vectab[256] ; diff --git a/c/src/exec/score/cpu/sh/cpu_asm.c b/c/src/exec/score/cpu/sh/cpu_asm.c index 42764f6eb1..192c2f43d2 100644 --- a/c/src/exec/score/cpu/sh/cpu_asm.c +++ b/c/src/exec/score/cpu/sh/cpu_asm.c @@ -41,10 +41,17 @@ #include #include #include -#include -#include #include -#include + +#if defined(sh7032) +#include +#include +#elif defined (sh7045) +#include +#include +#endif + +#include /* from cpu_isps.c */ extern proc_ptr _Hardware_isr_Table[]; diff --git a/c/src/exec/score/cpu/sh/cpu_isps.c b/c/src/exec/score/cpu/sh/cpu_isps.c deleted file mode 100644 index 3ef3c32465..0000000000 --- a/c/src/exec/score/cpu/sh/cpu_isps.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This file contains the isp frames for the user interrupts. - * From these procedures __ISR_Handler is called with the vector number - * as argument. - * - * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in - * some releases of gcc doesn't properly handle #pragma interrupt, if a - * file contains both isrs and normal functions. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include -#include -#include - -/* - * This is a exception vector table - * - * It has the same structure like the actual vector table (vectab) - */ -proc_ptr _Hardware_isr_Table[256]={ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -_nmi_isp, _usb_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -/* trapa 0 -31 */ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -/* irq 64 ... */ -_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, -_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, -_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, -_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, -_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, -_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, -_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, -_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, -_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, -_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, -_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, -_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, -_wdt_isp, -/* 113 */ _dref_isp -}; - -#define Str(a)#a - -/* - * Some versions of gcc and all version of egcs at least until egcs-1.1b - * are not able to handle #pragma interrupt correctly if more than 1 isr is - * contained in a file and when optimizing. - * We try to work around this problem by using the macro below. - */ -#define isp( name, number, func)\ -asm (".global _"Str(name)"\n\t" \ - "_"Str(name)": \n\t" \ - " mov.l r0,@-r15 \n\t" \ - " mov.l r1,@-r15 \n\t" \ - " mov.l r2,@-r15 \n\t" \ - " mov.l r3,@-r15 \n\t" \ - " mov.l r4,@-r15 \n\t" \ - " mov.l r5,@-r15 \n\t" \ - " mov.l r6,@-r15 \n\t" \ - " mov.l r7,@-r15 \n\t" \ - " mov.l r14,@-r15 \n\t" \ - " sts.l pr,@-r15 \n\t" \ - " sts.l mach,@-r15 \n\t" \ - " sts.l macl,@-r15 \n\t" \ - " mov r15,r14 \n\t" \ - " mov.l "Str(name)"_k, r1\n\t" \ - " jsr @r1 \n\t" \ - " mov #"Str(number)", r4\n\t" \ - " mov r14,r15 \n\t" \ - " lds.l @r15+,macl \n\t" \ - " lds.l @r15+,mach \n\t" \ - " lds.l @r15+,pr \n\t" \ - " mov.l @r15+,r14 \n\t" \ - " mov.l @r15+,r7 \n\t" \ - " mov.l @r15+,r6 \n\t" \ - " mov.l @r15+,r5 \n\t" \ - " mov.l @r15+,r4 \n\t" \ - " mov.l @r15+,r3 \n\t" \ - " mov.l @r15+,r2 \n\t" \ - " mov.l @r15+,r1 \n\t" \ - " mov.l @r15+,r0 \n\t" \ - " rte \n\t" \ - " nop \n\t" \ - " .align 2 \n\t" \ - #name"_k: \n\t" \ - ".long "Str(func)); - -/************************************************ - * Dummy interrupt service procedure for - * interrupts being not allowed --> Trap 34 - ************************************************/ -asm(" .section .text -.global __dummy_isp -__dummy_isp: - mov.l r14,@-r15 - mov r15, r14 - trapa #34 - mov.l @r15+,r14 - rte - nop"); - -/***************************** - * Non maskable interrupt - *****************************/ -isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); - -/***************************** - * User break controller - *****************************/ -isp( _usb_isp, USB_ISP_V, ___ISR_Handler); - -/***************************** - * External interrupts 0-7 - *****************************/ -isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); -isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); -isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); -isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); -isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); -isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); -isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); -isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); - -/***************************** - * DMA - controller - *****************************/ -isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); -isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); -isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); -isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); - - -/***************************** - * Interrupt timer unit - *****************************/ - -/***************************** - * Timer 0 - *****************************/ -isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler); -isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler); -isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 1 - *****************************/ -isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler); -isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler); -isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 2 - *****************************/ -isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler); -isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler); -isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 3 - *****************************/ -isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler); -isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler); -isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 4 - *****************************/ -isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler); -isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler); -isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler); - - -/***************************** - * Serial interfaces - *****************************/ - -/***************************** - * Serial interface 0 - *****************************/ -isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); -isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); -isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); -isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); - -/***************************** - * Serial interface 1 - *****************************/ -isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); -isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); -isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); -isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); - - -/***************************** - * Parity control unit of - * the bus state controller - *****************************/ -isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); - - -/****************************** - * Analog digital converter - * ADC - ******************************/ -isp( _adu_isp, ADU_ISP_V, ___ISR_Handler); - - -/****************************** - * Watchdog timer - ******************************/ -isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); - - -/****************************** - * DRAM refresh control unit - * of bus state controller - ******************************/ -isp( _dref_isp, DREF_ISP_V, ___ISR_Handler); diff --git a/c/src/exec/score/cpu/sh/ispsh7032.c b/c/src/exec/score/cpu/sh/ispsh7032.c index 3ef3c32465..9fcc9badbf 100644 --- a/c/src/exec/score/cpu/sh/ispsh7032.c +++ b/c/src/exec/score/cpu/sh/ispsh7032.c @@ -30,10 +30,14 @@ #include #include -#include +#include + +#if !defined(sh7032) +#error Wrong CPU MODEL +#endif /* - * This is a exception vector table + * This is an exception vector table * * It has the same structure like the actual vector table (vectab) */ diff --git a/c/src/exec/score/cpu/sh/rtems/score/Makefile.in b/c/src/exec/score/cpu/sh/rtems/score/Makefile.in index bd536daf80..72b3471072 100644 --- a/c/src/exec/score/cpu/sh/rtems/score/Makefile.in +++ b/c/src/exec/score/cpu/sh/rtems/score/Makefile.in @@ -18,7 +18,8 @@ C_PIECES = C_FILES = $(C_PIECES:%=%.c) C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) -H_PIECES = cpu.h shtypes.h sh.h sh_io.h cpu_isps.h iosh7030.h +H_PIECES = cpu.h shtypes.h sh.h sh_io.h isp$(RTEMS_CPU_MODEL).h \ + io$(RTEMS_CPU_MODEL).h H_FILES = $(H_PIECES:%=$(srcdir)/%) # Assembly source names, if any, go here -- minus the .S diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu.h b/c/src/exec/score/cpu/sh/rtems/score/cpu.h index 8a18848f09..dedd11c055 100644 --- a/c/src/exec/score/cpu/sh/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/sh/rtems/score/cpu.h @@ -377,6 +377,7 @@ typedef struct { void * (*stack_allocate_hook)( unsigned32 ); void (*stack_free_hook)( void* ); /* end of fields required on all CPUs */ + unsigned32 clicks_per_second ; /* cpu frequency in Hz */ } rtems_cpu_table; /* @@ -388,8 +389,9 @@ typedef struct { * Macros to access SH specific additions to the CPU Table */ -/* There are no CPU specific additions to the CPU Table for this port. */ - +#define rtems_cpu_configuration_get_clicks_per_second() \ + (_CPU_Table.clicks_per_second) + /* * This variable is optional. It is used on CPUs on which it is difficult * to generate an "uninitialized" FP context. It is filled in by @@ -434,6 +436,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ /* XXX: if needed, put more variables here */ +SCORE_EXTERN void CPU_delay( unsigned32 microseconds ); /* * The size of the floating point context area. On some CPUs this @@ -637,7 +640,7 @@ SCORE_EXTERN void _CPU_Context_Initialize( * * Other models include (1) not doing anything, and (2) putting * a "null FP status word" in the correct place in the FP context. - * SH has no FPU !!!!!!!!!!!! + * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. */ #define _CPU_Context_Initialize_fp( _destination ) \ diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h b/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h deleted file mode 100644 index 3f9baf1ad2..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_ISPS_H -#define __CPU_ISPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern void __ISR_Handler( unsigned32 vector ); - - -/* - * interrupt vector table offsets - */ -#define NMI_ISP_V 11 -#define USB_ISP_V 12 -#define IRQ0_ISP_V 64 -#define IRQ1_ISP_V 65 -#define IRQ2_ISP_V 66 -#define IRQ3_ISP_V 67 -#define IRQ4_ISP_V 68 -#define IRQ5_ISP_V 69 -#define IRQ6_ISP_V 70 -#define IRQ7_ISP_V 71 -#define DMA0_ISP_V 72 -#define DMA1_ISP_V 74 -#define DMA2_ISP_V 76 -#define DMA3_ISP_V 78 - -#define IMIA0_ISP_V 80 -#define IMIB0_ISP_V 81 -#define OVI0_ISP_V 82 - -#define IMIA1_ISP_V 84 -#define IMIB1_ISP_V 85 -#define OVI1_ISP_V 86 - -#define IMIA2_ISP_V 88 -#define IMIB2_ISP_V 89 -#define OVI2_ISP_V 90 - -#define IMIA3_ISP_V 92 -#define IMIB3_ISP_V 93 -#define OVI3_ISP_V 94 - -#define IMIA4_ISP_V 96 -#define IMIB4_ISP_V 97 -#define OVI4_ISP_V 98 - -#define ERI0_ISP_V 100 -#define RXI0_ISP_V 101 -#define TXI0_ISP_V 102 -#define TEI0_ISP_V 103 - -#define ERI1_ISP_V 104 -#define RXI1_ISP_V 105 -#define TXI1_ISP_V 106 -#define TEI1_ISP_V 107 - -#define PRT_ISP_V 108 -#define ADU_ISP_V 109 -#define WDT_ISP_V 112 -#define DREF_ISP_V 113 - - -/* dummy ISP */ -extern void _dummy_isp( void ); - -/* Non Maskable Interrupt */ -extern void _nmi_isp( void ); - -/* User Break Controller */ -extern void _usb_isp( void ); - -/* External interrupts 0-7 */ -extern void _irq0_isp( void ); -extern void _irq1_isp( void ); -extern void _irq2_isp( void ); -extern void _irq3_isp( void ); -extern void _irq4_isp( void ); -extern void _irq5_isp( void ); -extern void _irq6_isp( void ); -extern void _irq7_isp( void ); - -/* DMA - Controller */ -extern void _dma0_isp( void ); -extern void _dma1_isp( void ); -extern void _dma2_isp( void ); -extern void _dma3_isp( void ); - -/* Interrupt Timer Unit */ -/* Timer 0 */ -extern void _imia0_isp( void ); -extern void _imib0_isp( void ); -extern void _ovi0_isp( void ); -/* Timer 1 */ -extern void _imia1_isp( void ); -extern void _imib1_isp( void ); -extern void _ovi1_isp( void ); -/* Timer 2 */ -extern void _imia2_isp( void ); -extern void _imib2_isp( void ); -extern void _ovi2_isp( void ); -/* Timer 3 */ -extern void _imia3_isp( void ); -extern void _imib3_isp( void ); -extern void _ovi3_isp( void ); -/* Timer 4 */ -extern void _imia4_isp( void ); -extern void _imib4_isp( void ); -extern void _ovi4_isp( void ); - -/* seriell interfaces */ -extern void _eri0_isp( void ); -extern void _rxi0_isp( void ); -extern void _txi0_isp( void ); -extern void _tei0_isp( void ); -extern void _eri1_isp( void ); -extern void _rxi1_isp( void ); -extern void _txi1_isp( void ); -extern void _tei1_isp( void ); - -/* Parity Control Unit of the Bus State Controllers */ -extern void _prt_isp( void ); - -/* ADC */ -extern void _adu_isp( void ); - -/* Watchdog Timer */ -extern void _wdt_isp( void ); - -/* DRAM refresh control unit of bus state controller */ -extern void _dref_isp( void ); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h deleted file mode 100644 index 48463aed47..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which - * contained no copyright notice. - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __IOSH7030_H -#define __IOSH7030_H - -/* - * After each line is explained whether the access is char short or long. - * The functions read/writeb, w, l, 8, 16, 32 can be found - * in exec/score/cpu/sh/sh_io.h - * - * 8 bit == char ( readb, writeb, read8, write8) - * 16 bit == short ( readw, writew, read16, write16 ) - * 32 bit == long ( readl, writel, read32, write32 ) - */ - -#define SCI0_SMR 0x05fffec0 /* char */ -#define SCI0_BRR 0x05fffec1 /* char */ -#define SCI0_SCR 0x05fffec2 /* char */ -#define SCI0_TDR 0x05fffec3 /* char */ -#define SCI0_SSR 0x05fffec4 /* char */ -#define SCI0_RDR 0x05fffec5 /* char */ - -#define SCI1_SMR 0x05fffec8 /* char */ -#define SCI1_BRR 0x05fffec9 /* char */ -#define SCI1_SCR 0x05fffeca /* char */ -#define SCI1_TDR 0x05fffecb /* char */ -#define SCI1_SSR 0x05fffecc /* char */ -#define SCI1_RDR 0x05fffecd /* char */ - - -#define ADDRAH 0x05fffee0 /* char */ -#define ADDRAL 0x05fffee1 /* char */ -#define ADDRBH 0x05fffee2 /* char */ -#define ADDRBL 0x05fffee3 /* char */ -#define ADDRCH 0x05fffee4 /* char */ -#define ADDRCL 0x05fffee5 /* char */ -#define ADDRDH 0x05fffee6 /* char */ -#define ADDRDL 0x05fffee7 /* char */ -#define AD_DRA 0x05fffee0 /* short */ -#define AD_DRB 0x05fffee2 /* short */ -#define AD_DRC 0x05fffee4 /* short */ -#define AD_DRD 0x05fffee6 /* short */ -#define ADCSR 0x05fffee8 /* char */ -#define ADCR 0x05fffee9 /* char */ - -/*ITU SHARED*/ -#define ITU_TSTR 0x05ffff00 /* char */ -#define ITU_TSNC 0x05ffff01 /* char */ -#define ITU_TMDR 0x05ffff02 /* char */ -#define ITU_TFCR 0x05ffff03 /* char */ - -/*ITU CHANNEL 0*/ -#define ITU_TCR0 0x05ffff04 /* char */ -#define ITU_TIOR0 0x05ffff05 /* char */ -#define ITU_TIER0 0x05ffff06 /* char */ -#define ITU_TSR0 0x05ffff07 /* char */ -#define ITU_TCNT0 0x05ffff08 /* short */ -#define ITU_GRA0 0x05ffff0a /* short */ -#define ITU_GRB0 0x05ffff0c /* short */ - - /*ITU CHANNEL 1*/ -#define ITU_TCR1 0x05ffff0E /* char */ -#define ITU_TIOR1 0x05ffff0F /* char */ -#define ITU_TIER1 0x05ffff10 /* char */ -#define ITU_TSR1 0x05ffff11 /* char */ -#define ITU_TCNT1 0x05ffff12 /* short */ -#define ITU_GRA1 0x05ffff14 /* short */ -#define ITU_GRB1 0x05ffff16 /* short */ - - - /*ITU CHANNEL 2*/ -#define ITU_TCR2 0x05ffff18 /* char */ -#define ITU_TIOR2 0x05ffff19 /* char */ -#define ITU_TIER2 0x05ffff1A /* char */ -#define ITU_TSR2 0x05ffff1B /* char */ -#define ITU_TCNT2 0x05ffff1C /* short */ -#define ITU_GRA2 0x05ffff1E /* short */ -#define ITU_GRB2 0x05ffff20 /* short */ - - /*ITU CHANNEL 3*/ -#define ITU_TCR3 0x05ffff22 /* char */ -#define ITU_TIOR3 0x05ffff23 /* char */ -#define ITU_TIER3 0x05ffff24 /* char */ -#define ITU_TSR3 0x05ffff25 /* char */ -#define ITU_TCNT3 0x05ffff26 /* short */ -#define ITU_GRA3 0x05ffff28 /* short */ -#define ITU_GRB3 0x05ffff2A /* short */ -#define ITU_BRA3 0x05ffff2C /* short */ -#define ITU_BRB3 0x05ffff2E /* short */ - - /*ITU CHANNELS 0-4 SHARED*/ -#define ITU_TOCR 0x05ffff31 /* char */ - - /*ITU CHANNEL 4*/ -#define ITU_TCR4 0x05ffff32 /* char */ -#define ITU_TIOR4 0x05ffff33 /* char */ -#define ITU_TIER4 0x05ffff34 /* char */ -#define ITU_TSR4 0x05ffff35 /* char */ -#define ITU_TCNT4 0x05ffff36 /* short */ -#define ITU_GRA4 0x05ffff38 /* short */ -#define ITU_GRB4 0x05ffff3A /* short */ -#define ITU_BRA4 0x05ffff3C /* short */ -#define ITU_BRB4 0x05ffff3E /* short */ - - /*DMAC CHANNELS 0-3 SHARED*/ -#define DMAOR 0x05ffff48 /* short */ - - /*DMAC CHANNEL 0*/ -#define DMA_SAR0 0x05ffff40 /* long */ -#define DMA_DAR0 0x05ffff44 /* long */ -#define DMA_TCR0 0x05ffff4a /* short */ -#define DMA_CHCR0 0x05ffff4e /* short */ - - /*DMAC CHANNEL 1*/ -#define DMA_SAR1 0x05ffff50 /* long */ -#define DMA_DAR1 0x05ffff54 /* long */ -#define DMA_TCR1 0x05fffF5a /* short */ -#define DMA_CHCR1 0x05ffff5e /* short */ - - /*DMAC CHANNEL 3*/ -#define DMA_SAR3 0x05ffff60 /* long */ -#define DMA_DAR3 0x05ffff64 /* long */ -#define DMA_TCR3 0x05fffF6a /* short */ -#define DMA_CHCR3 0x05ffff6e /* short */ - -/*DMAC CHANNEL 4*/ -#define DMA_SAR4 0x05ffff70 /* long */ -#define DMA_DAR4 0x05ffff74 /* long */ -#define DMA_TCR4 0x05fffF7a /* short */ -#define DMA_CHCR4 0x05ffff7e /* short */ - -/*INTC*/ -#define INTC_IPRA 0x05ffff84 /* short */ -#define INTC_IPRB 0x05ffff86 /* short */ -#define INTC_IPRC 0x05ffff88 /* short */ -#define INTC_IPRD 0x05ffff8A /* short */ -#define INTC_IPRE 0x05ffff8C /* short */ -#define INTC_ICR 0x05ffff8E /* short */ - -/*UBC*/ -#define UBC_BARH 0x05ffff90 /* short */ -#define UBC_BARL 0x05ffff92 /* short */ -#define UBC_BAMRH 0x05ffff94 /* short */ -#define UBC_BAMRL 0x05ffff96 /* short */ -#define UBC_BBR 0x05ffff98 /* short */ - -/*BSC*/ -#define BSC_BCR 0x05ffffA0 /* short */ -#define BSC_WCR1 0x05ffffA2 /* short */ -#define BSC_WCR2 0x05ffffA4 /* short */ -#define BSC_WCR3 0x05ffffA6 /* short */ -#define BSC_DCR 0x05ffffA8 /* short */ -#define BSC_PCR 0x05ffffAA /* short */ -#define BSC_RCR 0x05ffffAC /* short */ -#define BSC_RTCSR 0x05ffffAE /* short */ -#define BSC_RTCNT 0x05ffffB0 /* short */ -#define BSC_RTCOR 0x05ffffB2 /* short */ - -/*WDT*/ -#define WDT_TCSR 0x05ffffB8 /* char */ -#define WDT_TCNT 0x05ffffB9 /* char */ -#define WDT_RSTCSR 0x05ffffBB /* char */ - -/*POWER DOWN STATE*/ -#define PDT_SBYCR 0x05ffffBC /* char */ - -/*PORT A*/ -#define PADR 0x05ffffC0 /* short */ - -/*PORT B*/ -#define PBDR 0x05ffffC2 /* short */ - - /*PORT C*/ -#define PCDR 0x05ffffD0 /* short */ - -/*PFC*/ -#define PFC_PAIOR 0x05ffffC4 /* short */ -#define PFC_PBIOR 0x05ffffC6 /* short */ -#define PFC_PACR1 0x05ffffC8 /* short */ -#define PFC_PACR2 0x05ffffCA /* short */ -#define PFC_PBCR1 0x05ffffCC /* short */ -#define PFC_PBCR2 0x05ffffCE /* short */ -#define PFC_CASCR 0x05ffffEE /* short */ - -/*TPC*/ -#define TPC_TPMR 0x05ffffF0 /* short */ -#define TPC_TPCR 0x05ffffF1 /* short */ -#define TPC_NDERH 0x05ffffF2 /* short */ -#define TPC_NDERL 0x05ffffF3 /* short */ -#define TPC_NDRB 0x05ffffF4 /* char */ -#define TPC_NDRA 0x05ffff5F /* char */ -#define TPC_NDRB1 0x05ffffF6 /* char */ -#define TPC_NDRA1 0x05ffffF7 /* char */ - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh.h b/c/src/exec/score/cpu/sh/rtems/score/sh.h index 96e10bfb1b..45228c5fe0 100644 --- a/c/src/exec/score/cpu/sh/rtems/score/sh.h +++ b/c/src/exec/score/cpu/sh/rtems/score/sh.h @@ -42,7 +42,16 @@ extern "C" { #if defined(sh7032) #define CPU_MODEL_NAME "SH 7032" +#define SH_HAS_FPU 0 + +/* + * If the following macro is set to 0 there will be no software irq stack + */ +#define SH_HAS_SEPARATE_STACKS 1 + +#elif defined (sh7045) +#define CPU_MODEL_NAME "SH 7045" #define SH_HAS_FPU 0 /* diff --git a/c/src/exec/score/cpu/sh/wrap/Makefile.in b/c/src/exec/score/cpu/sh/wrap/Makefile.in index 7884023a4b..12fe6d5d06 100644 --- a/c/src/exec/score/cpu/sh/wrap/Makefile.in +++ b/c/src/exec/score/cpu/sh/wrap/Makefile.in @@ -23,7 +23,7 @@ VPATH = @srcdir@/.. RELS = ../$(ARCH)/rtems-cpu.rel # C source names, if any, go here -- minus the .c -C_PIECES = cpu cpu_asm cpu_isps +C_PIECES = cpu cpu_asm isp$(RTEMS_CPU_MODEL) C_FILES = $(C_PIECES:%=%.c) C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) diff --git a/c/src/lib/libbsp/sh/gensh1/Makefile.in b/c/src/lib/libbsp/sh/gensh1/Makefile.in index 69aaa0d548..c495ae5306 100644 --- a/c/src/lib/libbsp/sh/gensh1/Makefile.in +++ b/c/src/lib/libbsp/sh/gensh1/Makefile.in @@ -20,7 +20,7 @@ INSTALL_CHANGE = @INSTALL_CHANGE@ # wrapup is the one that actually builds and installs the library # from the individual .rel files built in other directories -SUB_DIRS = include start startup scitab wrapup +SUB_DIRS = include start startup scitab console wrapup Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status cd $(top_builddir) \ diff --git a/c/src/lib/libbsp/sh/gensh1/README b/c/src/lib/libbsp/sh/gensh1/README index c75ad9927e..ce465b16a2 100644 --- a/c/src/lib/libbsp/sh/gensh1/README +++ b/c/src/lib/libbsp/sh/gensh1/README @@ -45,6 +45,10 @@ STOP BITS: n/a NOTES ===== -(1) Only stub console driver available at the moment. - Driver for the on-chip serial devices (sci) will be available soon. +(1) The stub console driver (null) is enabled by default. +(2) The driver for the on-chip serial devices (sci) is still in its infancy + and not fully tested. It may even be non-functional and therefore is + disabled by default. Please let us know any problems you encounter with + it. + To activate it edit libbsp/sh/gensh1/include/bsp.h diff --git a/c/src/lib/libbsp/sh/gensh1/include/bsp.h b/c/src/lib/libbsp/sh/gensh1/include/bsp.h index 8ac21df14e..f02abe156d 100644 --- a/c/src/lib/libbsp/sh/gensh1/include/bsp.h +++ b/c/src/lib/libbsp/sh/gensh1/include/bsp.h @@ -30,14 +30,22 @@ extern "C" { #endif -#define CPU_CONSOLE_DEVNAME "/dev/null" - - #include #include -#include #include +/* EDIT: To activate the sci driver, change the define below */ +#if 1 +#include +#define BSP_CONSOLE_DEVNAME "/dev/null" +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY +#else +#include +#define BSP_CONSOLE_DEVNAME "/dev/sci0" +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY +#endif + + /* * Define the time limits for RTEMS Test Suite test durations. * Long test and short test duration limits are provided. These @@ -68,39 +76,14 @@ extern "C" { #define Lower_tm27_intr() /* Constants */ -#ifndef MHZ -#error Missing MHZ -#endif /* * Simple spin delay in microsecond units for device drivers. * This is very dependent on the clock speed of the target. - * - * Since we don't have a real time clock, this is a very rough - * approximation, assuming that each cycle of the delay loop takes - * approx. 4 machine cycles. - * - * e.g.: MHZ = 20 => 5e-8 secs per instruction - * => 4 * 5e-8 secs per delay loop */ -#define delay( microseconds ) \ -{ register unsigned int _delay = (microseconds) * (MHZ / 4 ); \ - asm volatile ( \ -"0: add #-1,%0\n \ - nop\n \ - cmp/pl %0\n \ - bt 0b\ - nop" \ - :: "r" (_delay) ); \ -} - -/* - * For backward compatibility only. - * Do not rely on them being present in future - */ -#define CPU_delay( microseconds ) delay( microseconds ) -#define sh_delay( microseconds ) delay( microseconds ) +#define delay( microseconds ) CPU_delay(microseconds) +#define sh_delay( microseconds ) CPU_delay(microseconds) /* * Defined in the linker script 'linkcmds' @@ -128,13 +111,9 @@ extern void bsp_cleanup( void ); /* * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console */ -#if defined(CONSOLE_DRIVER_TABLE_ENTRY) -#warning Overwriting CONSOLE_DRIVER_TABLE_ENTRY #undef CONSOLE_DRIVER_TABLE_ENTRY -#endif - #define CONSOLE_DRIVER_TABLE_ENTRY \ - DEVNULL_DRIVER_TABLE_ENTRY, \ + BSP_CONSOLE_DRIVER_TABLE_ENTRY, \ { console_initialize, console_open, console_close, \ console_read, console_write, console_control } @@ -142,18 +121,6 @@ extern void bsp_cleanup( void ); * NOTE: Use the standard Clock driver entry */ -/* - * FIXME: Should this go to libcpu/sh/sh7032 ? - */ -#if 0 -/* functions */ -sh_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); -#endif - #ifdef __cplusplus } #endif diff --git a/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in b/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in index 1593251658..9919c0ec7e 100644 --- a/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in +++ b/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in @@ -64,7 +64,7 @@ $(PGM): $(SRCS) ${OBJS} all: ${ARCH} $(SRCS) $(PGM) scitab.c: $(SHGEN) - $(SHGEN) -M $(MHZ) sci > $@ + $(SHGEN) -H $(HZ) sci > $@ # the .rel file built here will be put into libbsp.a by ../wrapup/Makefile install: all diff --git a/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c b/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c index 08aaf8d905..7f0d7f8436 100644 --- a/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c +++ b/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c @@ -126,9 +126,9 @@ void bsp_start(void) Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ Cpu_table.postdriver_hook = bsp_postdriver_hook; - + #if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE ) Cpu_table.interrupt_stack_size = 4096; #endif - + Cpu_table.clicks_per_second = HZ ; } diff --git a/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in b/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in index c879e6a870..231bef4fa5 100644 --- a/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in +++ b/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in @@ -15,11 +15,11 @@ PROJECT_ROOT = @PROJECT_ROOT@ VPATH = @srcdir@ -BSP_PIECES = startup scitab +BSP_PIECES = startup scitab console GENERIC_PIECES = # pieces to pick up out of libcpu/sh -CPU_PIECES = sh7032/null sh7032/clock sh7032/console sh7032/timer +CPU_PIECES = sh7032/null sh7032/clock sh7032/timer sh7032/sci sh7032/delay # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS = $(foreach piece, $(BSP_PIECES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \ @@ -61,8 +61,10 @@ CLOBBER_ADDITIONS += $(LIB): ${OBJS} $(make-library) -all: ${ARCH} $(SRCS) $(LIB) - $(INSTALL_VARIANT) -m 644 $(LIB) $(PROJECT_RELEASE)/lib +$(PROJECT_RELEASE)/lib/libbsp$(LIBSUFFIX_VA): $(LIB) + $(INSTALL_DATA) $^ $@ + +all: ${ARCH} $(SRCS) $(PROJECT_RELEASE)/lib/libbsp$(LIBSUFFIX_VA) install: all diff --git a/c/src/lib/libbsp/sh/gensh2/Makefile.in b/c/src/lib/libbsp/sh/gensh2/Makefile.in new file mode 100644 index 0000000000..6162ab1d6b --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/Makefile.in @@ -0,0 +1,27 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../.. +subdir = sh/gensh2 + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/directory.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +## wrapup is the one that actually builds and installs the library +## from the individual .rel files built in other directories +SUB_DIRS = include start startup scitab console wrapup + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/README b/c/src/lib/libbsp/sh/gensh2/README new file mode 100644 index 0000000000..e5a578fa7c --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/README @@ -0,0 +1,51 @@ +# +# $Id$ +# +# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) +# Adapted by: John Mills (jmills@tga.com) +# + +BSP NAME: generic SH2 (gensh2) +BOARD: n/a +BUS: n/a +CPU FAMILY: Hitachi SH +CPU: SH 7045F +COPROCESSORS: none +MODE: n/a + +DEBUG MONITOR: gdb + +PERIPHERALS +=========== +TIMERS: on-chip + RESOLUTION: cf. Hitachi SH 704X Hardware Manual (Phi/4) +SERIAL PORTS: on-chip (with 2 ports) +REAL-TIME CLOCK: none +DMA: not used +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: on-chip timer +IOSUPP DRIVER: default +SHMSUPP: default +TIMER DRIVER: on-chip timer +TTY DRIVER: /dev/null (stub) + +STDIO +===== +PORT: /dev/null (stub) +ELECTRICAL: n/a +BAUD: n/a +BITS PER CHARACTER: n/a +PARITY: n/a +STOP BITS: n/a + +NOTES +===== + +(1) Only stub console driver available at the moment. + Driver for the on-chip serial devices (sci) will be available soon. + diff --git a/c/src/lib/libbsp/sh/gensh2/bsp_specs b/c/src/lib/libbsp/sh/gensh2/bsp_specs new file mode 100644 index 0000000000..9436cdcd72 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/bsp_specs @@ -0,0 +1,22 @@ +%rename cpp old_cpp +%rename lib old_lib +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*cpp: +%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded) + +*lib: +%{!qrtems: %(old_lib)} \ +%{qrtems: --start-group %{!qrtems_debug: -lrtemsall } %{qrtems_debug: -lrtemsall_g} \ + -lc -lgcc --end-group \ + %{!qnolinkcmds: -T linkcmds%s}} + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{qrtems: %{qrtems_debug: start_g.o%s} %{!qrtems_debug: start.o%s}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e _start} + diff --git a/c/src/lib/libbsp/sh/gensh2/console/Makefile.in b/c/src/lib/libbsp/sh/gensh2/console/Makefile.in new file mode 100644 index 0000000000..0da719d5b9 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/console/Makefile.in @@ -0,0 +1,71 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/console + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@:@top_srcdir@/sh/shared + +PGM = ${ARCH}/console.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = console +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .S +S_PIECES = +S_FILES = $(S_PIECES:%=%.S) +S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o) + +SRCS = $(C_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by +# ../wrapup/Makefile +install: all + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/include/Makefile.in b/c/src/lib/libbsp/sh/gensh2/include/Makefile.in new file mode 100644 index 0000000000..abbcd26b6e --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/include/Makefile.in @@ -0,0 +1,43 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/include + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h + +# +# Equate files are for including from assembly preprocessed by +# gm4 or gasp. No examples are provided except for those for +# other CPUs. The best way to generate them would be to +# provide a program which generates the constants used based +# on the C equivalents. +# + +EQ_FILES = + +SRCS = $(H_FILES) $(EQ_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: $(SRCS) + @INSTALL@ -m 644 $(H_FILES) $(PROJECT_INCLUDE) + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/include/bsp.h b/c/src/lib/libbsp/sh/gensh2/include/bsp.h new file mode 100644 index 0000000000..a403a44ecb --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/include/bsp.h @@ -0,0 +1,139 @@ +/* + * This include file contains all board IO definitions. + * + * generic sh2 + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Minor adaptations for sh2 by: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +#ifndef __gensh2_h +#define __gensh2_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#if 0 +#include +#define BSP_CONSOLE_DEVNAME "/dev/null" +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY +#else +#include +#define BSP_CONSOLE_DEVNAME "/dev/sci1" +#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY +#endif + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ +{ \ + rtems_isr_entry ignored ; \ + rtems_interrupt_catch( (handler), 0, &ignored ) ; \ +} + +#define Cause_tm27_intr() + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +/* Constants */ + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define delay( microseconds ) CPU_delay(microseconds) +#define sh_delay( microseconds ) CPU_delay( microseconds ) + + +/* + * Defined in the linker script 'linkcmds' + */ + +extern unsigned32 HeapStart ; +extern unsigned32 HeapEnd ; +extern unsigned32 WorkSpaceStart ; +extern unsigned32 WorkSpaceEnd ; + +extern void *CPU_Interrupt_stack_low ; +extern void *CPU_Interrupt_stack_high ; + + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +extern void bsp_cleanup( void ); + +/* + * Device Driver Table Entries + */ + +/* + * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console + */ +#undef CONSOLE_DRIVER_TABLE_ENTRY +#define CONSOLE_DRIVER_TABLE_ENTRY \ + BSP_CONSOLE_DRIVER_TABLE_ENTRY, \ + { console_initialize, console_open, console_close, \ + console_read, console_write, console_control } + +/* + * NOTE: Use the standard Clock driver entry + */ + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/sh/gensh2/include/coverhd.h b/c/src/lib/libbsp/sh/gensh2/include/coverhd.h new file mode 100644 index 0000000000..005e19455a --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/include/coverhd.h @@ -0,0 +1,130 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include all + * all calling overhead including passing of arguments. + * + * + * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4 + * on a Hitachi SH7045F Evaluation Board with SH7045F at 29 MHz + * + * These results are assumed to be applicable to most SH7045/29MHz boards + * + * Author: John M.Mills (jmills@tga.com) + * + * COPYRIGHT (c) 1999. TGA Technologies, Inc., Norcross, GA, USA + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * This file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 +#define CALLING_OVERHEAD_TASK_CREATE 2 +#define CALLING_OVERHEAD_TASK_IDENT 1 +#define CALLING_OVERHEAD_TASK_START 1 +#define CALLING_OVERHEAD_TASK_RESTART 1 +#define CALLING_OVERHEAD_TASK_DELETE 1 +#define CALLING_OVERHEAD_TASK_SUSPEND 1 +#define CALLING_OVERHEAD_TASK_RESUME 1 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 +#define CALLING_OVERHEAD_TASK_MODE 1 +#define CALLING_OVERHEAD_TASK_GET_NOTE 1 +#define CALLING_OVERHEAD_TASK_SET_NOTE 1 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 2 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 +#define CALLING_OVERHEAD_CLOCK_GET 3 +#define CALLING_OVERHEAD_CLOCK_SET 2 +#define CALLING_OVERHEAD_CLOCK_TICK 1 + +#define CALLING_OVERHEAD_TIMER_CREATE 1 +#define CALLING_OVERHEAD_TIMER_IDENT 1 +#define CALLING_OVERHEAD_TIMER_DELETE 1 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 3 +#define CALLING_OVERHEAD_TIMER_RESET 1 +#define CALLING_OVERHEAD_TIMER_CANCEL 1 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 1 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 1 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 + +#define CALLING_OVERHEAD_EVENT_SEND 1 +#define CALLING_OVERHEAD_EVENT_RECEIVE 1 +#define CALLING_OVERHEAD_SIGNAL_CATCH 1 +#define CALLING_OVERHEAD_SIGNAL_SEND 1 +#define CALLING_OVERHEAD_PARTITION_CREATE 2 +#define CALLING_OVERHEAD_PARTITION_IDENT 1 +#define CALLING_OVERHEAD_PARTITION_DELETE 1 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 +#define CALLING_OVERHEAD_REGION_CREATE 2 +#define CALLING_OVERHEAD_REGION_IDENT 1 +#define CALLING_OVERHEAD_REGION_DELETE 1 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 +#define CALLING_OVERHEAD_PORT_CREATE 2 +#define CALLING_OVERHEAD_PORT_IDENT 1 +#define CALLING_OVERHEAD_PORT_DELETE 1 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 1 + +#define CALLING_OVERHEAD_IO_INITIALIZE 1 +#define CALLING_OVERHEAD_IO_OPEN 1 +#define CALLING_OVERHEAD_IO_CLOSE 1 +#define CALLING_OVERHEAD_IO_READ 1 +#define CALLING_OVERHEAD_IO_WRITE 1 +#define CALLING_OVERHEAD_IO_CONTROL 1 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/sh/gensh2/scitab/Makefile.in b/c/src/lib/libbsp/sh/gensh2/scitab/Makefile.in new file mode 100644 index 0000000000..023fbe4e39 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/scitab/Makefile.in @@ -0,0 +1,74 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/scitab + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +PGM = $(ARCH)/scitab.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = scitab +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = +# Assembly source names, if any, go here -- minus the .s +S_PIECES = +S_FILES = $(S_PIECES:%=%.s) +S_O_FILES = $(S_FILES:%.s=${ARCH}/%.o) + +SRCS = $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +SHGEN = $(PROJECT_ROOT)/tools/cpu/sh/shgen + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +$(PGM): $(SRCS) ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +scitab.c: $(SHGEN) + $(SHGEN) -H $(HZ) sci > $@ + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/start/Makefile.in b/c/src/lib/libbsp/sh/gensh2/start/Makefile.in new file mode 100644 index 0000000000..6e7cdeba44 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/start/Makefile.in @@ -0,0 +1,70 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/start + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +PGMS = ${ARCH}/start.o + +# C source names, if any, go here -- minus the .c +C_PIECES = +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .S +S_PIECES = start +S_FILES = $(S_PIECES:%=%.S) +S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o) + +SRCS = $(C_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# force optimization, otherwise start.o will not work +# CFLAGS_PROFILE= +# CFLAGS_DEBUG=-O3 +# CFLAGS_OPTIMIZE=-O3 + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: ${ARCH} $(SRCS) $(OBJS) $(PGM) + @$(INSTALL_VARIANT) -m 755 ${PGMS} $(PROJECT_RELEASE)/lib + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/start/start.S b/c/src/lib/libbsp/sh/gensh2/start/start.S new file mode 100644 index 0000000000..f06b284f50 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/start/start.S @@ -0,0 +1,198 @@ +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Modified to reflect Hitachi EDK SH7045F: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * COPYRIGHT (c) 1999. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + PUBLIC(start) + +SYM (start): + ! install the stack pointer + mov.l stack_k,r15 + +#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ + ! Initialize minimal hardware + mov.l hw_init_k, r0 + jsr @r0 + nop !debug dead-slot target +#endif /* START_HW_INIT */ + + ! zero out bss + mov.l edata_k,r0 + mov.l end_k,r1 + mov #0,r2 +0: + mov.l r2,@r0 + add #4,r0 + cmp/ge r0,r1 + bt 0b + nop !debug dead-slot target + + ! copy the vector table from rom to ram + mov.l vects_k,r0 ! vectab + mov #0,r1 ! address of boot vector table + mov #0,r2 ! number of bytes copied + mov.w vects_size,r3 ! size of entries in vectab +1: + mov.l @r1+,r4 + mov.l r4,@r0 + add #4,r0 + add #1,r2 + cmp/hi r3,r2 + bf 1b + nop !debug dead-slot target + + ! overlay monitor vectors onto RTEMS table template + ! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s" + mova vects_k,r0 + mov.l @r0, r1 ! Shadow vect tbl addr + stc vbr, r2 ! Original vect tbl addr + and #0, r0 + mov r0, r4 ! 0 in r4 and r0 + +!trapa #32 + or #0x80, r0 + mov.l @(r0,r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!cpu addr err + or #0x24, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!ill slot + or #0x18, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!ill inst + or #0x10, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!nmi + or #0x2c, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!User brk + or #0x30, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!sci0 err + or #0x80, r0 + rotl r0 + rotl r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 +!sci rx + or #0x81, r0 + rotl r0 + rotl r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + + stc vbr,r3 ! capture copy of monitor vbr + mov.l vbrtemp_k,r0 + mov.l r3, @r0 + mov.l vects_k,r0 ! point vbr to vectab + ldc r0,vbr + + ! call the mainline + mov #0,r4 ! argc + mov #0,r5 ! argv - can place in dead slot + mov.l main_k,r0 + jsr @r0 + nop !debug dead-slot target + + ! call exit + mov r0,r4 + mov.l exit_k,r0 + or r0,r0 + jsr @r0 + nop !debug dead-slot target + + mov.l vbrtemp_k,r0 ! restore original vbr + mov.l @r0,r3 + ldc r3, vbr + trapa #13 ! UBR capture by monitor + nop !debug dead-slot target + + END_CODE + + .align 2 +stack_k: + .long SYM(stack) +edata_k: + .long SYM(edata) +end_k: + .long SYM(end) +main_k: + .long SYM(boot_card) +exit_k: + .long SYM(exit) +#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ +hw_init_k: + .long SYM(hw_initialize) +#endif /* START_HW_INIT */ +vbrtemp_k: + .long SYM(vbrtemp) +vects_k: + .long SYM(vectab) +vects_size: + .word 255 + +#ifdef __ELF__ + .section .stack,"aw" +#else + .section .stack +#endif +SYM(stack): + .long 0xdeaddead + +#ifdef __ELF__ + .section .bss,"aw" +#else + .section .bss +#endif +SYM(vbrtemp): + .long 0x0 + diff --git a/c/src/lib/libbsp/sh/gensh2/start/start.ram b/c/src/lib/libbsp/sh/gensh2/start/start.ram new file mode 100644 index 0000000000..1bbcc9daf2 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/start/start.ram @@ -0,0 +1,199 @@ +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect Hitachi EDK SH7045F: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + PUBLIC(start) + +SYM (start): + ! install the stack pointer + mov.l stack_k,r15 + +#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ + ! Initialize minimal hardware + mov.l hw_init_k, r0 + jsr @r0 + nop !debug dead-slot target +#endif /* START_HW_INIT */ + + ! zero out bss + mov.l edata_k,r0 + mov.l end_k,r1 + mov #0,r2 +0: + mov.l r2,@r0 + add #4,r0 + cmp/ge r0,r1 + bt 0b + nop !debug dead-slot target + + ! copy the vector table from rom to ram + mov.l vects_k,r0 ! vectab + mov #0,r1 ! address of boot vector table + mov #0,r2 ! number of bytes copied + mov.w vects_size,r3 ! size of entries in vectab +1: + mov.l @r1+,r4 + mov.l r4,@r0 + add #4,r0 + add #1,r2 + cmp/hi r3,r2 + bf 1b + nop !debug dead-slot target + + ! overlay monitor vectors onto RTEMS table template + ! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s" + mova vects_k,r0 + mov.l @r0, r1 ! Shadow vect tbl addr + stc vbr, r2 ! Original vect tbl addr + and #0, r0 + mov r0, r4 ! 0 in r4 and r0 + +!trapa #32 + or #0x80, r0 + mov.l @(r0,r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!cpu addr err + or #0x24, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!ill slot + or #0x18, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!ill inst + or #0x10, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!nmi + or #0x2c, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!User brk + or #0x30, r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 + +!sci0 err + or #0x80, r0 + rotl r0 + rotl r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + mov r4, r0 +!sci rx + or #0x81, r0 + rotl r0 + rotl r0 + mov.l @(r0, r2), r3 + mov.l r3, @(r0, r1) + + stc vbr,r3 ! capture copy of monitor vbr + mov.l vbrtemp_k,r0 + mov.l r3, @r0 + mov.l vects_k,r0 ! point vbr to vectab + ldc r0,vbr + + ! call the mainline + mov #0,r4 ! argc + mov #0,r5 ! argv - can place in dead slot + mov.l main_k,r0 + jsr @r0 + nop !debug dead-slot target + + ! call exit + mov r0,r4 + mov.l exit_k,r0 + or r0,r0 + jsr @r0 + nop !debug dead-slot target + + mov.l vbrtemp_k,r0 ! restore original vbr + mov.l @r0,r3 + ldc r3, vbr + trapa #13 ! UBR capture by monitor + nop !debug dead-slot target + + END_CODE + + .align 2 +stack_k: + .long SYM(stack) +edata_k: + .long SYM(edata) +end_k: + .long SYM(end) +main_k: + .long SYM(boot_card) +exit_k: + .long SYM(exit) +#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ +hw_init_k: + .long SYM(hw_initialize) +#endif /* START_HW_INIT */ +vbrtemp_k: + .long SYM(vbrtemp) +vects_k: + .long SYM(vectab) +vects_size: + .word 255 + +#ifdef __ELF__ + .section .stack,"aw" +#else + .section .stack +#endif +SYM(stack): + .long 0xdeaddead + +#ifdef __ELF__ + .section .bss,"aw" +#else + .section .bss +#endif +SYM(vbrtemp): + .long 0x0 + diff --git a/c/src/lib/libbsp/sh/gensh2/start/start.rom b/c/src/lib/libbsp/sh/gensh2/start/start.rom new file mode 100644 index 0000000000..9deeb53fed --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/start/start.rom @@ -0,0 +1,94 @@ +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + PUBLIC(start) +SYM (start): + ! install the stack pointer + mov.l stack_k,r15 + + ! zero out bss + mov.l edata_k,r0 + mov.l end_k,r1 + mov #0,r2 +0: + mov.l r2,@r0 + add #4,r0 + cmp/ge r0,r1 + bt 0b + + ! copy the vector table from rom to ram + mov.l vects_k,r0 ! vectab + mov #0,r1 ! address of boot vector table + mov #0,r2 | number of bytes copied + mov.w vects_size,r3 ! size of entries in vectab +1: + mov.l @r1+,r4 + mov.l r4,@r0 + add #4,r0 + add #1,r2 + cmp/hi r3,r2 + bf 1b + + mov.l vects_k,r0 ! update vbr to point to vectab + ldc r0,vbr + + ! call the mainline + mov #0,r4 ! argc + mov.l main_k,r0 + jsr @r0 + mov #0,r5 ! argv + + ! call exit + mov r0,r4 + mov.l exit_k,r0 + jsr @r0 + or r0,r0 + + END_CODE + + .align 2 +stack_k: + .long SYM(stack) +edata_k: + .long SYM(edata) +end_k: + .long SYM(end) +main_k: + .long SYM(boot_card) +exit_k: + .long SYM(exit) + +vects_k: + .long SYM(vectab) +vects_size: + .word 255 + +#ifdef __ELF__ + .section .stack,"aw" +#else + .section .stack +#endif +SYM(stack): + .long 0xdeaddead diff --git a/c/src/lib/libbsp/sh/gensh2/startup/Makefile.in b/c/src/lib/libbsp/sh/gensh2/startup/Makefile.in new file mode 100644 index 0000000000..5b758601f5 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/Makefile.in @@ -0,0 +1,77 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/startup + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared + +PGM = ${ARCH}/startup.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = hw_init bsplibc bsppost bspstart bspclean sbrk bootcard main \ + gnatinstallhandler +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .s +S_PIECES = +S_FILES = $(S_PIECES:%=%.S) +S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o) + +SRCS = linkcmds $(C_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ +mkinstalldirs = $(SHELL) $(top_srcdir)/@RTEMS_TOPdir@/mkinstalldirs + +INSTALLDIRS = $(PROJECT_RELEASE)/lib + +$(INSTALLDIRS): + @$(mkinstalldirs) $(INSTALLDIRS) + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += $(BSP_CPPFLAGS) +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + $(INSTALL_CHANGE) -m 644 $(srcdir)/linkcmds $(PROJECT_RELEASE)/lib + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/startup/bspclean.c b/c/src/lib/libbsp/sh/gensh2/startup/bspclean.c new file mode 100644 index 0000000000..fed966fdb4 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/bspclean.c @@ -0,0 +1,43 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, write to the Free Software Foundation, + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +void bsp_cleanup( void ) +{ +#if 0 + rtems_fatal_error_occurred(0); +#endif +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/bspstart.c b/c/src/lib/libbsp/sh/gensh2/startup/bspstart.c new file mode 100644 index 0000000000..abf97c3a86 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/bspstart.c @@ -0,0 +1,138 @@ +/* + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +#include + +#include + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern void hw_initialize(void); + +extern rtems_configuration_table Configuration; + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +char *rtems_progname; + +/* + * Use the shared implementations of the following routines + */ + +void bsp_postdriver_hook(void); +void bsp_libc_init( void *, unsigned32, int ); + +/* + * Function: bsp_pretasking_hook + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void bsp_pretasking_hook(void) +{ + bsp_libc_init(&HeapStart, sizeof(unsigned32) * (&HeapEnd - &HeapStart), 0); + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + +/* + * bsp_start + * + * This routine does the bulk of the system initialization. + */ + +void bsp_start(void) +{ + /* + For real boards you need to setup the hardware + and need to copy the vector table from rom to ram. + + Depending on the board this can ether be done from inside the rom + startup code, rtems startup code or here. + */ + hw_initialize(); + + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ; + BSP_Configuration.work_space_size = + (unsigned32) &WorkSpaceEnd - + (unsigned32) &WorkSpaceStart ; + + /* + * initialize the CPU table for this BSP + */ + +#if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE ) + _CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low ; + _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ; + + /* This isn't used anywhere */ + Cpu_table.interrupt_stack_size = + (unsigned32) (&CPU_Interrupt_stack_high) - + (unsigned32) (&CPU_Interrupt_stack_low) ; +#endif + + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + Cpu_table.postdriver_hook = bsp_postdriver_hook; + +#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE ) + Cpu_table.interrupt_stack_size = 4096; +#endif + + Cpu_table.clicks_per_second = HZ ; +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c b/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c new file mode 100644 index 0000000000..be2cdab35b --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c @@ -0,0 +1,140 @@ +/* + * hw_init.c: set up sh7045F internal subunits + * + * Author: John M. Mills (jmills@tga.com) + * COPYRIGHT(c) 1999, TGA Technologies, Inc + * Norcross, GA 30071 U.S.A + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Adapted from Hitachi EVB7045F tutorial files by: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +#include + +#include + +#include +#include +#include +#include + +/* exported entry */ +extern void hw_initialize (void); + +/* STANDALONE_EVB sets up bus, DRAM, PFC, and SCI0 */ +/* no STANDALONE_EVB accepts defaults, adds RESET, SCI1, WDT */ + +/***************************************************/ +/* Inline function to access CPU features */ +/* from C. This makes use of GNU extensions. */ +/***************************************************/ + +__inline__ void set_interrupt_mask(unsigned char mask) +{ + asm("mov.l r0,@-r15"); + asm("mov %0,r0"::"r"(mask)); + asm("and #0xF,r0"); + asm("rotl r0"); + asm("rotl r0"); + asm("rotl r0"); + asm("rotl r0"); + asm("ldc r0,sr"); + asm("mov.l @r15+,r0"); +} + +void hw_initialize (void) +{ + int a; + unsigned8 temp8; + unsigned16 temp16; + +#ifdef STANDALONE_EVB + write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */ + write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/ + write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */ + write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */ + write16(0x0000, BSC_DCR); /* DRAM control - default */ + write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */ + write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/ + write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */ + + write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */ + write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */ + write16(0x0000, PFC_PBCR1); /* Pin function controller - default */ + write16(0x2005, PFC_PBCR2); /* Pin function controller - A18,A17,A16 */ + write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */ + write16(0x5555, PFC_PDCRH1; /* Pin function controller - D31-D24 */ + write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */ + write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */ + write16(0x0000, PFC_IFCR); /* Pin function controller - default */ + write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */ + + /* SCI0 */ +/* FIXME: This doesn't belong here */ + write8(0x00, SCI_SCR0); /* Clear SCR */ + write8(0x00, SCI_SMR0); /* Clear SMR */ + write8(0x5F, SCI_BRR0); /* Default 9600 baud rate */ +#if 0 + write8(0x1F, SCI_BRR0); /* 28800 baud */ +#endif +/* FIXME: Will get optimized away */ + for(a=0;a<00000L;a++); /* One bit delay */ + write8(0x30, SCI_SCR0); /* Enable clock output */ + temp8 = read8(SCI_RDR0); /* Clear out old input */ + +#endif + + /* default hardware setup */ + + /* PFC: General I/O except pin 13 (reset): */ + temp16 = read16(PFC_PECR1) | 0x0800; + write16(temp16, PFC_PECR1); + + /* All I/O lines bits 7-0: */ + write16(0x00, PFC_PECR2); + + /* P5 out, all other pins in: */ + temp16 = read16(PFC_PEIOR) | 0x0020; + write16(temp16, PFC_PEIOR); + + /* PFC - pins for Tx0-1, Rx0-1: */ + temp16 = read16(PFC_PACRL2) | 0x0145; + write16(temp16, PFC_PACRL2); + + /* SCI1 - Default RTEMS console */ +#if FIXME + /* write8(0x00, SCI_SCR1); /* Clear SCR */ + /* write8(0x00, SCI_SMR1); /* Clear SMR */ + /* write8(0x5F, SCI_BRR1); /* Default 9600 baud rate */ + /* write8(0x1F, SCI_BRR1); /* 28800 baud */ +/* FIXME: Will get optimized away */ + /* for(a=0;a<10000L;a++); /* One bit delay */ + /* write8(0x30, SCI_SCR1); /* Enable clock output */ + /* temp8 = read8(SCI_RDR1); /* Clear out old input */ + + /* INTC setup */ + /* set_interrupt_mask(0); /* enable interrupts */ + /* INTC_IPRF &= ~(SCI1_IPMSK); /* set SIO1 priority at INTC */ + /* INTC_IPRF |= SCI1_LOWIP; */ +#endif +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/linkcmds b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds new file mode 100644 index 0000000000..71258d7fe8 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds @@ -0,0 +1,216 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ + +MEMORY +{ + rom : o = 0x00400000, l = 0x00040000 + ram : o = 0x00440000, l = 0x00040000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00400000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00440000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00442000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00444000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x00480000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0xFFFFF000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram new file mode 100644 index 0000000000..71258d7fe8 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram @@ -0,0 +1,216 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ + +MEMORY +{ + rom : o = 0x00400000, l = 0x00040000 + ram : o = 0x00440000, l = 0x00040000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00400000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00440000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00442000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00444000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x00480000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0xFFFFF000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom new file mode 100644 index 0000000000..54d28e5552 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom @@ -0,0 +1,217 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +/* These asignments represent actual SH7045F EVB architecture */ + +MEMORY +{ + rom : o = 0x00000000, l = 0x00040000 + ram : o = 0x00400000, l = 0x00080000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00000000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00400000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00402000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00404000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x00480000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0xFFFFF000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.in b/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.in new file mode 100644 index 0000000000..19f6e613c5 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/wrapup/Makefile.in @@ -0,0 +1,69 @@ +# +# $Id$ +# +# build and install libbsp +# + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/wrapup + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +BSP_PIECES = startup scitab console +GENERIC_PIECES = + +# pieces to pick up out of libcpu/sh +CPU_PIECES = sh7045/null sh7045/clock sh7045/timer sh7045/sci + +# bummer; have to use $foreach since % pattern subst rules only replace 1x +OBJS = $(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ + $(foreach piece, $(CPU_PIECES), \ + ../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(notdir $(piece)).rel) \ + $(foreach piece, $(GENERIC_PIECES), \ + ../../../../$(piece)/$(ARCH)/$(piece).rel) + +LIB = $(ARCH)/libbsp.a + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/lib.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +$(LIB): ${OBJS} + $(make-library) + +all: ${ARCH} $(SRCS) $(LIB) + $(INSTALL_VARIANT) -m 644 $(LIB) $(PROJECT_RELEASE)/lib + +install: all +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libcpu/sh/sh7032/Makefile.in b/c/src/lib/libcpu/sh/sh7032/Makefile.in index b91162bc3a..34e6494f8b 100644 --- a/c/src/lib/libcpu/sh/sh7032/Makefile.in +++ b/c/src/lib/libcpu/sh/sh7032/Makefile.in @@ -18,7 +18,7 @@ include $(RTEMS_ROOT)/make/directory.cfg INSTALL_CHANGE = @INSTALL_CHANGE@ -SUB_DIRS = include clock console timer null +SUB_DIRS = include clock timer null sci delay Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status cd $(top_builddir) \ diff --git a/c/src/lib/libcpu/sh/sh7032/clock/Makefile.in b/c/src/lib/libcpu/sh/sh7032/clock/Makefile.in index c9bd2ac92d..5617ae594e 100644 --- a/c/src/lib/libcpu/sh/sh7032/clock/Makefile.in +++ b/c/src/lib/libcpu/sh/sh7032/clock/Makefile.in @@ -40,7 +40,7 @@ INSTALL_CHANGE = @INSTALL_CHANGE@ # DEFINES += -CPPFLAGS += -DMHZ=$(MHZ) +CPPFLAGS += CFLAGS += $(CFLAGS_OS_V) LD_PATHS += diff --git a/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c b/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c index 7aef64ed99..a8acc1ca20 100644 --- a/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c +++ b/c/src/lib/libcpu/sh/sh7032/clock/ckinit.c @@ -29,25 +29,85 @@ #include #include #include -#include -#include - -#define _ITU_COUNTER0_MICROSECOND (MHZ/4) +#include +#include #ifndef CLOCKPRIO #define CLOCKPRIO 10 #endif +#define I_CLK_PHI_1 0 +#define I_CLK_PHI_2 1 +#define I_CLK_PHI_4 2 +#define I_CLK_PHI_8 3 + +/* + * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose + * a PHI/X clock rate. + */ + +#define I_CLK_PHI I_CLK_PHI_4 +#define CLOCK_SCALE (1< 0 ) + { + c /= 10 ; + d *= 10 ; + a = ( ( b / c ) * usec_per_tick ) / d ; + clicks_per_tick += a ; + } + return clicks_per_tick ; +#else + double fclicks_per_tick = + ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ; + return (unsigned32) fclicks_per_tick ; +#endif +} + /* * The interrupt vector number associated with the clock tick device * driver. @@ -100,7 +160,6 @@ rtems_isr Clock_isr( /* * bump the number of clock driver ticks since initialization * - * determine if it is time to announce the passing of tick as configured * to RTEMS through the rtems_clock_tick directive * @@ -137,13 +196,31 @@ void Install_clock( ) { unsigned8 temp8 = 0; + unsigned32 microseconds_per_tick ; + unsigned32 cclicks_per_tick ; + unsigned16 Clock_limit ; /* * Initialize the clock tick device driver variables */ Clock_driver_ticks = 0; - Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000; + + if ( rtems_configuration_get_microseconds_per_tick() != 0 ) + microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ; + else + microseconds_per_tick = 10000 ; /* 10000 us */ + + /* clock clicks per tick */ + cclicks_per_tick = + sh_clicks_per_tick( + rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE, + microseconds_per_tick ); + + Clock_isrs_const = cclicks_per_tick >> 16 ; + if ( ( cclicks_per_tick | 0xffff ) > 0 ) + Clock_isrs_const++ ; + Clock_limit = cclicks_per_tick / Clock_isrs_const ; Clock_isrs = Clock_isrs_const; /* @@ -191,8 +268,7 @@ void Install_clock( rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); /* set counter limits */ - write16( _ITU_COUNTER0_MICROSECOND * rtems_configuration_get_microseconds_per_tick(), - ITU_GRA0); + write16( Clock_limit, ITU_GRA0); /* start counter */ temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK; diff --git a/c/src/lib/libcpu/sh/sh7032/console/Makefile.in b/c/src/lib/libcpu/sh/sh7032/console/Makefile.in deleted file mode 100644 index 33710ef51f..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/console/Makefile.in +++ /dev/null @@ -1,71 +0,0 @@ -# -# $Id$ -# - -@SET_MAKE@ -srcdir = @srcdir@ -top_srcdir = @top_srcdir@ -top_builddir = ../../.. -subdir = sh/sh7032/console - -RTEMS_ROOT = @RTEMS_ROOT@ -PROJECT_ROOT = @PROJECT_ROOT@ - -VPATH = @srcdir@ - -PGM = ${ARCH}/console.rel - -# C source names, if any, go here -- minus the .c -C_PIECES = console -C_FILES = $(C_PIECES:%=%.c) -C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) - -H_FILES = - -# Assembly source names, if any, go here -- minus the .S -S_PIECES = -S_FILES = $(S_PIECES:%=%.S) -S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o) - -SRCS = $(C_FILES) $(H_FILES) $(S_FILES) -OBJS = $(C_O_FILES) $(S_O_FILES) - -include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg -include $(RTEMS_ROOT)/make/leaf.cfg - -INSTALL_CHANGE = @INSTALL_CHANGE@ - -# -# (OPTIONAL) Add local stuff here using += -# - -DEFINES += -CPPFLAGS += -CFLAGS += - -LD_PATHS += -LD_LIBS += -LDFLAGS += - -# -# Add your list of files to delete here. The config files -# already know how to delete some stuff, so you may want -# to just run 'make clean' first to see what gets missed. -# 'make clobber' already includes 'make clean' -# - -CLEAN_ADDITIONS += -CLOBBER_ADDITIONS += - -${PGM}: ${SRCS} ${OBJS} - $(make-rel) - -all: ${ARCH} $(SRCS) $(PGM) - -# the .rel file built here will be put into libbsp.a by -# libbsp/sh/BSP/wrapup/Makefile -install: all - -Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status - cd $(top_builddir) \ - && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libcpu/sh/sh7032/console/console.c b/c/src/lib/libcpu/sh/sh7032/console/console.c deleted file mode 100644 index 6c16adfa5f..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/console/console.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * /dev/console for Hitachi SH 703X - * - * The SH doesn't have a designated console device. Therefore we "alias" - * another device as /dev/console and revector all calls to /dev/console - * to this device. - * - * This approach is similar to installing a sym-link from one device to - * another device. If rtems once will support sym-links for devices files, - * this implementation could be dropped. - * - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include -#include -#include -#include - -#ifndef CPU_CONSOLE_DEVNAME -#error Missing CPU_CONSOLE_DEVNAME -#endif - -static rtems_driver_name_t *low_level_device_info = NULL ; - -/* console_initialize - * - * This routine initializes the console IO driver. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * Return values: - */ - -rtems_device_driver console_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - rtems_device_driver status ; - - status = rtems_io_register_name( - "/dev/console", - major, - (rtems_device_minor_number) 0 - ); - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - status = rtems_io_lookup_name( CPU_CONSOLE_DEVNAME, - &low_level_device_info ); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - return RTEMS_SUCCESSFUL; -} - - -/* - * Open entry point - */ - -rtems_device_driver console_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_io_open( low_level_device_info->major, - low_level_device_info->minor, - arg ); -} - -/* - * Close entry point - */ - -rtems_device_driver console_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_io_close( low_level_device_info->major, - low_level_device_info->minor, - arg ); -} - -/* - * read bytes from the serial port. We only have stdin. - */ - -rtems_device_driver console_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_io_read( low_level_device_info->major, - low_level_device_info->minor, - arg ); -} - -/* - * write bytes to the serial port. Stdout and stderr are the same. - */ - -rtems_device_driver console_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_io_write( low_level_device_info->major, - low_level_device_info->minor, - arg ); -} - -/* - * IO Control entry point - */ - -rtems_device_driver console_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - return rtems_io_control( low_level_device_info->major, - low_level_device_info->minor, - arg ); -} diff --git a/c/src/lib/libcpu/sh/sh7032/include/Makefile.in b/c/src/lib/libcpu/sh/sh7032/include/Makefile.in index 5f180b27f3..fb379f14eb 100644 --- a/c/src/lib/libcpu/sh/sh7032/include/Makefile.in +++ b/c/src/lib/libcpu/sh/sh7032/include/Makefile.in @@ -13,8 +13,8 @@ PROJECT_ROOT = @PROJECT_ROOT@ VPATH = @srcdir@ -H_FILES = $(srcdir)/ioqueue.h $(srcdir)/null.h $(srcdir)/sci.h \ - $(srcdir)/sh7_pfc.h $(srcdir)/sh7_sci.h +H_FILES = $(srcdir)/null.h $(srcdir)/sci.h $(srcdir)/sh7_pfc.h \ + $(srcdir)/sh7_sci.h SRCS = $(H_FILES) diff --git a/c/src/lib/libcpu/sh/sh7032/include/ioqueue.h b/c/src/lib/libcpu/sh/sh7032/include/ioqueue.h deleted file mode 100644 index 55020acfad..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/include/ioqueue.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Defines for low level queue management - * - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, Ralf Corsepius, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef _io_queue_h -#define _io_queue_h - -#include /* size_t */ - -/* - * NOTE: size needs to be a power of 2 - */ -#define IO_QUEUE(type,size,name) \ -typedef struct { \ - volatile type queue[size] ; \ - volatile unsigned short tail ; \ - volatile unsigned short head ; \ -} name ; - -#define IO_QUEUE_FULL(queue, size) \ - ((queue)->tail == (((queue)->head+1) & ((size)-1))) - -#define IO_QUEUE_EMPTY(queue) \ - (((queue)->tail) == ((queue)->head)) - -#define IO_QUEUE_INIT(queue) \ - (queue)->tail = (queue)->head = 0 - -#define IO_QUEUE_ADD(queue,size) \ - (queue)->head = (((queue)->head + 1) & ((size)-1)) - -#define IO_QUEUE_SUB(queue,size) \ - (queue)->tail = (((queue)->tail + 1) & ((size)-1)) - -#define IO_QUEUE_PUT(_queue,item) \ -{ \ - size_t i; \ - unsigned char* dest = (unsigned char*) ((_queue)->queue[(_queue)->head]); \ - unsigned char* src = (unsigned char*) (item); \ - for( i = 0; i < sizeof(item); i++) \ - { \ - dest[i] = src[i]; \ - } \ -} - -#define IO_QUEUE_GET(_queue,item) \ -{\ - size_t i; \ - unsigned char *src = (unsigned char*) (_queue)->queue[(_queue)->tail]; \ - unsigned char *dest = (unsigned char*) (item); \ - for( i=0; i< sizeof(item); i++)\ - {\ - dest[i] = src[i]; \ - }\ -} - -#endif diff --git a/c/src/lib/libcpu/sh/sh7032/include/sci.h b/c/src/lib/libcpu/sh/sh7032/include/sci.h index d897003315..b2468400b8 100644 --- a/c/src/lib/libcpu/sh/sh7032/include/sci.h +++ b/c/src/lib/libcpu/sh/sh7032/include/sci.h @@ -78,12 +78,6 @@ extern rtems_device_driver sh_sci_control( void * ); -/* Internal error codes */ -#define SH_TTY_NO_ERROR 0x2000 -#define SH_TTY_FRAME_ERR 0x2001 -#define SH_TTY_PARITY_ERR 0x2002 -#define SH_TTY_OVERRUN_ERR 0x2003 - #ifdef __cplusplus } #endif diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h index ba6580c5fd..6e12740340 100644 --- a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h +++ b/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h @@ -27,7 +27,7 @@ #ifndef _sh7_pfc_h #define _sh7_pfc_h -#include +#include /* * Port B IO Register (PBIOR) diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h index cb2cc03893..3bd01ecc8f 100644 --- a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h +++ b/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h @@ -27,7 +27,7 @@ #ifndef _sh7_sci_h #define _sh7_sci_h -#include +#include /* * Serial mode register bits diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c index 42764f6eb1..192c2f43d2 100644 --- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c +++ b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c @@ -41,10 +41,17 @@ #include #include #include -#include -#include #include -#include + +#if defined(sh7032) +#include +#include +#elif defined (sh7045) +#include +#include +#endif + +#include /* from cpu_isps.c */ extern proc_ptr _Hardware_isr_Table[]; diff --git a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c index 3ef3c32465..9fcc9badbf 100644 --- a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c +++ b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c @@ -30,10 +30,14 @@ #include #include -#include +#include + +#if !defined(sh7032) +#error Wrong CPU MODEL +#endif /* - * This is a exception vector table + * This is an exception vector table * * It has the same structure like the actual vector table (vectab) */ diff --git a/c/src/lib/libcpu/sh/sh7032/timer/Makefile.in b/c/src/lib/libcpu/sh/sh7032/timer/Makefile.in index 735ef3961d..ce19bbb25c 100644 --- a/c/src/lib/libcpu/sh/sh7032/timer/Makefile.in +++ b/c/src/lib/libcpu/sh/sh7032/timer/Makefile.in @@ -40,7 +40,7 @@ INSTALL_CHANGE = @INSTALL_CHANGE@ # DEFINES += -CPPFLAGS += -DMHZ=$(MHZ) +CPPFLAGS += CFLAGS += LD_PATHS += diff --git a/c/src/lib/libcpu/sh/sh7032/timer/timer.c b/c/src/lib/libcpu/sh/sh7032/timer/timer.c index 03ffdd7e56..9dd57a4bb4 100644 --- a/c/src/lib/libcpu/sh/sh7032/timer/timer.c +++ b/c/src/lib/libcpu/sh/sh7032/timer/timer.c @@ -32,17 +32,26 @@ #include #include -#include +#include +#include + +#define I_CLK_PHI_1 0 +#define I_CLK_PHI_2 1 +#define I_CLK_PHI_4 2 +#define I_CLK_PHI_8 3 /* - * We use a Phi/4 timer + * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose + * a PHI/X clock rate. */ -#define SCALE (MHZ/4) + +#define I_CLK_PHI I_CLK_PHI_4 +#define CLOCK_SCALE (1< + +#include + +#include +#include +#include +#include +#include + +#define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/4) + +#ifndef CLOCKPRIO +#define CLOCKPRIO 10 +#endif + +#define MTU0_STARTMASK 0xfe +#define MTU0_SYNCMASK 0xfe +#define MTU0_MODEMASK 0xc0 +#define MTU0_TCRMASK 0x01 /* bit 7 also used, vs 703x */ +#define MTU0_STAT_MASK 0xc0 +#define MTU0_IRQMASK 0xfe +#define MTU0_TIERMASK 0x01 +#define IPRC_MTU0_MASK 0xff0f +#define MTU0_TIORVAL 0x08 + +/* + * The interrupt vector number associated with the clock tick device + * driver. + */ + +#define CLOCK_VECTOR MTUA0_ISP_V + +/* + * Clock_driver_ticks is a monotonically increasing counter of the + * number of clock ticks since the driver was initialized. + */ + +volatile rtems_unsigned32 Clock_driver_ticks; + +static void Clock_exit( void ); +static rtems_isr Clock_isr( rtems_vector_number vector ); +static rtems_unsigned32 Clock_MHZ ; + +/* + * Clock_isrs is the number of clock ISRs until the next invocation of + * the RTEMS clock tick routine. The clock tick device driver + * gets an interrupt once a millisecond and counts down until the + * length of time between the user configured microseconds per tick + * has passed. + */ + +rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ +static rtems_unsigned32 Clock_isrs_const; /* only calculated once */ + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +/* + * The previous ISR on this clock tick interrupt vector. + */ + +rtems_isr_entry Old_ticker; + +/* + * Isr Handler + */ + +rtems_isr Clock_isr( + rtems_vector_number vector +) +{ + /* + * bump the number of clock driver ticks since initialization + * + + * determine if it is time to announce the passing of tick as configured + * to RTEMS through the rtems_clock_tick directive + * + * perform any timer dependent tasks + */ + unsigned8 temp; + + /* reset the flags of the status register */ + temp = read8( MTU_TSR0) & MTU0_STAT_MASK; + write8( temp, MTU_TSR0); + + Clock_driver_ticks++ ; + + if( Clock_isrs == 1) + { + rtems_clock_tick(); + Clock_isrs = Clock_isrs_const; + } + else + { + Clock_isrs-- ; + } +} + +/* + * Install_clock + * + * Install a clock tick handler and reprograms the chip. This + * is used to initially establish the clock tick. + */ + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + unsigned8 temp8 = 0; + + /* + * Initialize the clock tick device driver variables + */ + + Clock_driver_ticks = 0; + Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000; + Clock_isrs = Clock_isrs_const; + + Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ; + + /* + * If ticks_per_timeslice is configured as non-zero, then the user + * wants a clock tick. + */ + + if ( rtems_configuration_get_ticks_per_timeslice() ) { + rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); + /* + * Hardware specific initialize goes here + */ + + /* stop Timer 0 */ + temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; + write8( temp8, MTU_TSTR); + + /* set initial counter value to 0 */ + write16( 0, MTU_TCNT0); + + /* Timer 0 runs independent */ + temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK; + write8( temp8, MTU_TSYR); + + /* Timer 0 normal mode */ + temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK; + write8( temp8, MTU_TMDR0); + + /* TCNT is cleared by GRA ; internal clock /4 */ + write8( MTU0_TCRMASK , MTU_TCR0); + + /* use GRA without I/O - pins */ + write8( MTU0_TIORVAL, MTU_TIORL0); + + /* reset flags of the status register */ + temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK; + write8( temp8, MTU_TSR0); + + /* Irq if is equal GRA */ + temp8 = read8( MTU_TIER0) | MTU0_TIERMASK; + write8( temp8, MTU_TIER0); + + /* set interrupt priority */ + if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); + + /* set counter limits */ + write16( _MTU_COUNTER0_MICROSECOND * + rtems_configuration_get_microseconds_per_tick(), + + MTU_GR0A); + + /* start counter */ + temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK; + write8( temp8, MTU_TSTR); + + } + + /* + * Schedule the clock cleanup routine to execute if the application exits. + */ + + atexit( Clock_exit ); +} + +/* + * Clean up before the application exits + */ + +void Clock_exit( void ) +{ + unsigned8 temp8 = 0; + if ( rtems_configuration_get_ticks_per_timeslice() ) { + + /* turn off the timer interrupts */ + /* set interrupt priority to 0 */ + if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred( RTEMS_UNSATISFIED); + +/* + * temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK; + * write16( temp16, MTU_TIER0); + */ + + /* stop counter */ + temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; + write8( temp8, MTU_TSTR); + + /* old vector shall not be installed */ + } +} + +/* + * Clock_initialize + * + * Device driver entry point for clock tick driver initialization. + */ + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_unsigned32 isrlevel; + rtems_libio_ioctl_args_t *args = pargp; + + if (args != 0) + { + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) + { + Clock_isr(CLOCK_VECTOR); + } + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) + { + rtems_isr_entry ignored ; + rtems_interrupt_disable( isrlevel ); + rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored ); + + rtems_interrupt_enable( isrlevel ); + } + } + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/include/Makefile.in b/c/src/lib/libcpu/sh/sh7045/include/Makefile.in new file mode 100644 index 0000000000..bf69d92121 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/include/Makefile.in @@ -0,0 +1,46 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/sh7045/include + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +H_FILES = $(srcdir)/io_types.h $(srcdir)/null.h $(srcdir)/sci.h \ + $(srcdir)/sh7_pfc.h $(srcdir)/sh7_sci.h + +SRCS = $(H_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ +mkinstalldirs = $(SHELL) $(top_srcdir)/@RTEMS_TOPdir@/mkinstalldirs + +INSTALLDIRS = $(PROJECT_INCLUDE)/sh + +$(INSTALLDIRS): + @$(mkinstalldirs) $(INSTALLDIRS) + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: install + +# NOTE: Unlike other CPUS, we install into a subdirectory to avoid +# file name conflicts + +install: + $(mkinstalldirs) $(PROJECT_INCLUDE)/sh + @$(INSTALL_CHANGE) -m 644 $(H_FILES) $(PROJECT_INCLUDE)/sh + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libcpu/sh/sh7045/include/io_types.h b/c/src/lib/libcpu/sh/sh7045/include/io_types.h new file mode 100644 index 0000000000..18ba181143 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/include/io_types.h @@ -0,0 +1,87 @@ +/************************************************************************ + * + * Data types and constants for Hitachi SH704X on-chip peripherals + * + * Author: John M.Mills (jmills@tga.com) + * + * COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * This file may be distributed as part of the RTEMS software item. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + * + * + ************************************************************************/ + +#ifndef _sh_io_types_h +#define _sh_io_types_h + +#include +#include + +typedef enum {SCI0, SCI1} portNo; +typedef enum {eight, seven} dataBits; +typedef enum {one, two} stopBits; +typedef enum {even, odd} parity; + +typedef struct { + portNo line; + int speed_ix; + dataBits dBits; + int parEn; + parity par; + int mulPro; + stopBits sBits; +} sci_setup_t; + +typedef union{ + unsigned char Reg; /* By Register */ + struct { /* By Field */ + unsigned char Sync :1; /* Async/Sync */ + unsigned char DBts :1; /* Char.Length */ + unsigned char ParEn :1; /* Parity En.*/ + unsigned char Odd :1; /* Even/Odd */ + unsigned char SBts :1; /* No.Stop Bits */ + unsigned char MulP :1; /* Multi-Proc. */ + unsigned char Dvsr :2; /* Clock Sel. */ + } Fld; +} sci_smr_t; + +typedef union { + unsigned char Reg; /* By Register */ + struct { /* By Field */ + unsigned char TIE :1; /* Tx.Int.En. */ + unsigned char RIE :1; /* Rx.Int.En. */ + unsigned char TE :1; /* Tx.En. */ + unsigned char RE :1; /* Rx.En. */ + unsigned char MPIE:1; /* Mult.Pro.Int.En. */ + unsigned char TEIE:1; /* Tx.End Int.En. */ + unsigned char CkSrc :2; /* Clock Src. */ + } Fld; +} sci_scr_t; + +typedef struct { + unsigned char n ; + unsigned char N ; +} sci_bitrate_t; + +#endif /* _sh_io_types_h */ + diff --git a/c/src/lib/libcpu/sh/sh7045/include/null.h b/c/src/lib/libcpu/sh/sh7045/include/null.h new file mode 100644 index 0000000000..9ce4886c14 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/include/null.h @@ -0,0 +1,72 @@ +/* null.h + * + * Null device driver, derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __NULL_DRIVER_h +#define __NULL_DRIVER_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define DEVNULL_DRIVER_TABLE_ENTRY \ + { null_initialize, null_open, null_close, null_read, \ + null_write, null_control } + +#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL + +rtems_device_driver null_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver null_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver null_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver null_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver null_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver null_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libcpu/sh/sh7045/include/sci.h b/c/src/lib/libcpu/sh/sh7045/include/sci.h new file mode 100644 index 0000000000..c18321899c --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/include/sci.h @@ -0,0 +1,85 @@ +/* + * Driver for the sh2 704x on-chip serial devices (sci) + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _sh_sci_h +#define _sh_sci_h + +#ifdef __cplusplus +extern"C" { +#endif + +/* + * Devices are set to 9600 bps, 8 databits, 1 stopbit, no + * parity and asynchronous mode by default. + * + * NOTE: + * The onboard serial devices of the SH do not support hardware + * handshake. + */ + +#define DEVSCI_DRIVER_TABLE_ENTRY \ + { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ + sh_sci_write, sh_sci_control } + +extern rtems_device_driver sh_sci_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h new file mode 100644 index 0000000000..5be9ca8a5d --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h @@ -0,0 +1,118 @@ +/* + * Bit values for the pin function controller of the Hitachi SH704x + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _sh7_pfc_h +#define _sh7_pfc_h + +#include + +/* + * Port B IO Register (PBIOR) + */ +#define PBIOR PFC_PBIOR +#define PB15IOR 0x8000 +#define PB14IOR 0x4000 +#define PB13IOR 0x2000 +#define PB12IOR 0x1000 +#define PB11IOR 0x0800 +#define PB10IOR 0x0400 +#define PB9IOR 0x0200 +#define PB8IOR 0x0100 +#define PB7IOR 0x0080 +#define PB6IOR 0x0040 +#define PB5IOR 0x0020 +#define PB4IOR 0x0010 +#define PB3IOR 0x0008 +#define PB2IOR 0x0004 +#define PB1IOR 0x0002 +#define PB0IOR 0x0001 + +/* + * Port B Control Register (PBCR1) + */ +#define PBCR1 PFC_PBCR1 +#define PB15MD1 0x8000 +#define PB15MD0 0x4000 +#define PB14MD1 0x2000 +#define PB14MD0 0x1000 +#define PB13MD1 0x0800 +#define PB13MD0 0x0400 +#define PB12MD1 0x0200 +#define PB12MD0 0x0100 +#define PB11MD1 0x0080 +#define PB11MD0 0x0040 +#define PB10MD1 0x0020 +#define PB10MD0 0x0010 +#define PB9MD1 0x0008 +#define PB9MD0 0x0004 +#define PB8MD1 0x0002 +#define PB8MD0 0x0001 + +#define PB15MD PB15MD1|PB14MD0 +#define PB14MD PB14MD1|PB14MD0 +#define PB13MD PB13MD1|PB13MD0 +#define PB12MD PB12MD1|PB12MD0 +#define PB11MD PB11MD1|PB11MD0 +#define PB10MD PB10MD1|PB10MD0 +#define PB9MD PB9MD1|PB9MD0 +#define PB8MD PB8MD1|PB8MD0 + +#define PB_TXD1 PB11MD1 +#define PB_RXD1 PB10MD1 +#define PB_TXD0 PB9MD1 +#define PB_RXD0 PB8MD1 + +/* + * Port B Control Register (PBCR2) + */ +#define PBCR2 PFC_PBCR2 +#define PB7MD1 0x8000 +#define PB7MD0 0x4000 +#define PB6MD1 0x2000 +#define PB6MD0 0x1000 +#define PB5MD1 0x0800 +#define PB5MD0 0x0400 +#define PB4MD1 0x0200 +#define PB4MD0 0x0100 +#define PB3MD1 0x0080 +#define PB3MD0 0x0040 +#define PB2MD1 0x0020 +#define PB2MD0 0x0010 +#define PB1MD1 0x0008 +#define PB1MD0 0x0004 +#define PB0MD1 0x0002 +#define PB0MD0 0x0001 + +#define PB7MD PB7MD1|PB7MD0 +#define PB6MD PB6MD1|PB6MD0 +#define PB5MD PB5MD1|PB5MD0 +#define PB4MD PB4MD1|PB4MD0 +#define PB3MD PB3MD1|PB3MD0 +#define PB2MD PB2MD1|PB2MD0 +#define PB1MD PB1MD1|PB1MD0 +#define PB0MD PB0MD1|PB0MD0 + +#endif /* _sh7_pfc_h */ diff --git a/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h new file mode 100644 index 0000000000..cf33c0ebdd --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h @@ -0,0 +1,91 @@ +/* + * Bit values for the serial control registers of the Hitachi SH704X + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _sh7_sci_h +#define _sh7_sci_h + +#include + +/* + * Serial mode register bits + */ + +#define SCI_SYNC_MODE 0x80 +#define SCI_SEVEN_BIT_DATA 0x40 +#define SCI_PARITY_ON 0x20 +#define SCI_ODD_PARITY 0x10 +#define SCI_STOP_BITS_2 0x08 +#define SCI_ENABLE_MULTIP 0x04 +#define SCI_PHI_64 0x03 +#define SCI_PHI_16 0x02 +#define SCI_PHI_4 0x01 +#define SCI_PHI_0 0x00 + +/* + * Serial register offsets, relative to SCI0_SMR or SCI1_SMR + */ + +#define SCI_SMR 0x00 +#define SCI_BRR 0x01 +#define SCI_SCR 0x02 +#define SCI_TDR 0x03 +#define SCI_SSR 0x04 +#define SCI_RDR 0x05 + +/* + * Serial control register bits + */ +#define SCI_TIE 0x80 /* Transmit interrupt enable */ +#define SCI_RIE 0x40 /* Receive interrupt enable */ +#define SCI_TE 0x20 /* Transmit enable */ +#define SCI_RE 0x10 /* Receive enable */ +#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ +#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ +#define SCI_CKE1 0x02 /* Clock enable 1 */ +#define SCI_CKE0 0x01 /* Clock enable 0 */ + +/* + * Serial status register bits + */ +#define SCI_TDRE 0x80 /* Transmit data register empty */ +#define SCI_RDRF 0x40 /* Receive data register full */ +#define SCI_ORER 0x20 /* Overrun error */ +#define SCI_FER 0x10 /* Framing error */ +#define SCI_PER 0x08 /* Parity error */ +#define SCI_TEND 0x04 /* Transmit end */ +#define SCI_MPB 0x02 /* Multiprocessor bit */ +#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ + +/* + * INTC Priority Settings + */ + +#define SCI0_IPMSK 0x00F0 +#define SCI0_LOWIP 0x0010 +#define SCI1_IPMSK 0x000F +#define SCI1_LOWIP 0x0001 + +#endif /* _sh7_sci_h */ diff --git a/c/src/lib/libcpu/sh/sh7045/null/Makefile.in b/c/src/lib/libcpu/sh/sh7045/null/Makefile.in new file mode 100644 index 0000000000..94b08d5a73 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/Makefile.in @@ -0,0 +1,70 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/sh7045/null + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +PGM = ${ARCH}/null.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = open close read write init cntrl +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .s +S_PIECES = +S_FILES = $(S_PIECES:%=%.s) +S_O_FILES = $(S_FILES:%.s=${ARCH}/%.o) + +SRCS = $(DOCS) $(C_FILES) $(H_FILES) +OBJS = $(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libcpu/sh/sh7045/null/close.c b/c/src/lib/libcpu/sh/sh7045/null/close.c new file mode 100644 index 0000000000..cb5ac8cd65 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/close.c @@ -0,0 +1,38 @@ +/* null_close + * + * This routine is the null device driver close routine. + * + * Derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * Input parameters: + * major - device major number + * minor - device minor number + * pargb - pointer to close parameter block + * + * Output parameters: + * rval - NULL_SUCCESSFUL + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +rtems_device_driver null_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + return NULL_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/null/cntrl.c b/c/src/lib/libcpu/sh/sh7045/null/cntrl.c new file mode 100644 index 0000000000..cafc714279 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/cntrl.c @@ -0,0 +1,38 @@ +/* null_control + * + * This routine is the null device driver control routine. + * + * Derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * Input parameters: + * major - device major number + * minor - device minor number + * pargp - pointer to cntrl parameter block + * + * Output parameters: + * rval - NULL_SUCCESSFUL + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +rtems_device_driver null_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + return NULL_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/null/init.c b/c/src/lib/libcpu/sh/sh7045/null/init.c new file mode 100644 index 0000000000..dcc1800f6b --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/init.c @@ -0,0 +1,53 @@ +/* null_initialize + * + * This routine is the null device driver init routine. + * + * Derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * Input parameters: + * major - device major number + * minor - device minor number + * pargp - pointer to parameter block + * + * Output parameters: + * rval - NULL_SUCCESSFUL + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +rtems_unsigned32 NULL_major; + +rtems_device_driver null_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_device_driver status ; + + status = rtems_io_register_name( + "/dev/null", + major, + (rtems_device_minor_number) 0 + ); + + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred(status); + + NULL_major = major; + + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/null/open.c b/c/src/lib/libcpu/sh/sh7045/null/open.c new file mode 100644 index 0000000000..352f4b981e --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/open.c @@ -0,0 +1,38 @@ +/* null_open + * + * This routine is the null device driver open routine. + * + * Derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * Input parameters: + * major - device major number + * minor - device minor number + * pargb - pointer to open parameter block + * + * Output parameters: + * rval - NULL_SUCCESSFUL + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +rtems_device_driver null_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + return NULL_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/null/read.c b/c/src/lib/libcpu/sh/sh7045/null/read.c new file mode 100644 index 0000000000..895ba0c7f4 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/read.c @@ -0,0 +1,38 @@ +/* null_read + * + * This routine is the null device driver read routine. + * + * Derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * Input parameters: + * major - device major number + * minor - device minor number + * pargp - pointer to read parameter block + * + * Output parameters: + * rval - NULL_SUCCESSFUL + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +rtems_device_driver null_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + return NULL_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/null/write.c b/c/src/lib/libcpu/sh/sh7045/null/write.c new file mode 100644 index 0000000000..d9c4da434b --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/null/write.c @@ -0,0 +1,44 @@ +/* null_write + * + * This routine is the null device driver write routine. + * + * Derived from rtems' stub driver. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * Input parameters: + * major - device major number + * minor - device minor number + * pargp - pointer to write parameter block + * + * Output parameters: + * rval - NULL_SUCCESSFUL + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +#include + +rtems_device_driver null_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) pargp ; + + rw_args->bytes_moved = rw_args->count ; + + return NULL_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/sh/sh7045/sci/Makefile.in b/c/src/lib/libcpu/sh/sh7045/sci/Makefile.in new file mode 100644 index 0000000000..2548c0b478 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/sci/Makefile.in @@ -0,0 +1,71 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/sh7045/sci + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +PGM = ${ARCH}/sci.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = sci +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .s +S_PIECES = +S_FILES = $(S_PIECES:%=%.s) +S_O_FILES = $(S_FILES:%.s=${ARCH}/%.o) + +SRCS = $(C_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by +# libbsp/sh/BSP/wrapup/Makefile +install: all + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libcpu/sh/sh7045/sci/sci.c b/c/src/lib/libcpu/sh/sh7045/sci/sci.c new file mode 100644 index 0000000000..4a50abc803 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/sci/sci.c @@ -0,0 +1,384 @@ +/* + * /dev/sci[0|1] for Hitachi SH 704X + * + * The SH doesn't have a designated console device. Therefore we "alias" + * another device as /dev/console and revector all calls to /dev/console + * to this device. + * + * This approach is similar to installing a sym-link from one device to + * another device. If rtems once will support sym-links for devices files, + * this implementation could be dropped. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect sh7045 processor: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +struct scidev_t { + char * name ; + rtems_device_minor_number minor ; + unsigned short opened ; + tcflag_t cflags ; +} sci_device[2] = +{ + { "/dev/sci0", 0, 0, B9600 | CS8 }, + { "/dev/sci1", 0, 0, B9600 | CS8 } +} ; + +/* local data structures maintain hardware configuration */ +extern int _sci_get_brparms( + tcflag_t cflag, + unsigned char *smr, + unsigned char *brr ); + +#if UNUSED +static sci_setup_t sio_param[2]; +#endif + +/* local functions operate SCI ports 0 and 1 */ +/* called from polling routines or ISRs */ +rtems_boolean wrtSCI0(unsigned char ch) +{ + unsigned8 temp; + rtems_boolean result=FALSE; + + if ((read8(SCI_SSR0) & SCI_TDRE) != 0x00) { + /* Write the character to the TDR */ + write8(ch, SCI_TDR0); + /* Clear the TDRE bit */ + temp = read8(SCI_SSR0) & ~SCI_TDRE; + write8(temp, SCI_SSR0); + result = TRUE; + } + return result; +} /* wrtSCI0 */ + +rtems_boolean wrtSCI1(unsigned char ch) +{ + unsigned8 temp; + rtems_boolean result=FALSE; + + if ((read8(SCI_SSR1) & SCI_TDRE) != 0x00) { + /* Write the character to the TDR */ + write8(ch, SCI_TDR1); + /* Clear the TDRE bit */ + temp = read8(SCI_SSR1) & ~SCI_TDRE; + write8(temp, SCI_SSR1); + result = TRUE; + } + return result; +} /* wrtSCI1 */ + +/* polled output steers byte to selected port */ +void sh_sci_outbyte_polled( + rtems_device_minor_number minor, + char ch ) +{ + if (minor == 0) /* blocks until port ready */ + while (wrtSCI0(ch) != TRUE); /* SCI0*/ + else + while (wrtSCI1(ch) != TRUE); /* SCI1*/ +} /* sh_sci_outbyte_polled */ + +/* Initial version calls polled output driver and blocks */ +void outbyte( + rtems_device_minor_number minor, + char ch) +{ + sh_sci_outbyte_polled(minor, (unsigned char)ch); +} /* outbyte */ + +rtems_boolean rdSCI0(unsigned char *ch) +{ + unsigned8 temp; + rtems_boolean result=FALSE; + + if ((read8(SCI_SSR0) & SCI_RDRF) != 0x00) { + /* Write the character to the TDR */ + write8(*ch, SCI_RDR0); + /* Clear the TDRE bit */ + temp = read8(SCI_SSR0) & ~SCI_RDRF; + write8(temp, SCI_SSR0); + result = TRUE; + } + return result; +} /* rdSCI0 */ + +rtems_boolean rdSCI1(unsigned char *ch) +{ + unsigned8 temp; + rtems_boolean result=FALSE; + + if ((read8(SCI_SSR1) & SCI_RDRF) != 0x00) { + /* Write the character to the TDR */ + write8(*ch, SCI_RDR1); + /* Clear the TDRE bit */ + temp= read8(SCI_SSR1) & ~SCI_RDRF; + write8(temp, SCI_SSR1); + result = TRUE; + } + return result; +} /* rdSCI1 */ + + +/* initial version pulls byte from selected port */ +char sh_sci_inbyte_polled( + rtems_device_minor_number minor ) +{ + char ch; + + if (minor == 0) /* blocks until char.ready */ + while (rdSCI0(&ch) != TRUE); /* SCI0 */ + else + while (rdSCI1(&ch) != TRUE); /* SCI1 */ + return ch; +} /* sh_sci_inbyte_polled */ + +/* Initial version calls polled input driver */ +char inbyte( + rtems_device_minor_number minor ) +{ + char ch; + + ch = sh_sci_inbyte_polled(minor); + return ch; +} /* inbyte */ + + +/* sh_sci_initialize + * + * This routine initializes the sh_sci IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver sh_sci_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg ) +{ + int a; + unsigned16 temp16; + rtems_device_driver status ; + + /* register devices */ + for ( a = 0 ; a < 2 ; a++ ) + { + status = rtems_io_register_name( + sci_device[a].name, + major, + sci_device[a].minor ); + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred(status); + } + + /* default hardware setup */ + + /* general setup */ + temp16 = read16(PFC_PECR1) | 0x0800; /* General I/O except pin 13 (reset) */ + write16(temp16, PFC_PECR1); + write16(0x00, PFC_PECR2); /* All I/O lines bits 7-0 */ + temp16 = read16(PFC_PEIOR) | 0x0020; /* P5 to out, all other pins in */ + write16(temp16, PFC_PEIOR); + + temp16 = read16(PFC_PACRL2) | 0x0145; /* PFC - pins for Tx0-1, Rx0-1 */ + write16(temp16, PFC_PACRL2); + + return RTEMS_SUCCESSFUL; +} + + +/* + * Open entry point + */ + +rtems_device_driver sh_sci_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg ) +{ + unsigned8 temp8; + unsigned char smr ; + unsigned char brr ; + + unsigned a ; + + /* device already opened */ + if ( sci_device[minor].opened > 0 ) + { + sci_device[minor].opened++ ; + + return RTEMS_SUCCESSFUL ; + } + + /* retrieve brr and smr values */ + _sci_get_brparms( sci_device[minor].cflags, &smr, &brr ); + + if (minor == 0) { + write8(0x00, SCI_SCR0); /* Clear SCR */ + write8(smr, SCI_SMR0); /* Clear SMR */ + write8(brr, SCI_BRR0); /* Default 9600 baud rate */ +#if 0 + write8(0x1F, SCI_BRR0); /* 28800 baud */ +#endif +/* FIXME: Will get optimized away */ + for(a=0;a<10000L;a++); /* One bit delay */ + write8(0x30, SCI_SCR0); /* Enable clock output */ + temp8 = read8(SCI_RDR0); /* Clear out old input */ + + } else { + write8(0x00, SCI_SCR1); /* Clear SCR */ + write8(smr, SCI_SMR1); /* Clear SMR */ + write8(brr, SCI_BRR1); /* Default 9600 baud rate */ +#if 0 + write8(0x1F, SCI_BRR1); /* 28800 baud */ +#endif +/* FIXME: Will get optimized away */ + for(a=0;a<10000L;a++); /* One bit delay */ + write8(0x30, SCI_SCR1); /* Enable clock output */ + temp8 = read8(SCI_RDR1); /* Clear out old input */ + } + + sci_device[minor].opened++ ; + + return RTEMS_SUCCESSFUL ; +} + +/* + * Close entry point + */ + +rtems_device_driver sh_sci_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + /* FIXME: Incomplete */ + if ( sci_device[minor].opened > 0 ) + sci_device[minor].opened-- ; + else + return RTEMS_INVALID_NUMBER ; + + return RTEMS_SUCCESSFUL ; +} + +/* + * read bytes from the serial port. We only have stdin. + */ + +rtems_device_driver sh_sci_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + rtems_libio_rw_args_t *rw_args; + char *buffer; + int maximum; + int count = 0; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + buffer[ count ] = inbyte(minor); + if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { + buffer[ count++ ] = '\n'; + break; + } + } + + rw_args->bytes_moved = count; + return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; +} + +/* + * write bytes to the serial port. Stdout and stderr are the same. + */ + +rtems_device_driver sh_sci_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + int count; + int maximum; + rtems_libio_rw_args_t *rw_args; + char *buffer; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + if ( buffer[ count ] == '\n') { + outbyte(minor, '\r'); + } + outbyte( minor, buffer[ count ] ); + } + + rw_args->bytes_moved = maximum; + return 0; +} + +/* + * IO Control entry point + */ + +rtems_device_driver sh_sci_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + /* Not yet supported */ + return RTEMS_SUCCESSFUL ; +} diff --git a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c index 42764f6eb1..192c2f43d2 100644 --- a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c +++ b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c @@ -41,10 +41,17 @@ #include #include #include -#include -#include #include -#include + +#if defined(sh7032) +#include +#include +#elif defined (sh7045) +#include +#include +#endif + +#include /* from cpu_isps.c */ extern proc_ptr _Hardware_isr_Table[]; diff --git a/c/src/lib/libcpu/sh/sh7045/timer/Makefile.in b/c/src/lib/libcpu/sh/sh7045/timer/Makefile.in new file mode 100644 index 0000000000..8bf33bee32 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/timer/Makefile.in @@ -0,0 +1,71 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/sh7045/timer + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@ + +PGM = ${ARCH}/timer.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = timer +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .s +S_PIECES = +S_FILES = $(S_PIECES:%=%.s) +S_O_FILES = $(S_FILES:%.s=${ARCH}/%.o) + +SRCS = $(C_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by +# libbsp/sh/BSP/Makefile +install: all + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libcpu/sh/sh7045/timer/timer.c b/c/src/lib/libcpu/sh/sh7045/timer/timer.c new file mode 100644 index 0000000000..029c0bec94 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/timer/timer.c @@ -0,0 +1,208 @@ +/* + * timer for the Hitachi SH 704X + * + * This file manages the benchmark timer used by the RTEMS Timing Test + * Suite. Each measured time period is demarcated by calls to + * Timer_initialize() and Read_timer(). Read_timer() usually returns + * the number of microseconds since Timer_initialize() exitted. + * + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include + +#include +#include + +/* + * We use a Phi/4 timer + */ +#define SCALE (Timer_MHZ/4) + +#define MTU1_STARTMASK 0xfd +#define MTU1_SYNCMASK 0xfd +#define MTU1_MODEMASK 0xc0 +#define MTU1_TCRMASK 0x01 +#define MTU1_TIORMASK 0x88 +#define MTU1_STAT_MASK 0xf8 +#define MTU1_TIERMASK 0xfc +#define IPRC_MTU1_MASK 0xfff0 + +#ifndef MTU1_PRIO +#define MTU1_PRIO 15 +#endif + +#define MTU1_VECTOR 86 + +rtems_isr timerisr(); + +static rtems_unsigned32 Timer_interrupts; + +rtems_boolean Timer_driver_Find_average_overhead; + +static rtems_unsigned32 Timer_MHZ ; + +void Timer_initialize( void ) +{ + rtems_unsigned8 temp8; + rtems_unsigned16 temp16; + rtems_unsigned32 level; + rtems_isr *ignored; + + Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ; + + /* + * Timer has never overflowed. This may not be necessary on some + * implemenations of timer but .... + */ + + Timer_interrupts /* .i */ = 0; + _CPU_ISR_Disable( level); + + /* + * Somehow start the timer + */ + /* stop Timer 1 */ + temp8 = read8( MTU_TSTR) & MTU1_STARTMASK; + write8( temp8, MTU_TSTR); + + /* initialize counter 1 */ + write16( 0, MTU_TCNT1); + + /* Timer 1 is independent of other timers */ + temp8 = read8( MTU_TSYR) & MTU1_SYNCMASK; + write8( temp8, MTU_TSYR); + + /* Timer 1, normal mode */ + temp8 = read8( MTU_TMDR1) & MTU1_MODEMASK; + write8( temp8, MTU_TMDR1); + + /* x0000000 + * |||||+++--- Internal Clock + * |||++------ Count on rising edge + * |++-------- disable TCNT clear + * +---------- don`t care + */ + write8( MTU1_TCRMASK, MTU_TCR1); + + /* gra and grb are not used */ + write8( MTU1_TIORMASK, MTU_TIOR1); + + /* reset all status flags */ + temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK; + write8( temp8, MTU_TSR1); + + /* enable overflow interrupt */ + write8( MTU1_TIERMASK, MTU_TIER1); + + /* set interrupt priority */ + temp16 = read16( INTC_IPRC) & IPRC_MTU1_MASK; + temp16 |= MTU1_PRIO; + write16( temp16, INTC_IPRC); + + /* initialize ISR */ + _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored ); + _CPU_ISR_Enable( level); + + /* start timer 1 */ + temp8 = read8( MTU_TSTR) | ~MTU1_STARTMASK; + write8( temp8, MTU_TSTR); +} + +/* + * The following controls the behavior of Read_timer(). + * + * AVG_OVERHEAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */ + /* (Y countdowns) to start/stop the timer. */ + /* This value is in microseconds. */ +#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ + +int Read_timer( void ) +{ + rtems_unsigned32 clicks; + rtems_unsigned32 total ; + /* + * Read the timer and see how many clicks it has been since we started. + */ + + + clicks = read16( MTU_TCNT1); /* XXX: read some HW here */ + + /* + * Total is calculated by taking into account the number of timer overflow + * interrupts since the timer was initialized and clicks since the last + * interrupts. + */ + + total = clicks + Timer_interrupts * 65536 ; + + if ( Timer_driver_Find_average_overhead ) + return total / SCALE; /* in XXX microsecond units */ + else + { + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + /* + * Somehow convert total into microseconds + */ + return (total / SCALE - AVG_OVERHEAD) ; + } +} + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ + +rtems_status_code Empty_function( void ) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} + +/* Timer 1 is used */ + +#pragma interrupt +void timerisr( void ) +{ + unsigned8 temp8; + + /* reset the flags of the status register */ + temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK; + write8( temp8, MTU_TSR1); + + Timer_interrupts += 1; +} diff --git a/cpukit/score/cpu/sh/cpu.c b/cpukit/score/cpu/sh/cpu.c index cc07552cf0..06f7b9c3d7 100644 --- a/cpukit/score/cpu/sh/cpu.c +++ b/cpukit/score/cpu/sh/cpu.c @@ -30,7 +30,7 @@ #include -/* referenced in start.s */ +/* referenced in start.S */ extern proc_ptr vectab[] ; proc_ptr vectab[256] ; diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h index 8a18848f09..dedd11c055 100644 --- a/cpukit/score/cpu/sh/rtems/score/cpu.h +++ b/cpukit/score/cpu/sh/rtems/score/cpu.h @@ -377,6 +377,7 @@ typedef struct { void * (*stack_allocate_hook)( unsigned32 ); void (*stack_free_hook)( void* ); /* end of fields required on all CPUs */ + unsigned32 clicks_per_second ; /* cpu frequency in Hz */ } rtems_cpu_table; /* @@ -388,8 +389,9 @@ typedef struct { * Macros to access SH specific additions to the CPU Table */ -/* There are no CPU specific additions to the CPU Table for this port. */ - +#define rtems_cpu_configuration_get_clicks_per_second() \ + (_CPU_Table.clicks_per_second) + /* * This variable is optional. It is used on CPUs on which it is difficult * to generate an "uninitialized" FP context. It is filled in by @@ -434,6 +436,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ /* XXX: if needed, put more variables here */ +SCORE_EXTERN void CPU_delay( unsigned32 microseconds ); /* * The size of the floating point context area. On some CPUs this @@ -637,7 +640,7 @@ SCORE_EXTERN void _CPU_Context_Initialize( * * Other models include (1) not doing anything, and (2) putting * a "null FP status word" in the correct place in the FP context. - * SH has no FPU !!!!!!!!!!!! + * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. */ #define _CPU_Context_Initialize_fp( _destination ) \ diff --git a/cpukit/score/cpu/sh/rtems/score/sh.h b/cpukit/score/cpu/sh/rtems/score/sh.h index 96e10bfb1b..45228c5fe0 100644 --- a/cpukit/score/cpu/sh/rtems/score/sh.h +++ b/cpukit/score/cpu/sh/rtems/score/sh.h @@ -42,7 +42,16 @@ extern "C" { #if defined(sh7032) #define CPU_MODEL_NAME "SH 7032" +#define SH_HAS_FPU 0 + +/* + * If the following macro is set to 0 there will be no software irq stack + */ +#define SH_HAS_SEPARATE_STACKS 1 + +#elif defined (sh7045) +#define CPU_MODEL_NAME "SH 7045" #define SH_HAS_FPU 0 /* diff --git a/make/custom/gensh1.cfg b/make/custom/gensh1.cfg index b5d98630e2..5dc58d8e82 100644 --- a/make/custom/gensh1.cfg +++ b/make/custom/gensh1.cfg @@ -8,7 +8,7 @@ # $Id$ # -MHZ=20 +HZ=20000000 include $(RTEMS_ROOT)/make/custom/default.cfg @@ -20,19 +20,17 @@ RTEMS_BSP_FAMILY=gensh1 # BSP specific preprocessor flags. # These should only be used in BSP dependent directories. -BSP_CPPFLAGS=-DMHZ=$(MHZ) +BSP_CPPFLAGS=-DHZ=$(HZ) # # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. # -# HACK: We have to append BSP_CPPFLAGS to CPU_CFLAGS, because -# per BSP and per CPU CPPFLAGS are not (yet?) supported -CPU_CFLAGS=-m1 $(BSP_CPPFLAGS) -# CPU_CFLAGS=-m1 +CPU_CFLAGS=-m1 # debug flags: typically none, but we use -O1 as it produces better code -CFLAGS_DEBUG_V = -O1 +# CFLAGS_DEBUG_V = -O1 +CFLAGS_DEBUG_V = # optimize flag: typically -0, could use -O4 or -fast # -O4 is ok for RTEMS @@ -75,8 +73,8 @@ define make-exe endef else define make-exe - $(CC) $(CPPFLAGS) -Wl,-Map,$(basename $@).map \ - $(CFLAGS) $(CFLAGS_LD) -o $(basename $@).exe \ + $(LINK.c) -Wl,-Map,$(basename $@).map \ + $(LDLIBS) -o $(basename $@).exe \ $(LINK_OBJS) $(LINK_LIBS) $(NM) -n $(basename $@).exe > $(basename $@).num $(SIZE) $(basename $@).exe diff --git a/make/custom/gensh2.cfg b/make/custom/gensh2.cfg new file mode 100644 index 0000000000..a03f7a950c --- /dev/null +++ b/make/custom/gensh2.cfg @@ -0,0 +1,86 @@ +# +# gensh2.cfg +# +# default configuration for Hitachi sh1 processors +# +# Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) +# +# $Id$ +# + +HZ:=29491200 + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU=sh +RTEMS_CPU_MODEL=sh7045 + +# This is the actual bsp directory used during the build process. +RTEMS_BSP_FAMILY=gensh2 + +# BSP specific preprocessor flags. +# These should only be used in BSP dependent directories. +BSP_CPPFLAGS=-DHZ=$(HZ) + +# +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +# +CPU_CFLAGS= -m2 + +# debug flags: typically none, but we use -O1 as it produces better code +CFLAGS_DEBUG_V = -O1 + +# optimize flag: typically -0, could use -O4 or -fast +# -O4 is ok for RTEMS +CFLAGS_OPTIMIZE_V = -O4 + +# This section makes the target dependent options file. + +# NDEBUG (C library) +# if defined asserts do not generate code. This is commonly used +# as a command line option. +# +# RTEMS_TEST_NO_PAUSE (RTEMS tests) +# do not pause between screens of output in the rtems tests +# +# RTEMS_DEBUG (RTEMS) +# If defined, debug checks in RTEMS and support library code are enabled. +# +# STANDALONE_EVB +# This switch compiles code to jump-start from FLASH, without a monitor +# + +define make-target-options + @echo "/* #define NDEBUG 1 */ " >>$@ + @echo "#define RTEMS_TEST_NO_PAUSE 1" >>$@ + @echo "#define RTEMS_TEST_IO_STREAM 1" >>$@ + @echo "/* #define STANDALONE_EVB 1 */" >>$@ + @echo "/* #define RTEMS_DEBUG 1 */" >>$@ +endef + + +# The following are definitions of make-exe which will work using ld as +# is currently required. It is expected that as of gcc 2.8, the end user +# will be able to override parts of the compilers specs and link using gcc. + +ifeq ($(RTEMS_USE_GCC272),yes) +define make-exe + $(LD) $(LDFLAGS) -N -e _start \ + -T$(PROJECT_RELEASE)/lib/linkcmds\ + -o $(basename $@).exe \ + $(START_FILE) $(LINK_OBJS) --start-group $(LINK_LIBS) --end-group + $(NM) -n $(basename $@).exe > $(basename $@).num + $(SIZE) $(basename $@).exe +endef +else +define make-exe + $(LINK.c) -Wl,-Map,$(basename $@).map \ + $(LDLIBS) -o $(basename $@).exe \ + $(LINK_OBJS) $(LINK_LIBS) + $(NM) -n $(basename $@).exe > $(basename $@).num + $(SIZE) $(basename $@).exe +endef +endif + +# Miscellaneous additions go here -- cgit v1.2.3