From 3ad3849a899a34e83ed217e708de0425199a0c9e Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 22 Sep 2017 13:15:56 +0200 Subject: bsp/imx: Add register headers Update #3090. --- c/src/lib/libbsp/arm/imx/Makefile.am | 2 + .../arm/imx/include/arm/freescale/imx/imx_gpcreg.h | 162 +++++++++++++++++++++ .../arm/imx/include/arm/freescale/imx/imx_srcreg.h | 104 +++++++++++++ c/src/lib/libbsp/arm/imx/preinstall.am | 8 + 4 files changed, 276 insertions(+) create mode 100644 c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_gpcreg.h create mode 100644 c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_srcreg.h diff --git a/c/src/lib/libbsp/arm/imx/Makefile.am b/c/src/lib/libbsp/arm/imx/Makefile.am index da0b12bacf..20737ba7d4 100644 --- a/c/src/lib/libbsp/arm/imx/Makefile.am +++ b/c/src/lib/libbsp/arm/imx/Makefile.am @@ -41,6 +41,8 @@ include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h include_arm_freescale_imx_HEADERS = include_arm_freescale_imx_HEADERS += include/arm/freescale/imx/imx_ccmvar.h +include_arm_freescale_imx_HEADERS += include/arm/freescale/imx/imx_gpcreg.h +include_arm_freescale_imx_HEADERS += include/arm/freescale/imx/imx_srcreg.h include_arm_freescale_imx_HEADERS += include/arm/freescale/imx/imx_uartreg.h ############################################################################### diff --git a/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_gpcreg.h b/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_gpcreg.h new file mode 100644 index 0000000000..924166c70d --- /dev/null +++ b/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_gpcreg.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_GPCREG_H +#define IMX_GPCREG_H + +#include + +typedef struct { + uint32_t lpcr_a7_bsc; + uint32_t lpcr_a7_ad; + uint32_t lpcr_m4; + uint32_t reserved_0c[2]; + uint32_t slpcr; + uint32_t reserved_18[2]; + uint32_t mlpcr; + uint32_t pgc_ack_sel_a7; + uint32_t pgc_ack_sel_m4; + uint32_t misc; + uint32_t imr1_core0_a7; + uint32_t imr2_core0_a7; + uint32_t imr3_core0_a7; + uint32_t imr4_core0_a7; + uint32_t imr1_core1_a7; + uint32_t imr2_core1_a7; + uint32_t imr3_core1_a7; + uint32_t imr4_core1_a7; + uint32_t imr1_m4; + uint32_t imr2_m4; + uint32_t imr3_m4; + uint32_t imr4_m4; + uint32_t reserved_60[4]; + uint32_t isr1_a7; + uint32_t isr2_a7; + uint32_t isr3_a7; + uint32_t isr4_a7; + uint32_t isr1_m4; + uint32_t isr2_m4; + uint32_t isr3_m4; + uint32_t isr4_m4; + uint32_t reserved_90[8]; + uint32_t slt0_cfg; + uint32_t slt1_cfg; + uint32_t slt2_cfg; + uint32_t slt3_cfg; + uint32_t slt4_cfg; + uint32_t slt5_cfg; + uint32_t slt6_cfg; + uint32_t slt7_cfg; + uint32_t slt8_cfg; + uint32_t slt9_cfg; + uint32_t reserved_d8[5]; + uint32_t pgc_cpu_mapping; +#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2) +#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1) +#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0) +#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4) +#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3) +#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2) +#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1) +#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0) + uint32_t cpu_pgc_sw_pup_req; + uint32_t reserved_f4; + uint32_t pu_pgc_sw_pup_req; + uint32_t cpu_pgc_sw_pdn_req; + uint32_t reserved_100; + uint32_t pu_pgc_sw_pdn_req; + uint32_t reserved_108[10]; + uint32_t cpu_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status0; + uint32_t a7_mix_pgc_pup_status1; + uint32_t a7_mix_pgc_pup_status2; + uint32_t m4_mix_pgc_pup_status0; + uint32_t m4_mix_pgc_pup_status1; + uint32_t m4_mix_pgc_pup_status2; + uint32_t a7_pu_pgc_pup_status0; + uint32_t a7_pu_pgc_pup_status1; + uint32_t a7_pu_pgc_pup_status2; + uint32_t m4_pu_pgc_pup_status0; + uint32_t m4_pu_pgc_pup_status1; + uint32_t m4_pu_pgc_pup_status2; + uint32_t reserved_164[3]; + uint32_t cpu_pgc_pdn_status1; + uint32_t reserved_174[6]; + uint32_t a7_pu_pgc_pdn_status0; + uint32_t a7_pu_pgc_pdn_status1; + uint32_t a7_pu_pgc_pdn_status2; + uint32_t m4_pu_pgc_pdn_status0; + uint32_t m4_pu_pgc_pdn_status1; + uint32_t m4_pu_pgc_pdn_status2; + uint32_t reserved_1a4[3]; + uint32_t a7_mix_pdn_flg; + uint32_t a7_pu_pdn_flg; + uint32_t m4_mix_pdn_flg; + uint32_t m4_pu_pdn_flg; +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29) +#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21) +#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6) +#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6) +#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0) + uint32_t reserved_1c0[400]; + uint32_t pgc_a7core0_ctrl; + uint32_t pgc_a7core0_pupscr; + uint32_t pgc_a7core0_pdnscr; + uint32_t pgc_a7core0_sr; + uint32_t reserved_810[12]; + uint32_t pgc_a7core1_ctrl; + uint32_t pgc_a7core1_pupscr; + uint32_t pgc_a7core1_pdnscr; + uint32_t pgc_a7core1_sr; + uint32_t reserved_850[12]; + uint32_t pgc_a7scu_ctrl; + uint32_t pgc_a7scu_pupscr; + uint32_t pgc_a7scu_pdnscr; + uint32_t pgc_a7scu_sr; + uint32_t pgc_scu_auxsw; + uint32_t reserved_894[11]; + uint32_t pgc_mix_ctrl; + uint32_t pgc_mix_pupscr; + uint32_t pgc_mix_pdnscr; + uint32_t pgc_mix_sr; + uint32_t reserved_8d0[12]; + uint32_t pgc_mipi_ctrl; + uint32_t pgc_mipi_pupscr; + uint32_t pgc_mipi_pdnscr; + uint32_t pgc_mipi_sr; + uint32_t reserved_910[12]; + uint32_t pgc_pcie_ctrl; + uint32_t pgc_pcie_pupscr; + uint32_t pgc_pcie_pdnscr; + uint32_t pgc_pcie_sr; + uint32_t reserved_950[176]; + uint32_t pgc_mipi_auxsw; + uint32_t reserved_c14[15]; + uint32_t pgc_pcie_auxsw; + uint32_t reserved_c54[43]; + uint32_t pgc_hsic_ctrl; + uint32_t pgc_hsic_pupscr; + uint32_t pgc_hsic_pdnscr; + uint32_t pgc_hsic_sr; +} imx_gpc; + +#endif /* IMX_GPCREG_H */ diff --git a/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_srcreg.h b/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_srcreg.h new file mode 100644 index 0000000000..b5f3490b79 --- /dev/null +++ b/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_srcreg.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_SRCREG_H +#define IMX_SRCREG_H + +#include + +typedef struct { + uint32_t scr; +#define IMX_SRC_SCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_SCR_LOCK BSP_BIT32(30) +#define IMX_SRC_SCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_SCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_SCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_SCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_SCR_MASK_TEMPSENSE_RESET_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) + uint32_t a7rcr0; +#define IMX_SRC_A7RCR0_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR0_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR0_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR0_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR0_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR0_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR0_A7_L2RESET BSP_BIT32(21) +#define IMX_SRC_A7RCR0_A7_SOC_DBG_RESET BSP_BIT32(20) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST(val) BSP_FLD32(val, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define IMX_SRC_A7RCR0_MASK_WDOG1_RST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define IMX_SRC_A7RCR0_A7_ETM_RESET1 BSP_BIT32(13) +#define IMX_SRC_A7RCR0_A7_ETM_RESET0 BSP_BIT32(12) +#define IMX_SRC_A7RCR0_A7_DBG_RESET1 BSP_BIT32(9) +#define IMX_SRC_A7RCR0_A7_DBG_RESET0 BSP_BIT32(8) +#define IMX_SRC_A7RCR0_A7_CORE_RESET1 BSP_BIT32(5) +#define IMX_SRC_A7RCR0_A7_CORE_RESET0 BSP_BIT32(4) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET1 BSP_BIT32(1) +#define IMX_SRC_A7RCR0_A7_CORE_POR_RESET0 BSP_BIT32(0) + uint32_t a7rcr1; +#define IMX_SRC_A7RCR1_DOM_EN BSP_BIT32(31) +#define IMX_SRC_A7RCR1_LOCK BSP_BIT32(30) +#define IMX_SRC_A7RCR1_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_A7RCR1_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_A7RCR1_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_A7RCR1_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_A7RCR1_A7_CORE1_ENABLE BSP_BIT32(1) + uint32_t m4rcr; +#define IMX_SRC_M4RCR_DOM_EN BSP_BIT32(31) +#define IMX_SRC_M4RCR_LOCK BSP_BIT32(30) +#define IMX_SRC_M4RCR_DOMAIN3 BSP_BIT32(27) +#define IMX_SRC_M4RCR_DOMAIN2 BSP_BIT32(26) +#define IMX_SRC_M4RCR_DOMAIN1 BSP_BIT32(25) +#define IMX_SRC_M4RCR_DOMAIN0 BSP_BIT32(24) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION BSP_BIT32(9) +#define IMX_SRC_M4RCR_WDOG3_RST_OPTION_M4 BSP_BIT32(8) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST(val) BSP_FLD32(val, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_GET(reg) BSP_FLD32GET(reg, 4, 7) +#define IMX_SRC_M4RCR_MASK_WDOG3_RST_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define IMX_SRC_M4RCR_ENABLE_M4 BSP_BIT32(3) +#define IMX_SRC_M4RCR_SW_M4P_RST BSP_BIT32(2) +#define IMX_SRC_M4RCR_SW_M4C_RST BSP_BIT32(1) +#define IMX_SRC_M4RCR_SW_M4C_NON_SCLR_RST BSP_BIT32(0) + uint32_t reserved_10; + uint32_t ercr; + uint32_t reserved_18; + uint32_t hsicphy_rcr; + uint32_t usbophy1_rcr; + uint32_t usbophy2_rcr; + uint32_t mipiphy_rcr; + uint32_t pciephy_rcr; + uint32_t reserved_30[10]; + uint32_t sbmr1; + uint32_t srsr; + uint32_t reserved_60[2]; + uint32_t sisr; + uint32_t simr; + uint32_t sbmr2; + uint32_t gpr1; + uint32_t gpr2; + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t reserved_9c[985]; + uint32_t ddrc_rcr; +} imx_src; + +#endif /* IMX_SRCREG_H */ diff --git a/c/src/lib/libbsp/arm/imx/preinstall.am b/c/src/lib/libbsp/arm/imx/preinstall.am index 1f08be6c40..6b3d589f2b 100644 --- a/c/src/lib/libbsp/arm/imx/preinstall.am +++ b/c/src/lib/libbsp/arm/imx/preinstall.am @@ -135,6 +135,14 @@ $(PROJECT_INCLUDE)/arm/freescale/imx/imx_ccmvar.h: include/arm/freescale/imx/imx $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/arm/freescale/imx/imx_ccmvar.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/arm/freescale/imx/imx_ccmvar.h +$(PROJECT_INCLUDE)/arm/freescale/imx/imx_gpcreg.h: include/arm/freescale/imx/imx_gpcreg.h $(PROJECT_INCLUDE)/arm/freescale/imx/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/arm/freescale/imx/imx_gpcreg.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/arm/freescale/imx/imx_gpcreg.h + +$(PROJECT_INCLUDE)/arm/freescale/imx/imx_srcreg.h: include/arm/freescale/imx/imx_srcreg.h $(PROJECT_INCLUDE)/arm/freescale/imx/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/arm/freescale/imx/imx_srcreg.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/arm/freescale/imx/imx_srcreg.h + $(PROJECT_INCLUDE)/arm/freescale/imx/imx_uartreg.h: include/arm/freescale/imx/imx_uartreg.h $(PROJECT_INCLUDE)/arm/freescale/imx/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/arm/freescale/imx/imx_uartreg.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/arm/freescale/imx/imx_uartreg.h -- cgit v1.2.3