From 32c896092579feeee787209deb269f9c66c0081f Mon Sep 17 00:00:00 2001
From: Ralf Kirchner <ralf.kirchner@embedded-brains.de>
Date: Wed, 28 May 2014 14:47:03 +0200
Subject: bsp/altera-cyclone-v: Enable L2 cache for network driver

---
 c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c b/c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c
index d2f669a658..43c95cd723 100644
--- a/c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c
+++ b/c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c
@@ -40,6 +40,7 @@
 #include <bsp/alt_generalpurpose_io.h>
 #include <bsp/nocache-heap.h>
 #include "socal/alt_rstmgr.h"
+#include "socal/alt_sysmgr.h"
 #include "socal/hps.h"
 #include "socal/socal.h"
 #include <libchip/dwmac.h>
@@ -1080,9 +1081,21 @@ static int network_if_mem_free_nocache(
  */
 static int network_if_bus_setup( void *arg )
 {
+  volatile uint32_t reg = alt_read_word( ALT_SYSMGR_EMAC_L3MST_ADDR );
+
   (void) arg;
 
-  /* Nothing to be done */
+  reg &= ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK;
+  reg &= ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK;
+  reg |= ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(
+    ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC
+  );
+  reg |= ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(
+    ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC
+  );
+
+  alt_write_word( ALT_SYSMGR_EMAC_L3MST_ADDR, reg );
+
   return 0;
 }
 
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