From 2e2a41ecd99d17b379b2874cbd45d32b9430791e Mon Sep 17 00:00:00 2001
From: Christian Mauderer <Christian.Mauderer@embedded-brains.de>
Date: Fri, 28 Jul 2017 11:11:54 +0200
Subject: bsp/atsam: Add timing for RAM mt48lc16m16a2p-6a.

---
 c/src/lib/libbsp/arm/atsam/configure.ac           |  1 +
 c/src/lib/libbsp/arm/atsam/startup/sdram-config.c | 57 +++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/c/src/lib/libbsp/arm/atsam/configure.ac b/c/src/lib/libbsp/arm/atsam/configure.ac
index 8a4a2f2a7f..06a0b3a5e6 100644
--- a/c/src/lib/libbsp/arm/atsam/configure.ac
+++ b/c/src/lib/libbsp/arm/atsam/configure.ac
@@ -56,6 +56,7 @@ AC_ARG_ENABLE(
 [case "${enableval}" in
   is42s16100e-7bli) AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000 ;;
   is42s16320f-7bl) AC_DEFINE([ATSAM_SDRAM_IS42S16320F_7BL],[1],[SDRAM variant]) EXTSDRAM=0x04000000 ;;
+  mt48lc16m16a2p-6a) AC_DEFINE([ATSAM_SDRAM_MT48LC16M16A2P_6A],[1],[SDRAM variant]) EXTSDRAM=0x02000000 ;;
   *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;;
 esac],
 [AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000])
diff --git a/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c b/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c
index 135a2ccebf..a2f1158377 100644
--- a/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c
+++ b/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c
@@ -74,6 +74,63 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
       SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14))
 };
 
+#elif defined ATSAM_SDRAM_MT48LC16M16A2P_6A
+
+/*
+ * Refresh: 7.81 us
+ * TWR: 12 ns
+ * TRC_TRFC: 60 ns
+ * TRP: 15 ns
+ * TRCD: 18 ns
+ * TRAS: 42 ns
+ * TXSR: 67 ns
+ * TMRD: 2 clock cycles
+ */
+
+#if ATSAM_MCK == 60000000
+const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
+  .sdramc_tr = 0x1D4,
+  .sdramc_cr =
+      SDRAMC_CR_NC_COL9
+    | SDRAMC_CR_NR_ROW13
+    | SDRAMC_CR_NB_BANK4
+    | SDRAMC_CR_CAS_LATENCY3
+    | SDRAMC_CR_DBW
+    | SDRAMC_CR_TWR(3)
+    | SDRAMC_CR_TRC_TRFC(8)
+    | SDRAMC_CR_TRP(3)
+    | SDRAMC_CR_TRCD(3)
+    | SDRAMC_CR_TRAS(5)
+    | SDRAMC_CR_TXSR(9),
+  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
+  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
+      SDRAMC_CFR1_TMRD(2)
+};
+
+#elif ATSAM_MCK == 123000000
+const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
+  .sdramc_tr = 960,
+  .sdramc_cr =
+      SDRAMC_CR_NC_COL9
+    | SDRAMC_CR_NR_ROW13
+    | SDRAMC_CR_NB_BANK4
+    | SDRAMC_CR_CAS_LATENCY3
+    | SDRAMC_CR_DBW
+    | SDRAMC_CR_TWR(2)
+    | SDRAMC_CR_TRC_TRFC(8)
+    | SDRAMC_CR_TRP(2)
+    | SDRAMC_CR_TRCD(3)
+    | SDRAMC_CR_TRAS(6)
+    | SDRAMC_CR_TXSR(9),
+  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
+  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
+      SDRAMC_CFR1_TMRD(2)
+};
+
+#else /* ATSAM_MCK unknown */
+#error Please check SDRAM settings for this frequency.
+#endif
+
 #else
   #error SDRAM not supported.
 #endif
-- 
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