From 2dca2e62414b32cb59218ca689b990d0864403f0 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Sat, 23 Jan 2016 16:49:29 -0600 Subject: Obsolete and remove powerpc/mbx8xx closes #2545. --- c/ACKNOWLEDGEMENTS | 6 - c/src/lib/libbsp/powerpc/acinclude.m4 | 2 - c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am | 84 - c/src/lib/libbsp/powerpc/mbx8xx/README | 521 ------ c/src/lib/libbsp/powerpc/mbx8xx/bsp_specs | 13 - c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c | 83 - c/src/lib/libbsp/powerpc/mbx8xx/configure.ac | 112 -- c/src/lib/libbsp/powerpc/mbx8xx/console/console.c | 1116 ------------- c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c | 48 - c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c | 384 ----- .../lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h | 454 ----- c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h | 97 -- c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h | 527 ------ c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h | 366 ---- c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h | 63 - c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c | 347 ---- c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h | 184 --- .../powerpc/mbx8xx/make/custom/mbx821_001.cfg | 13 - .../powerpc/mbx8xx/make/custom/mbx821_002.cfg | 13 - .../powerpc/mbx8xx/make/custom/mbx821_002b.cfg | 17 - .../powerpc/mbx8xx/make/custom/mbx860_001b.cfg | 13 - .../powerpc/mbx8xx/make/custom/mbx860_002.cfg | 13 - .../powerpc/mbx8xx/make/custom/mbx860_005b.cfg | 16 - .../powerpc/mbx8xx/make/custom/mbx860_1b.cfg | 13 - .../libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc | 57 - c/src/lib/libbsp/powerpc/mbx8xx/network/network.c | 1743 -------------------- c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am | 95 -- c/src/lib/libbsp/powerpc/mbx8xx/start/start.S | 434 ----- c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c | 168 -- .../powerpc/mbx8xx/startup/bspstart.c.nocache | 107 -- c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c | 644 -------- c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds | 333 ---- .../lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c | 185 --- c/src/lib/libbsp/powerpc/mbx8xx/times-mbx821 | 187 --- c/src/lib/libbsp/powerpc/mbx8xx/times-mbx860 | 187 --- 35 files changed, 8645 deletions(-) delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/README delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/bsp_specs delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/configure.ac delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/console/console.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_001.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002b.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_001b.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_002.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_005b.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_1b.cfg delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/network/network.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/start/start.S delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c.nocache delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/times-mbx821 delete mode 100644 c/src/lib/libbsp/powerpc/mbx8xx/times-mbx860 diff --git a/c/ACKNOWLEDGEMENTS b/c/ACKNOWLEDGEMENTS index bfa5c7d7f0..4437ace6ec 100644 --- a/c/ACKNOWLEDGEMENTS +++ b/c/ACKNOWLEDGEMENTS @@ -142,12 +142,6 @@ The following persons/organizations have made contributions: numerous simulators. Many work with instruction set simulators in gdb. -+ Darlene Stewart and Charles Gauthier - of the Institute for Information Technology - for the National Research Council of Canada submitted the Motorola - MBX8XX BSP and consolidated libcpu support for the MPC860 and MPC821 - into MPC8XX. - + John Cotton and Charles Gauthier of the Institute for Information Technology for the National Research Council of Canada diff --git a/c/src/lib/libbsp/powerpc/acinclude.m4 b/c/src/lib/libbsp/powerpc/acinclude.m4 index cddd9a7309..4c83475dd8 100644 --- a/c/src/lib/libbsp/powerpc/acinclude.m4 +++ b/c/src/lib/libbsp/powerpc/acinclude.m4 @@ -10,8 +10,6 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR], AC_CONFIG_SUBDIRS([gen83xx]);; haleakala ) AC_CONFIG_SUBDIRS([haleakala]);; - mbx8xx ) - AC_CONFIG_SUBDIRS([mbx8xx]);; motorola_powerpc ) AC_CONFIG_SUBDIRS([motorola_powerpc]);; mpc55xxevb ) diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am b/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am deleted file mode 100644 index 27f2e95213..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am +++ /dev/null @@ -1,84 +0,0 @@ -ACLOCAL_AMFLAGS = -I ../../../../aclocal - -include $(top_srcdir)/../../../../automake/compile.am - -include_bspdir = $(includedir)/bsp - -dist_project_lib_DATA = bsp_specs - -include_HEADERS = include/bsp.h -include_HEADERS += ../../shared/include/tm27.h - -nodist_include_HEADERS = include/bspopts.h -nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h -DISTCLEANFILES = include/bspopts.h - -noinst_PROGRAMS = - -include_HEADERS += include/coverhd.h -include_bsp_HEADERS = include/mbx.h include/commproc.h include/8xx_immap.h \ - irq/irq.h \ - ../../shared/include/irq-generic.h \ - ../../shared/include/irq-info.h - -EXTRA_DIST = times-mbx821 times-mbx860 - -dist_project_lib_DATA += startup/linkcmds - -noinst_LIBRARIES = libbspstart.a -libbspstart_a_SOURCES = start/start.S -project_lib_DATA = start.$(OBJEXT) - -libbspstart_a_SOURCES += ../../powerpc/shared/start/rtems_crti.S -project_lib_DATA += rtems_crti.$(OBJEXT) - -noinst_LIBRARIES += libbsp.a -libbsp_a_SOURCES = - -# pclock -libbsp_a_SOURCES += clock/p_clock.c -# console -libbsp_a_SOURCES += console/console.c -# irq -libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c -libbsp_a_SOURCES += ../../shared/src/irq-generic.c -libbsp_a_SOURCES += ../../shared/src/irq-info.c -libbsp_a_SOURCES += ../../shared/src/irq-legacy.c -libbsp_a_SOURCES += ../../shared/src/irq-server.c -libbsp_a_SOURCES += ../../shared/src/irq-shell.c -libbsp_a_SOURCES += irq/irq.c -# ide -libbsp_a_SOURCES += ide/idecfg.c ide/pcmcia_ide.c -# startup -libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \ - ../../shared/bsppost.c ../../shared/bsppredriverhook.c \ - ../../shared/bspgetworkarea.c \ - startup/bspstart.c ../../shared/bootcard.c \ - startup/imbx8xx.c startup/mmutlbtab.c \ - ../../shared/sbrk.c ../../shared/gnatinstallhandler.c - -if HAS_NETWORKING -network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -noinst_PROGRAMS += network.rel -network_rel_SOURCES = network/network.c -network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS) -network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -endif - -libbsp_a_LIBADD = \ - ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \ - ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ - ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \ - ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \ - ../../../libcpu/@RTEMS_CPU@/mpc8xx/clock.rel \ - ../../../libcpu/@RTEMS_CPU@/mpc8xx/console-generic.rel \ - ../../../libcpu/@RTEMS_CPU@/mpc8xx/cpm.rel \ - ../../../libcpu/@RTEMS_CPU@/mpc8xx/mmu.rel \ - ../../../libcpu/@RTEMS_CPU@/mpc8xx/timer.rel - -if HAS_NETWORKING -libbsp_a_LIBADD += network.rel -endif - -include $(srcdir)/preinstall.am -include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/README b/c/src/lib/libbsp/powerpc/mbx8xx/README deleted file mode 100644 index 3d10f6709d..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/README +++ /dev/null @@ -1,521 +0,0 @@ -This is a README file for the MBX860/MBX821 port of RTEMS 4.5.0 - -Please send any comments, improvements, or bug reports to: - -Charles-Antoine Gauthier -charles.gauthier@nrc.ca - -or - -Darlene Stewart -Darlene.Stewart@nrc.ca - -Software Engineering Group -Institute for Information Technology -National Research Council of Canada -Ottawa, ON, K1A 0R6 -Canada - - -Disclaimer ----------- - -The National Research Council of Canada is distributing this RTEMS -board support package for the Motorola MBX860 and MBX821 as free -software; you can redistribute it and/or modify it under terms of -the GNU General Public License as published by the Free Software -Foundation; either version 2, or (at your option) any later version. -This software is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. You should have received a -copy of the GNU General Public License along with RTEMS; see file -COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, -Cambridge, MA 02139, USA. - -Under no circumstances will the National Research Council of Canada -nor Her Majesty the Queen in right of Canada assume any liablility -for the use this software, nor any responsibility for its quality or -its support. - - -Summary -------- - -BSP NAME: mbx8xx -BOARD: Motorola MBX860 and MBX821 Embedded Controllers -BUS: No backplane. On-board ISA, PCI, PC/104 and PCMCIA. -CPU FAMILY: PowerPC -CPU: PowerPC MPC860 or MPC821 -COPROCESSORS: Built-in Motorola QUICC -MODE: 32 bit mode - -DEBUG MONITOR: EPPC-Bug - -PERIPHERALS -=========== -TIMERS: PIT / Timebase - RESOLUTION: 1 microsecond / frequency = clock-speed / 16 -SERIAL PORTS: 2 or 4 SCCs (SCC1 is hardwired for Ethernet) - 2 SMC - 1 SIO -REAL-TIME CLOCK: Many. Look at documentation. -DMA: Each SCC and SMC. -VIDEO: None on-board. MPC821 has a built-in LCD panel driver. -SCSI: None on-board. -NETWORKING: Ethernet (10 Mbps) on SCC1 - - -DRIVER INFORMATION -================== -CLOCK DRIVER: yes -CONSOLE DRIVER: yes -SHMSUPP: N/A -TIMER DRIVER: yes -NETWORK DRIVER: yes - -NOTES -===== -On-chip resources: - SCC1 network or console - SCC2 serial port - SMC1 gdb debug console/application console - SMC2 application console - CLK1 network - CLK2 network - CLK3 - CLK4 - CLK5 - CLK6 - CLK7 - CLK8 - BRG1 console - BRG2 console - BRG3 console - BRG4 console - RTC - PIT clock - TB - DEC - SWT - *CS0 FLASH - *CS1 DRAM bank (onboard) - *CS2 DRAM bank 0 (1st half of DIMM) - *CS3 DRAM bank 1 (2nd half of DIMM) - *CS4 Battery-Backed SRAM - *CS5 QSPAN PCI - *CS6 QSPAN - *CS7 Boot ROM - UPMA - UPMB - IRQ0 - IRQ1 - IRQ2 - IRQ3 - IRQ4 - IRQ5 - IRQ6 - IRQ7 - IRQ_LVL0 - IRQ_LVL1 - IRQ_LVL2 - IRQ_LVL3 - IRQ_LVL4 - IRQ_LVL5 - IRQ_LVL6 - IRQ_LVL7 - - -Board description ------------------ -Clock rate: 50MHz Entry level boards, 40 MHz others. -Bus width: 8/32 bit Flash, 32 bit DRAM -FLASH: 2-4MB, 120ns -RAM: 4-16MB EDO, 60ns DRAM DIMM - - -Installation ------------- - -All MBX821/MBX860 ports share the same source code base. The MPC821 does -not have SCC3 and SCC4. Instead, it has an LCD panel driver. Otherwise, -the MBX821 and MBX860 boards are essentially identical. Entry level boards -do not have all connectors and peripheral devices present. This has no -impact on the source code base; it merely means that some functionality -is not available on these entry level boards. For the most part, the port -uses the standard build process for powerpc targets. However, you must -specify the EXACT model of MBX board that you are building for as the -argument to the RTEMS_BSP make variable. If you do not, the build process -will build for a MBX860-002. Look at rtems/make/custom/mbx8xx.cfg for the -specific list of boards supported and their corresponding names. An -example build command is: - - make RTEMS_BSP=mbx821_001 VARIANT=DEBUG - -This will build the debug version of all RTEMS libraries, samples and tests -(if the latter are enabled). - -The Software Engineering Group of the Institute for Information Technology -only owns an MBX821-001 and MBX86-002. The only provided config files are -mbx821_001.cfg and mbx860_002.cfg. A SPECIFIC CONFIG FILE IS REQUIRED. Use -one of the provided files as a template to create a specific config file for -another model. - -We rely on EPPC-BUG to download to the targets. We use the "PLH" command. -We enabled a TFTP deamon on our development host. - - -Port Description -Console driver ---------------- - -This BSP includes an termios-capable asynchronous serial line driver that -supports SMC1, SMC2, SCC2, and SCC3 and SCC4 if present. The RTEMS console is -selected in rtems/make/custom/mbx8xx.cfg with the CONSOLE_MINOR variable, or -in NVRAM if that option is enabled in the rtems/make/custom/mbx8xx.cfg file. -We normally run with the RTEMS application console on SMC2. SMC1 is used by -the debugger. - -Support is provided for five different modes of operation: - - 1. polled I/O done by EPPC-Bug with termios support, - 2. polled I/O done by EPPC-Bug without termios support, - 3. polled I/O done by the supplied device driver with termios support, - 4. polled I/O done by the supplied device driver without termios support, - 5. interrupt-driven I/O done by the supplied device driver with termios - support. - -If NVRAM_CONFIGURE is set to 1 in rtems/make/custom/mbx8xx.cfg, the mode of -operation of the driver is determined at boot time from the values stored -in the user area in NVRAM. See the Configuration Parameters section below for -instructions on setting up NVRAM. Otherwise, the mode of operation of the -serial driver is determined at build time in part by the value of the -UARTS_IO_MODE constant in rtems/make/custom/mbx8xx.cfg. Edit the file to select -the type of I/O desired before building RTEMS. The choices are: - - 0 - polled I/O done by the supplied device driver, - 1 - interrupt-driven I/O done by the supplied device driver, - 2 - polled I/O done by EPPC-Bug. - -Also, if NVRAM_CONFIGURE is not set to 1 in rtems/make/custom/mbx8xx.cfg, set -the value of UARTS_USE_TERMIOS to select whether termios should be used to -perform buffering and input/output processing. Without termios support, input -processing is limited to the substitution of LF for a received CR, and output -processing is limited to the transmission of a CR following the transmission of -a LF. The choices for UARTS_USE_TERMIOS are: - - 0 - do not use termios - 1 - use termios - -In most real-time applications, the driver should be configured to use -termios and interrupt-driven I/O. Special requirements may dictate otherwise. - -Polled I/O must be used when running the timing tests. It must also be used -to run some other tests and some samples, such as the cdtest. Some tests -change the interrupt mask and will hang interrupt-driven I/O indefinitely. -Others, such as cdtest, perform console output from the static constructors -before the console is opened, causing the test to hang. Still other tests -produce output that is supposed to be in some specific order. For these -tests, termios should not be used, as termios buffers output and the -transmission of the buffers occur at somewhat unpredictable times. - -The real solution is to fix the tests so that they work with interrupt-driven -I/O and termios. - - -printk() and debug output ------------------------ - -The implementation of printk() in RTEMS is mostly independent of most system -services. The printk() function can therefore be used to print messages to a -debug console, particularly when debugging startup code or device drivers, -i.e. code that runs before the console driver is opened or that runs with -interrupts disabled. - -Support is provided to send printk output to any port. Specify the desired -port at build time in rtems/make/custom/mbx8xx.cfg by setting the value -of PRINTK_MINOR to one of SMC1_MINOR, SMC2_MINOR, SCC2_MINOR, SCC3_MINOR, -or SCC4_MINOR. Alternatively, if NVRAM_CONFIGURE is set to 1 in -rtems/make/custom/mbx8xx.cfg, the printk port is selected based on data that -is stored in the user area in NVRAM. See the Configuration Parameters section -below for instructions on setting up NVRAM. - -Select the type of output desired for printk() by setting the value of -PRINTK_IO_MODE in rtems/make/custom/mbx8xx.cfg. The choices are: - - 0 - polled I/O done by the supplied device driver, - 1 - polled I/O done by the supplied device driver, - 2 - polled I/O done by EPPC-Bug. - -printk() does not use termios. - -If the printk() port is opened by RTEMS, then PRINK_IO_MODE mode must have -the same value as UARTS_IO_MODE, otherwise the I/O functions will be in -conflict. Interrupt-driven printk() output did not work, although we think -that it should have. It would have been of dubious value anyways. If -interrupt-driven I/O is selected (value of 1), the driver defaults to using -polled I/O through the RTEMS driver. - -IMPORTANT: Polled I/O through the RTEMS driver requires that the driver be -initialized. Consequently, to debug startup code using printk prior to the -initialization of the serial driver, use mode 2: polled I/O through EPPC-Bug, -and read the next section. - - -EPPC-Bug and I/O ----------------- - -IMPORTANT: When using EPPC-Bug 1.1 for polled I/O, only the SMC1 port is -usable. This is a deficiency of the firmware which may be fixed in later -revision. When using this monitor with UARTS_IO_MODE set to 2, CONSOLE_MINOR -must be set to SMC1_MINOR. Similarly, if PRINTK_IO_MODE set to 2, -PRINTK_MINOR must be set to SMC1_MINOR. When UARTS_IO_MODE is set to 2, -only SMC1 is usable. - -Be warned that when EPPC-Bug does I/O through a serial port, all interrupts -get turned off in the SIMASK register! This is a definite bug in release 1.1 -of the firmware. It may have been fixed in later releases. EPPB-Bug does -I/O through its debug port whenever it is given control, e.g. after a -breakpoint is hit, not just when it is used to perform polled I/O on behalf -of RTEMS applications. In particular, in our configuration, we have gdb -communication with EPPC-Bug through SMC1. - -To solve this problem, whenever the BSP manipulates the SIMASK, it makes a -copy of the written value in a global variable called 'simask_copy'. That -value must be restored by GDB before execution resumes. The following commands -placed in the .gdbinit file takes care of this: - -# GDB Initialization file for EPPC-Bug. - -define hook-stepi -set language c -set *(int *)0xFA200014=simask_copy -set language auto -end - -define hook-step -set language c -set *(int *)0xFA200014=simask_copy -set language auto -end - -define hook-continue -set language c -set *(int *)0xFA200014=simask_copy -set language auto -end - -define hook-nexti -set language c -set *(int *)0xFA200014=simask_copy -set language auto -end - -define hook-next -set language c -set *(int *)0xFA200014=simask_copy -set language auto -end - -define hook-finish -set language c -set *(int *)0xFA200014=simask_copy -set language auto -end - -IMPORTANT: When using EPPC-Bug on SMC1, either for debugging or for polled I/O, -EPPCBUG_SMC1 must be defined in rtems/make/custom/mbx8xx.cfg, or the eppc_bug -field set to non-zero in NVRAM. Defining this constant prevents the device -driver from re-initializing SMC1. It also causes the network driver, the clock -driver, and the asynchronous serial line driver to maintain simask_copy for use -by gdb. - -Polled I/O through EPPC-Bug is pretty funky... If your are old enough, it might -bring back fond memories of the days of 300 baud modems. If not, you can -experience for yourself what the state of the art used to be. - - -Floating-point --------------- - -The MPC860 and MPC821 do not have floating-point units. All code should -get compiled with the appropriate -mcpu flag. The nof variants of the gcc -runtime libraries should be used for linking. - - -Configuration Parameters ------------------------- - -If NVRAM_CONFIGURE is set in rtems/make/custom/mbx8xx.cfg, certain -configuration parameters will be read from the first 31 bytes of the NVRAM -User Area, which starts at 0xFA001000. The user is responsible for writing -the appropriate values in NVRAM (via EPPC-Bug). The paramaters -that are configurable and their default settings are described below. - - Cache Mode (0xFA001000 - 1 byte) - Set the following bits in the byte to control the caches: - bit 0 - 0 - data cache disable - 1 - data cache enable - bit 1 - 0 - instruction cache disable - 1 - instruction cache enable - If enabled, all of RAM except for the last 512 KB will be cached using - copyback mode. The last 512 KB of RAMis for the use of EPPC-Bug. - - Console driver I/O mode (0xFA001001 - 1 byte) - Set the following bits in the byte to set the desired I/O mode - for the rtems ports: - bit 0 - 0 - do not use termios - 1 - use termios - bit 2 & 1 - 00 - polled I/O through RTEMS driver - 01 - interrupt-driven I/O - 10 - polled I/O through EPPC-Bug - Set the following bits in the byte to set the desired I/O mode - for printk: - bit 5 & 4 - 00 - polled I/O through RTEMS driver - 01 - polled I/O through RTEMS driver - 10 - polled I/O through EPPC-Bug - - Console driver ports (0xFA001002 - 1 byte) - Set the following bits in the byte to select the console and printk ports: - bit 2, 1 & 0 select the RTEMS console port - 000 - /dev/tty0, SMC1 - 001 - /dev/tty1, SMC2 - 011 - /dev/tty2, SCC2 - 100 - /dev/tty3, SCC3 - 101 - /dev/tty4, SCC4 - bit 6, 5 & 4 select the RTEMS printk port - 000 - /dev/tty0, SMC1 - 001 - /dev/tty1, SMC2 - 011 - /dev/tty2, SCC2 - 100 - /dev/tty3, SCC3 - 101 - /dev/tty4, SCC4 - If the printk port is the same as some other port that will be opened by an - RTEMS application, then the driver must use polled I/O, or the printk port - must not be used. - - EPPC-Bug in use on SMC1 (0xFA001003 - 1 byte) - Set to non-zero to indicate that EPPC-Bug is using SMC1. This will prevent - the SMC1 port from being re-initialized. - - IP Address (0xFA001004 - 4 bytes) - Write the hexadecimal representation of the IP address of the board in this - location, e.g. 192.168.1.2 = 0xC0A80102 - - Netmask (0xFA001008 - 4 bytes) - Write the hexadecimal representation of the netmask in this location - for example, 255.255.255.0 = 0xFFFFFF00 - - Ethernet Address (0xFA00100C - 6 bytes) - Write the Ethernet address of the board in this location - - Processor ID (0xFA001012 - 2 bytes) - Reserved for future use - - RMA start (0xFA001014 - 4 bytes) - Reserved for future use - - VMA start (0xFA001018 - 4 bytes) - Reserved for future use - - RamSize (0xFA00101C - 4 bytes) - Reserved for future use - - -Miscellaneous -------------- - -All development was based on the eth_comm port. - - -Host System ------------ - -The port was developed on Pentiums II and III running RedHat Linux 6.0 and -6.1. The following tools were used: - - - GNU gcc snapshot dated 20000214 configured for powerpc-rtems; - - GNU binutils 2.10 configured for powerpc-rtems; - -Gcc 2.95.2 also worked. Gcc 2.95.1 will not compile the console driver with --O4 or -O3. Compile it manually with -O2. - - -Known Problems --------------- - -The cdtest will not run with interrupt-driven I/O. The reason is that the -constructors for the static objects are called at boot time when the -interrupts are still disabled. The output buffer fills up, but never empties, -and the application goes into an infinite loop waiting for buffer space. This -should have been documented in the rtems/c/src/tests/PROBLEMS file. The moral -of this story is: do not do I/O from the constructors or destructors of static -objects. - -When using interrupt-driven I/O, psx08 fails with an internal assertion error. - - -What is new ----------- - -All known problems with use of the caches on the MBX860-002 and MBX821-001 -have been resolved. - -Configuration of the console and network is now possible at boot time through -NVRAM parameters. - - -Thanks ------- - -- to Jay Monkman (jmonkman@frasca.com) of Frasca International, Inc. - for his eth_comm port. - -- to On-Line Applications Research Corporation (OAR) for developing - RTEMS and making it available on a Technology Transfer basis; - -- to the FSF and to Cygnus Support for great free software; - - -Test Configuration ------------------- - -Board: MBX821-001, MBX860-002 -CPU: Motorola MPC821, MPC860 -Clock Speed: 50 MHz, 40 MHz -RAM: 4 MBytes of 32-bit DRAM -Cache Configuration: Instruction cache on; data cache on, copyback mode. -Times Reported in: clock ticks: TMBCLK = system clock / 16. -Timer Source: Timebase clock -GCC Flags: -O4 -fno-keep-inline-functions -mcpu=(821/860) -Console: Operates in polled mode on SMC2. No I/O through EPPC-Bug. - - -Test Results ------------- - -Single processor tests: All tests passed, except the following ones: - - - cpuuse and malloctest did not work. - - - The stackchk test got an access fault exception before the RTEMS stack - checker had had a chance to detect the corrupted stack. - - -Multi-processort tests: not applicable. - - -Timing tests: - See the times-mbx821 and times-mbx860 files for the results of the - timing tests. - - -Network tests: - Worked. - - - diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/bsp_specs b/c/src/lib/libbsp/powerpc/mbx8xx/bsp_specs deleted file mode 100644 index 5f2b130450..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/bsp_specs +++ /dev/null @@ -1,13 +0,0 @@ -%rename endfile old_endfile -%rename startfile old_startfile -%rename link old_link - -*startfile: -%{!qrtems: %(old_startfile)} \ -%{!nostdlib: %{qrtems: ecrti%O%s rtems_crti%O%s crtbegin.o%s start.o%s}} - -*endfile: -%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s} - -*link: -%{!qrtems: %(old_link)} %{qrtems: -dc -dp -u __vectors -N} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c b/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c deleted file mode 100644 index d1fd075b01..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * @file - * @brief mbx8xx Clock Tick connection code. - */ - -/* - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to support the MPC750. - * Modifications Copyright (c) 1999 Eric Valette valette@crf.canon.fr - */ - -#include -#include -#include - -extern void clockOn(void*); -extern void clockOff (void*); -extern int clockIsOn(void*); -extern void Clock_isr(void*); - -static rtems_irq_connect_data clockIrqData = { - BSP_PERIODIC_TIMER, - (rtems_irq_hdl)Clock_isr, - 0, - (rtems_irq_enable)clockOn, - (rtems_irq_disable)clockOff, - (rtems_irq_is_enabled)clockIsOn -}; - -/* - * Prototypes - */ -int BSP_get_clock_irq_level(void); -int BSP_connect_clock_handler(rtems_irq_hdl hdl); -int BSP_disconnect_clock_handler(void); - -int BSP_get_clock_irq_level(void) -{ - /* - * Caution: if you change this, you must change the - * definition of BSP_PERIODIC_TIMER accordingly - */ - return 6; -} - -int BSP_disconnect_clock_handler(void) -{ - if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) { - printk("Unable to stop system clock\n"); - rtems_fatal_error_occurred(1); - } - return BSP_remove_rtems_irq_handler (&clockIrqData); -} - -int BSP_connect_clock_handler(rtems_irq_hdl hdl) -{ - if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) { - printk("Unable to get system clock handler\n"); - rtems_fatal_error_occurred(1); - } - - if (!BSP_remove_rtems_irq_handler(&clockIrqData)) { - printk("Unable to remove current system clock handler\n"); - rtems_fatal_error_occurred(1); - } - - /* - * Reinit structure - */ - clockIrqData.name = BSP_PERIODIC_TIMER; - clockIrqData.hdl = (rtems_irq_hdl) hdl; - clockIrqData.on = (rtems_irq_enable)clockOn; - clockIrqData.off = (rtems_irq_enable)clockOff; - clockIrqData.isOn = (rtems_irq_is_enabled)clockIsOn; - - return BSP_install_rtems_irq_handler (&clockIrqData); -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac b/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac deleted file mode 100644 index 996c780394..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/configure.ac +++ /dev/null @@ -1,112 +0,0 @@ -## Process this file with autoconf to produce a configure script. - -AC_PREREQ([2.69]) -AC_INIT([rtems-c-src-lib-libbsp-powerpc-mbx8xx],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) -AC_CONFIG_SRCDIR([bsp_specs]) -RTEMS_TOP(../../../../../..) - -RTEMS_CANONICAL_TARGET_CPU -AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) -RTEMS_BSP_CONFIGURE - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_CANONICALIZE_TOOLS -RTEMS_PROG_CCAS - -RTEMS_CHECK_NETWORKING -AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") - -RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mbx860_005b],[]) -RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1]) -RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED - -RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1]) -RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED - -RTEMS_BSPOPTS_SET([NVRAM_CONFIGURE],[mbx860_005b],[0]) -RTEMS_BSPOPTS_SET([NVRAM_CONFIGURE],[*],[1]) -RTEMS_BSPOPTS_HELP([NVRAM_CONFIGURE], -[Define to 1 if you want the console driver, network driver and caches - configured at boot time from parameters stored in NVRAM. If set to 1, - most parameters below are ignored during the build. If not set to 1, - then the console driver is configured at build time, the network host - information is obtained from application supplied data structures, and - the caches are configured at boot time based on the information - supplied - in this file.]) - -RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[mbx860_005b],[1]) -RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[*],[0]) -RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS], -[Define to 1 if you want termios support for every port. - Termios support is independent of the choice of UART I/O mode.]) - -RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[mbx860_005b],[SMC1_MINOR]) -RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[*],[SMC2_MINOR]) -RTEMS_BSPOPTS_HELP([CONSOLE_MINOR], -[(BSP--console driver) Must be defined to be one of SMC1_MINOR, - SMC2_MINOR, SCC2_MINOR, SCC3_MINOR, or SCC4_MINOR. - Determines which device will be registered as /dev/console.]) - -RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[*],[0]) -RTEMS_BSPOPTS_HELP([UARTS_IO_MODE], -[(BSP--console driver) - Define to 0 or 1 if you want polled I/O performed by RTEMS. - Define to 1 if you want interrupt-driven performed by RTEMS. - Define to 2 if you want polled I/O performed by EPPCBug. - There is no provision to have a mix of interrupt-driven and polled I/O - ports, except that the printk port may use a different mode from the - other ports. If this is done, do not open the printk port from an RTEMS - application. With EPPCBug 1.1, if mode 2 is selected, CONSOLE_MINOR - must be set to SMC1_MINOR. This is a deficiency of the firmware: it - does not perform serial I/O on any port other than its default debug - port, which must be SMC1.]) - -RTEMS_BSPOPTS_SET([PRINTK_MINOR],[mbx860_005b],[SMC1_MINOR]) -RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*],[SMC2_MINOR]) -RTEMS_BSPOPTS_HELP([PRINTK_MINOR], -[(BSP--console driver) - Must be defined to be one of SMC1_MINOR, SMC2_MINOR, SCC2_MINOR, - SCC3_MINOR, or SCC4_MINOR. Determines which device is used for output - by printk(). If the port that printk() uses is also used for other - I/O (e.g. if PRINTK_MINOR == \$CONSOLE_MINOR), then both ports should - use the same type of I/O, otherwise the drivers will likely conflict with - each other.]) - -RTEMS_BSPOPTS_SET([PRINTK_IO_MODE],[*],[0]) -RTEMS_BSPOPTS_HELP([PRINTK_IO_MODE], -[(BSP--console driver) - Define to 0 or 1 if you want polled I/O performed by RTEMS. - Define to 2 if you want polled I/O performed by EPPCBug. - The printk() port is not configured to use termios. With EPPCBug 1.1, - if mode 2 is selected, PRINTK_MINOR must be set to SMC1_MINOR. - This is a deficiency of the firmware: it does not perform serial I/O - on any port other than its default debug port, which must be SMC1. - Printk always uses polled output.]) - -RTEMS_BSPOPTS_SET([EPPCBUG_SMC1],[mbx860_005b],[]) -RTEMS_BSPOPTS_SET([EPPCBUG_SMC1],[*],[1]) -RTEMS_BSPOPTS_HELP([EPPCBUG_SMC1], -[(BSP--console driver) - If defined, SMC1 is in use by EPPC-Bug. The console driver will not - re-initialize that port.]) - -RTEMS_BSPOPTS_SET([EPPCBUG_VECTORS],[mbx860_005b],[]) -RTEMS_BSPOPTS_SET([EPPCBUG_VECTORS],[*],[1]) -RTEMS_BSPOPTS_HELP([EPPCBUG_VECTORS], -[(BSP--RTEMS) - If defined, vectors branch to EPPCBug, except the following: - 0x500 (external interrupt), 0x900 (decrementer).]) - -RTEMS_BSPOPTS_SET([DISPATCH_HANDLER_STAT],[*],[]) -RTEMS_BSPOPTS_HELP([DISPATCH_HANDLER_STAT], -[used by irq/irq.c]) - -RTEMS_BSP_CLEANUP_OPTIONS(0, 0) - -# Explicitly list a Makefile here -AC_CONFIG_FILES([Makefile]) - -RTEMS_PPC_EXCEPTIONS - -AC_OUTPUT diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c deleted file mode 100644 index 6c7d593b9f..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * console.c - * - * This file contains the MBX8xx termios serial I/O package. - * Only asynchronous I/O is supported. - * - * The SCCs and SMCs are assigned as follows - * - * Channel Device Minor Note - * SMC1 /dev/tty0 0 - * SMC2 /dev/tty1 1 - * SCC1 2 N/A. Hardwired as ethernet port - * SCC2 /dev/tty2 3 - * SCC3 /dev/tty3 4 - * SCC4 /dev/tty4 5 - * - * All ports support termios. The use of termios is recommended for real-time - * applications. Termios provides buffering and input processing. When not - * using termios, processing is limited to the substitution of LF for CR on - * input, and the output of a CR following the output of a LF character. - * Note that the terminal should not send CR/LF pairs when the return key - * is pressed, and that output lines are terminated with LF/CR, not CR/LF - * (although that would be easy to change). - * - * I/O may be interrupt-driven (recommended for real-time applications) or - * polled. Polled I/O may be performed by this device driver entirely, or - * in part by EPPCBug. With EPPCBug 1.1, polled I/O is limited to the - * EPPCBug debug console. This is a limitation of the firmware. Later - * firmware may be able to do I/O through any port. This code assumes - * that the EPPCBug console is the default: SMC1. If the console and - * printk ports are set to anything else with EPPCBug polled I/O, the - * system will hang. Only port SMC1 is usable with EPPCBug polled I/O. - * - * LIMITATIONS: - * - * It is not possible to use different I/O modes on the different ports. The - * exception is with printk. The printk port can use a different mode from - * the other ports. If this is done, it is important not to open the printk - * port from an RTEMS application. - * - * Currently, the I/O modes are determined at build time. It would be much - * better to have the mode selected at boot time based on parameters in - * NVRAM. - * - * Interrupt-driven I/O requires termios. - * - * TESTS: - * - * TO RUN THE TESTS, USE POLLED I/O WITHOUT TERMIOS SUPPORT. Some tests - * play with the interrupt masks and turn off I/O. Those tests will hang - * when interrupt-driven I/O is used. Other tests, such as cdtest, do I/O - * from the static constructors before the console is open. This test - * will not work with interrupt-driven I/O. Because of the buffering - * performed in termios, test output may not be in sequence.The tests - * should all be fixed to work with interrupt-driven I/O and to - * produce output in the expected sequence. Obviously, the termios test - * requires termios support in the driver. - * - * Set CONSOLE_MINOR to the appropriate device minor number in the - * config file. This allows the RTEMS application console to be different - * from the EPPBug debug console or the GDB port. - * - * This driver handles all five available serial ports: it distinguishes - * the sub-devices using minor device numbers. It is not possible to have - * other protocols running on the other ports when this driver is used as - * currently written. - * - * Based on code (alloc860.c in eth_comm port) by - * Jay Monkman (jmonkman@frasca.com), - * Copyright (C) 1998 by Frasca International, Inc. - * - * Modifications by Darlene Stewart - * and Charles-Antoine Gauthier . - * Copyright (c) 2000, National Research Council of Canada - * - */ -#include -#include -#include /* Must be before libio.h */ -#include -#include -#include -#include - -static void _BSP_output_char( char c ); - -static void _BSP_null_char( char c ) {return;} -static void serial_putchar(const char c); - -BSP_output_char_function_type BSP_output_char = _BSP_null_char; -BSP_polling_getchar_function_type BSP_poll_char = NULL; - -extern volatile m8xx_t m8xx; -extern struct rtems_termios_tty *ttyp[]; - -#if UARTS_IO_MODE == 2 || NVRAM_CONFIGURE == 1 -/* - * _EPPCBug_pollRead - * - * Read a character from the EPPCBug console, and return it. Return -1 - * if there is no character in the input FIFO. - * - * Input parameters: - * minor - selected channel - * - * Output parameters: NONE - * - * Return value: char returned as positive signed int - * -1 if no character is present in the input FIFO. - */ -static int _EPPCBug_pollRead( - int minor -) -{ - char c; - volatile int simask; /* We must read and write m8xx.simask */ - int retval; - ISR_Level level; - - struct { - int clun; - int dlun; - char * inbuf; - int nbytes_requested; - int reserved; - } volatile input_params; - - struct { - int status; - union { - struct { - int input_char_available; - int output_possible; - int break_detected; - int modem_status; - } stat; - struct { - int nbytes_received; - } read; - } u; - } volatile output_params; - - retval = -1; - - input_params.clun = 0; - - switch( minor ) { - case SMC1_MINOR: - input_params.dlun = 0; /* Should be 4, but doesn't work with EPPCBug 1.1 */ - break; - case SMC2_MINOR: - input_params.dlun = 5; - break; - case SCC2_MINOR: - input_params.dlun = 1; - break; -#ifdef mpc860 - case SCC3_MINOR: - input_params.dlun = 2; - break; - case SCC4_MINOR: - input_params.dlun = 3; - break; -#endif - default: - input_params.dlun = 0; - break; - } - - _ISR_Disable( level ); - simask = m8xx.simask; - - /* Check for a char in the input FIFO using .CIO_STAT */ - __asm__ volatile( "li 10,0x202\n\ - mr 3, %0\n\ - mr 4, %1\n\ - sc" - :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); - - if ( (output_params.status == 0) && output_params.u.stat.input_char_available) { - - /* Read the char and return it */ - input_params.inbuf = &c; - input_params.nbytes_requested = 1; - - __asm__ volatile( "li 10,0x200 /* Code for .CIO_READ */\n\ - mr 3, %0 /* Address of input_params */\n\ - mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ - :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); - - if ( (output_params.status == 0) && output_params.u.read.nbytes_received) - retval = (int)c; - } - - m8xx.simask = simask; - _ISR_Enable( level ); - return retval; -} -#endif /* UARTS_IO_MODE == 2 || NVRAM_CONFIGURE == 1 */ - -#if PRINTK_IO_MODE == 2 || UARTS_IO_MODE == 2 || NVRAM_CONFIGURE == 1 -/* - * _EPPCBug_pollWrite - * - * Output buffer through EPPCBug. Returns only once every character has been - * sent (polled output). - * - * Input parameters: - * minor - selected channel - * buf - output buffer - * len - number of chars to output - * - * Output parameters: NONE - * - * Return value: IGNORED - */ -static ssize_t _EPPCBug_pollWrite( - int minor, - const char *buf, - size_t len -) -{ - volatile int simask; - int i; - ISR_Level level; - - struct { - int clun; - int dlun; - const char * outbuf; - int nbytes_to_output; - int reserved; - } volatile input_params; - - struct { - int status; - union { - struct { - int input_char_available; - int output_possible; - int break_detected; - int modem_status; - } stat; - struct { - int nbytes_sent; - } write; - } u; - } volatile output_params; - - input_params.clun = 0; - input_params.reserved = 0; - - switch( minor ) { - case SMC1_MINOR: - input_params.dlun = 0; /* Should be 4, but doesn't work with EPPCBug 1.1 */ - break; - case SMC2_MINOR: - input_params.dlun = 5; - break; - case SCC2_MINOR: - input_params.dlun = 1; - break; -#ifdef mpc860 - case SCC3_MINOR: - input_params.dlun = 2; - break; - case SCC4_MINOR: - input_params.dlun = 3; - break; -#endif - default: - input_params.dlun = 0; - break; - } - - i = 0; - - _ISR_Disable( level ); - simask = m8xx.simask; - - while (i < len) { - /* Wait for space in the output buffer */ - do { - /* Check for space in the output FIFO */ - __asm__ volatile( "li 10,0x202 /* Code for .CIO_STAT */\n\ - mr 3, %0 /* Address of input_params */\n\ - mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ - :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); - - if (output_params.status) - goto error; - } while (!output_params.u.stat.output_possible); - - /* Output the characters until done */ - input_params.outbuf = &buf[i]; - input_params.nbytes_to_output = len - i; - - __asm__ volatile( "li 10,0x201 /* Code for .CIO_WRITE */\n\ - mr 3, %0 /* Address of input_params */\n\ - mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ - :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); - - if (output_params.status) - goto error; - - i += output_params.u.write.nbytes_sent; - } - - /* Return something */ - m8xx.simask = simask; - _ISR_Enable( level ); - return len; - -error: - m8xx.simask = simask; - _ISR_Enable( level ); - return -1; -} -#endif /* PRINTK_IO_MODE == 2 || UARTS_IO_MODE == 2 || NVRAM_CONFIGURE == 1 */ - -#if UARTS_USE_TERMIOS != 1 || NVRAM_CONFIGURE == 1 -/* - * do_poll_read - * - * Input characters through polled I/O. Returns has soon as a character has - * been received. Otherwise, if we wait for the number of requested characters, - * we could be here forever! - * - * CR is converted to LF on input. The terminal should not send a CR/LF pair - * when the return or enter key is pressed. - * - * Input parameters: - * major - ignored. Should be the major number for this driver. - * minor - selected channel. - * arg->buffer - where to put the received characters. - * arg->count - number of characters to receive before returning--Ignored. - * - * Output parameters: - * arg->bytes_moved - the number of characters read. Always 1. - * - * Return value: RTEMS_SUCCESSFUL - * - * CANNOT BE COMBINED WITH INTERRUPT DRIVEN I/O! - */ -static rtems_status_code do_poll_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_libio_rw_args_t *rw_args = arg; - int c; - -#if NVRAM_CONFIGURE == 1 - - int (*pollRead)( int minor ); - - if ( (nvram->console_mode & 0x06) == 0x04 ) - pollRead = _EPPCBug_pollRead; - else - pollRead = m8xx_uart_pollRead; - - while( (c = (*pollRead)(minor)) == -1 ); - rw_args->buffer[0] = (uint8_t)c; - if( rw_args->buffer[0] == '\r' ) - rw_args->buffer[0] = '\n'; - rw_args->bytes_moved = 1; - return RTEMS_SUCCESSFUL; - -#else - -#if UARTS_IO_MODE == 2 -#define BSP_READ _EPPCBug_pollRead -#else -#define BSP_READ m8xx_uart_pollRead -#endif - - while( (c = BSP_READ(minor)) == -1 ); - rw_args->buffer[0] = (uint8_t)c; - if( rw_args->buffer[0] == '\r' ) - rw_args->buffer[0] = '\n'; - rw_args->bytes_moved = 1; - return RTEMS_SUCCESSFUL; - -#endif -} - -/* - * do_poll_write - * - * Output characters through polled I/O. Returns only once every character has - * been sent. - * - * CR is transmitted AFTER a LF on output. - * - * Input parameters: - * major - ignored. Should be the major number for this driver. - * minor - selected channel - * arg->buffer - where to get the characters to transmit. - * arg->count - the number of characters to transmit before returning. - * - * Output parameters: - * arg->bytes_moved - the number of characters read - * - * Return value: RTEMS_SUCCESSFUL - * - * CANNOT BE COMBINED WITH INTERRUPT DRIVEN I/O! - */ -static rtems_status_code do_poll_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_libio_rw_args_t *rw_args = arg; - uint32_t i; - char cr ='\r'; - -#if NVRAM_CONFIGURE == 1 - - ssize_t (*pollWrite)(int minor, const char *buf, size_t len); - - if ( (nvram->console_mode & 0x06) == 0x04 ) - pollWrite = _EPPCBug_pollWrite; - else - pollWrite = m8xx_uart_pollWrite; - - for( i = 0; i < rw_args->count; i++ ) { - (*pollWrite)(minor, &(rw_args->buffer[i]), 1); - if ( rw_args->buffer[i] == '\n' ) - (*pollWrite)(minor, &cr, 1); - } - rw_args->bytes_moved = i; - return RTEMS_SUCCESSFUL; - -#else - -#if UARTS_IO_MODE == 2 -#define BSP_WRITE _EPPCBug_pollWrite -#else -#define BSP_WRITE m8xx_uart_pollWrite -#endif - - for( i = 0; i < rw_args->count; i++ ) { - BSP_WRITE(minor, &(rw_args->buffer[i]), 1); - if ( rw_args->buffer[i] == '\n' ) - BSP_WRITE(minor, &cr, 1); - } - rw_args->bytes_moved = i; - return RTEMS_SUCCESSFUL; - -#endif -} -#endif /* UARTS_USE_TERMIOS != 1 || NVRAM_CONFIGURE == 1 */ - -/* - * Print functions prototyped in bspIo.h - */ - -static void _BSP_output_char( char c ) -{ - char cr = '\r'; - - /* - * Can't rely on console_initialize having been called before this function - * is used, so it may fail unless output is done through EPPC-Bug. - */ -#if NVRAM_CONFIGURE == 1 - - rtems_device_minor_number printk_minor; - - /* Use NVRAM info for configuration */ - printk_minor = (nvram->console_printk_port & 0x70) >> 4; - if( (nvram->console_mode & 0x30) == 0x20 ) { - _EPPCBug_pollWrite( printk_minor, &c, 1 ); - if( c == '\n' ) - _EPPCBug_pollWrite( printk_minor, &cr, 1 ); - } - else { - m8xx_uart_pollWrite( printk_minor, &c, 1 ); - if( c == '\n' ) - m8xx_uart_pollWrite( PRINTK_MINOR, &cr, 1 ); - } - -#else - -#if PRINTK_IO_MODE == 2 -#define PRINTK_WRITE _EPPCBug_pollWrite -#else -#define PRINTK_WRITE m8xx_uart_pollWrite -#endif - - PRINTK_WRITE( PRINTK_MINOR, &c, 1 ); - if( c == '\n' ) - PRINTK_WRITE( PRINTK_MINOR, &cr, 1 ); - -#endif -} - -bd_t *eppcbugInfo= (bd_t *)0xdeadbeef; -bd_t fakeEppcBugInfo = { - 0x42444944, /* Should be 0x42444944 "BDID" */ - sizeof(bd_t), /* Size of this structure */ - 0, /* revision of this structure */ - 0, /* EPPCbug date, i.e. 0x11061997 */ - 0, /* Memory start address */ - 0x1000000, /* Memory (end) size in bytes */ - 0x28, /* Internal Freq, in Hz */ - 0, /* Bus Freq, in Hz */ - 0, /* Boot device controller */ - 0 /* Boot device logical dev */ -}; - -#define EARLY_CONSOLE -#ifdef EARLY_CONSOLE - -#define MBX_CSR1 ((volatile unsigned char *)0xfa100000) -#define CSR1_COMEN (unsigned char)0x02 -#define PROFF_CONS PROFF_SMC1 -#define CPM_CR_CH_CONS CPM_CR_CH_SMC1 -#define SMC_INDEX 0 - -#include - -static cpm8xx_t *cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm); - -void -serial_init(void) -{ - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp; - unsigned int dpaddr, memaddr; - bd_t *bd; - -#if NVRAM_CONFIGURE == 1 - if ( ((nvram->console_mode & 0x06) != 0x04 ) || - ((nvram->console_mode & 0x30) != 0x20 )) { - /* - * FIXME: refine this condition... - */ -#endif - bd = eppcbugInfo; - - cp = cpmp; - sp = (smc_t*)&(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *)&cp->cp_dparam[PROFF_CONS]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - if (*MBX_CSR1 & CSR1_COMEN) { - /* COM1 is enabled. Initialize SMC1 and use it for - * the console port. - */ - - /* Enable SDMA. - */ - ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sdcr = 1; - - /* Use Port B for SMCs instead of other functions. - */ - cp->cp_pbpar |= 0x00000cc0; - cp->cp_pbdir &= ~0x00000cc0; - cp->cp_pbodr &= ~0x00000cc0; - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - */ - dpaddr = 0x0800; - - /* Grab a few bytes from the top of memory. EPPC-Bug isn't - * running any more, so we can do this. - */ - memaddr = (bd->bi_memsize - 32) & ~15; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = memaddr; - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = memaddr+4; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - */ - cp->cp_simode = 0x10000000; - cp->cp_brgc1 = - ((((bd->bi_intfreq * 1000000)/16) / 9600) << 1) | CPM_BRG_EN; - - /* Enable SMC1 for console output. - */ - *MBX_CSR1 &= ~CSR1_COMEN; - } - else { - /* SMCx is used as console port. - */ - tbdf = (cbd_t *)&cp->cp_dpmem[up->smc_tbase]; - rbdf = (cbd_t *)&cp->cp_dpmem[up->smc_rbase]; - - /* Issue a stop transmit, and wait for it. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, - CPM_CR_STOP_TX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - } - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_CONS, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG); - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; -#if NVRAM_CONFIGURE == 1 - } - else { - const char bootmsg_text[]= "using EPPC bug for console I/O\n"; - _EPPCBug_pollWrite((nvram->console_printk_port & 0x70) >> 4, - bootmsg_text, - sizeof(bootmsg_text)-1); - } -#endif -#if NVRAM_CONFIGURE == 1 - if ((nvram->console_mode & 0x30) == 0x20 ) { - BSP_output_char = _BSP_output_char; - } - else { - BSP_output_char = serial_putchar; - } -#else - - BSP_output_char = serial_putchar; -#endif -} - -void -serial_putchar(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY); - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -char -serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile char *buf; - volatile smc_uart_t *up; - char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY); - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int -serial_tstc(void) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_CONS]; - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -#endif -/* - *************** - * BOILERPLATE * - *************** - * - * All these functions are prototyped in rtems/c/src/lib/include/console.h. - */ - -/* - * Initialize and register the device - */ -rtems_device_driver console_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - rtems_status_code status; - rtems_device_minor_number console_minor; - - /* - * Set up TERMIOS if needed - */ -#if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ - console_minor = nvram->console_printk_port & 0x07; - - if ( nvram->console_mode & 0x01 ) - /* termios */ - rtems_termios_initialize (); - - /* - * Do common initialization. - */ - m8xx_uart_initialize(); - - /* - * Do device-specific initialization - */ - if ( !nvram->eppcbug_smc1 && - ( ((nvram->console_mode & 0x30) != 0x20) || - (((nvram->console_printk_port & 0x30) >> 4) != SMC1_MINOR) ) ) - m8xx_uart_smc_initialize(SMC1_MINOR); /* /dev/tty0 */ - - if ( ((nvram->console_mode & 0x30) != 0x20) || - (((nvram->console_printk_port & 0x30) >> 4) != SMC2_MINOR) ) - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ - - if ( ((nvram->console_mode & 0x30) != 0x20) || - (((nvram->console_printk_port & 0x30) >> 4) != SCC2_MINOR) ) - m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ - -#ifdef mpc860 - - if ( ((nvram->console_mode & 0x30) != 0x20) || - (((nvram->console_printk_port & 0x30) >> 4) != SCC3_MINOR) ) - m8xx_uart_scc_initialize(SCC3_MINOR); /* /dev/tty3 */ - - if ( ((nvram->console_mode & 0x30) != 0x20) || - (((nvram->console_printk_port & 0x30) >> 4) != SCC4_MINOR) ) - m8xx_uart_scc_initialize(SCC4_MINOR); /* /dev/tty4 */ - -#endif /* mpc860 */ - BSP_output_char = _BSP_output_char; -#else /* NVRAM_CONFIGURE != 1 */ - - console_minor = CONSOLE_MINOR; - -#if UARTS_USE_TERMIOS == 1 - - rtems_termios_initialize (); - -#endif /* UARTS_USE_TERMIOS */ - - /* - * Do common initialization. - */ - m8xx_uart_initialize(); - - /* - * Do device-specific initialization - */ -#if !defined(EPPCBUG_SMC1) && ( PRINTK_IO_MODE != 2 || PRINTK_MINOR != SMC1_MINOR ) - m8xx_uart_smc_initialize(SMC1_MINOR); /* /dev/tty0 */ -#endif - -#if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SMC2_MINOR - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ -#endif - - #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC2_MINOR - m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ - #endif - -#ifdef mpc860 - -#if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC3_MINOR - m8xx_uart_scc_initialize(SCC3_MINOR); /* /dev/tty3 */ -#endif - -#if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC4_MINOR - m8xx_uart_scc_initialize(SCC4_MINOR); /* /dev/tty4 */ -#endif - -#endif /* mpc860 */ - - BSP_output_char = _BSP_output_char; - -#endif /* NVRAM_CONFIGURE != 1 */ - - status = rtems_io_register_name ("/dev/tty0", major, SMC1_MINOR); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - - status = rtems_io_register_name ("/dev/tty1", major, SMC2_MINOR); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - - status = rtems_io_register_name ("/dev/tty2", major, SCC2_MINOR); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - -#ifdef mpc860 - status = rtems_io_register_name ("/dev/tty3", major, SCC3_MINOR); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - - status = rtems_io_register_name ("/dev/tty4", major, SCC4_MINOR); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - -#endif /* mpc860 */ - - /* Now register the RTEMS console */ - status = rtems_io_register_name ("/dev/console", major, console_minor); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - - return RTEMS_SUCCESSFUL; -} - -/* - * Open the device - */ -rtems_device_driver console_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ -#if NVRAM_CONFIGURE == 1 - /* Used to track termios private data for callbacks */ - rtems_libio_open_close_args_t *args = arg; - static const rtems_termios_callbacks sccEPPCBugCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - _EPPCBug_pollRead, /* pollRead */ - _EPPCBug_pollWrite, /* write */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - 0 /* outputUsesInterrupts */ - }; -#endif - static const rtems_termios_callbacks pollCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - m8xx_uart_pollRead, /* pollRead */ - m8xx_uart_pollWrite, /* write */ - m8xx_uart_setAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - 0 /* outputUsesInterrupts */ - }; - rtems_status_code sc; - -#if (NVRAM_CONFIGURE == 1) || \ - ((NVRAM_CONFIGURE != 1) && (UARTS_USE_TERMIOS == 1) && \ - (UARTS_IO_MODE == 1)) - - static const rtems_termios_callbacks intrCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - NULL, /* pollRead */ - m8xx_uart_write, /* write */ - m8xx_uart_setAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - 1 /* outputUsesInterrupts */ - }; -#endif - - if ( minor > NUM_PORTS-1 ) - return RTEMS_INVALID_NUMBER; - -#if NVRAM_CONFIGURE == 1 - - /* Use NVRAM info for configuration */ - if ( nvram->console_mode & 0x01 ) { - /* Use termios */ - if ( (nvram->console_mode & 0x06) == 0x02 ) { - /* interrupt-driven I/O */ - sc = rtems_termios_open( major, minor, arg, &intrCallbacks ); - ttyp[minor] = args->iop->data1; /* Keep cookie returned by termios_open */ - return sc; - } - else if ( (nvram->console_mode & 0x06) == 0x04 ) - /* polled I/O through EPPC-Bug, better be through SMC1 */ - return rtems_termios_open( major, minor, arg, &sccEPPCBugCallbacks ); - else - /* normal polled I/O */ - return rtems_termios_open( major, minor, arg, &pollCallbacks ); - } - else - /* no termios -- default to polled I/O */ - return RTEMS_SUCCESSFUL; - -#else /* NVRAM_CONFIGURE != 1 */ - -#if UARTS_USE_TERMIOS == 1 - -#if UARTS_IO_MODE == 2 /* EPPCBug polled I/O with termios */ - sc = rtems_termios_open( major, minor, arg, &sccEPPCBugCallbacks ); -#elif UARTS_IO_MODE == 1 /* RTEMS interrupt-driven I/O with termios */ - sc = rtems_termios_open( major, minor, arg, &intrCallbacks ); - ttyp[minor] = args->iop->data1; /* Keep cookie returned by termios_open */ -#else /* RTEMS polled I/O with termios */ - sc = rtems_termios_open( major, minor, arg, &pollCallbacks ); -#endif - -#else /* UARTS_USE_TERMIOS != 1 */ - /* no termios -- default to polled I/O */ - sc = RTEMS_SUCCESSFUL; -#endif /* UARTS_USE_TERMIOS != 1 */ - - return sc; - -#endif /* NVRAM_CONFIGURE != 1 */ -} - -/* - * Close the device - */ -rtems_device_driver console_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - if ( minor > NUM_PORTS-1 ) - return RTEMS_INVALID_NUMBER; - -#if NVRAM_CONFIGURE == 1 - - /* Use NVRAM info for configuration */ - if ( nvram->console_mode & 0x01 ) - /* use termios */ - return rtems_termios_close( arg ); - else - /* no termios */ - return RTEMS_SUCCESSFUL; - -#else /* NVRAM_CONFIGURE != 1 */ - -#if UARTS_USE_TERMIOS == 1 - return rtems_termios_close( arg ); -#else - return RTEMS_SUCCESSFUL; -#endif - -#endif /* NVRAM_CONFIGURE != 1 */ -} - -/* - * Read from the device - */ -rtems_device_driver console_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - if ( minor > NUM_PORTS-1 ) - return RTEMS_INVALID_NUMBER; - -#if NVRAM_CONFIGURE == 1 - - /* Use NVRAM info for configuration */ - if ( nvram->console_mode & 0x01 ) - /* use termios */ - return rtems_termios_read( arg ); - else - /* no termios -- default to polled */ - return do_poll_read( major, minor, arg ); - -#else - -#if UARTS_USE_TERMIOS == 1 - return rtems_termios_read( arg ); -#else - return do_poll_read( major, minor, arg ); -#endif - -#endif -} - -/* - * Write to the device - */ -rtems_device_driver console_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - if ( minor > NUM_PORTS-1 ) - return RTEMS_INVALID_NUMBER; - -#if NVRAM_CONFIGURE == 1 - - /* Use NVRAM info for configuration */ - if ( nvram->console_mode & 0x01 ) - /* use termios */ - return rtems_termios_write( arg ); - else - /* no termios -- default to polled */ - return do_poll_write( major, minor, arg ); - -#else - -#if UARTS_USE_TERMIOS == 1 - return rtems_termios_write( arg ); -#else - /* no termios -- default to polled */ - return do_poll_write( major, minor, arg ); -#endif - -#endif -} - -/* - * Handle ioctl request. - */ -rtems_device_driver console_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - if ( minor > NUM_PORTS-1 ) - return RTEMS_INVALID_NUMBER; - -#if NVRAM_CONFIGURE == 1 - - /* Uuse NVRAM info for configuration */ - if ( nvram->console_mode & 0x01 ) - /* termios */ - return rtems_termios_ioctl( arg ); - else - /* no termios -- default to polled */ - return RTEMS_SUCCESSFUL; - -#else - -#if UARTS_USE_TERMIOS == 1 - return rtems_termios_ioctl( arg ); -#else - return RTEMS_SUCCESSFUL; -#endif - -#endif -} - -/* - * Support routine for console-generic - */ - -int mbx8xx_console_get_configuration(void) -{ -#if NVRAM_CONFIGURE == 1 - return nvram->console_mode; -#else -#if UARTS_IO_MODE == 1 - return 0x02; -#else - return 0; -#endif -#endif - -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c b/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c deleted file mode 100644 index 9b9537de2b..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c +++ /dev/null @@ -1,48 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS MBX8xx IDE harddisc driver tables | -+-----------------------------------------------------------------+ -| File: idecfg.c | -+-----------------------------------------------------------------+ -| Copyright (c) 2003 IMD | -| Ingenieurbuero fuer Microcomputertechnik Th. Doerfler | -| | -| all rights reserved | -+-----------------------------------------------------------------+ -| this file contains the table of functions for the BSP layer | -| for IDE access below the libchip IDE harddisc driver | -| | -+-----------------------------------------------------------------+ -| date history ID | -| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | -| 01.14.03 creation doe | -\*===============================================================*/ - -#include -#include -#include -#include -#include -#include -#include - -/* - * The following table configures the IDE driver used in this BSP. - */ -extern ide_ctrl_fns_t mbx8xx_pcmciaide_ctrl_fns; - -/* IDE controllers Table */ -ide_controller_bsp_table_t IDE_Controller_Table[] = { - {"/dev/idepcmcia", - IDE_STD, /* PCMCIA Flash cards emulate standard IDE controller */ - &mbx8xx_pcmciaide_ctrl_fns, - NULL, /* no BSP dependent probe needed */ - FALSE, /* not (yet) initialized */ - PCMCIA_MEM_ADDR, /* access address for register set */ - FALSE,0, /* not (yet) interrupt driven */ - NULL - } -}; - -/* Number of rows in IDE_Controller_Table */ -unsigned long IDE_Controller_Count = - sizeof(IDE_Controller_Table)/sizeof(IDE_Controller_Table[0]); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c b/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c deleted file mode 100644 index 5ef67739ee..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c +++ /dev/null @@ -1,384 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS MBX8xx PCMCIA IDE harddisc driver | -+-----------------------------------------------------------------+ -| File: pcmcia_ide.c | -+-----------------------------------------------------------------+ -| Copyright (c) 2003 IMD | -| Ingenieurbuero fuer Microcomputertechnik Th. Doerfler | -| | -| all rights reserved | -+-----------------------------------------------------------------+ -| this file contains the BSP layer for PCMCIA IDE access below the| -| libchip IDE harddisc driver | -| based on a board specific driver from | -| Eugeny S. Mints, Oktet | -| | -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| date history ID | -| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | -| 01.14.03 creation doe | -\*===============================================================*/ - -#include -#include -#include -#include -#include -#include -#include - -/* #define DATAREG_16BIT */ /* 16 bit mode not yet working */ -/* #define DEBUG_OUT */ -/* - * support functions for PCMCIA IDE IF - */ -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static bool mbx8xx_pcmciaide_probe -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| This function should probe, whether a PCMCIA flash disk is available | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| true, when flash disk available | -\*=========================================================================*/ -{ - bool ide_card_plugged = true; /* assume: we have a card plugged in */ - - /* - * check, that the CD# pins are low -> a PCMCIA card is plugged in - */ - if ((m8xx.pipr - & (M8xx_PCMCIA_PIPR_CACD1 | M8xx_PCMCIA_PIPR_CACD2)) != 0x00) { - ide_card_plugged = false; - } - /* - * set supply voltage to 3.3V - * FIXME: this should be depending on state of VS1/2 pins - * FIXME: there should be a shadow variable for the BSP for CSR2 access - */ - *((volatile uint8_t*)MBX_CSR2) = 0xb0; - /* - * check card information service whether card is a ATA like disk - * -> scan for tuple of type 0x21 with content 0x04 0xXX (fixed disk) - * -> scan for tuple of type 0x22 with content 0x01 0x01 - */ - if (ide_card_plugged) { -#define CIS_BYTE(pos) (((uint8_t*)PCMCIA_ATTRB_ADDR)[(pos)*2]) - int cis_pos = 0; - bool fixed_disk_tuple_found = false; - bool ata_disk_tuple_found = false; - - while ((cis_pos < 256) && - (CIS_BYTE(cis_pos) != 0xff) && - (!fixed_disk_tuple_found || !ata_disk_tuple_found)) { - /* - * check for neede tuples - */ - if ((CIS_BYTE(cis_pos ) == 0x21) && - (CIS_BYTE(cis_pos+2) == 0x04)) { - fixed_disk_tuple_found = true; - } - else if ((CIS_BYTE(cis_pos ) == 0x22) && - (CIS_BYTE(cis_pos+2) == 0x01) && - (CIS_BYTE(cis_pos+3) == 0x01)) { - ata_disk_tuple_found = true; - } - /* - * advance using the length field - */ - cis_pos += CIS_BYTE(cis_pos+1)+2; - } - ide_card_plugged = fixed_disk_tuple_found && ata_disk_tuple_found; - } - return ide_card_plugged; -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static void mbx8xx_pcmciaide_initialize -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| initialize PCMCIA IDE flash card access | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor /* controller minor number */ - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| | -\*=========================================================================*/ -{ - /* - * FIXME: enable interrupts, if needed - */ - /* - * FIXME: set programming voltage as requested - */ -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static void mbx8xx_pcmciaide_read_reg -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| read a PCMCIA IDE controller register | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor, /* controller minor number */ - int reg, /* register index to access */ - uint16_t *value /* ptr to return value location */ - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| | -\*=========================================================================*/ -{ - uint32_t port = IDE_Controller_Table[minor].port1; - - if (reg == IDE_REGISTER_DATA_WORD) { -#ifdef DATAREG_16BIT - *value = *(volatile uint16_t*)(port+reg); -#else - *value = ((*(volatile uint8_t*)(port+reg) << 8) + - (*(volatile uint8_t*)(port+reg+1) )); -#endif - } - else { - *value = *(volatile uint8_t*)(port+reg); - } -#ifdef DEBUG_OUT - printk("mbx8xx_pcmciaide_read_reg(0x%x)=0x%x\r\n",reg,*value & 0xff); -#endif -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static void mbx8xx_pcmciaide_write_reg -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| write a PCMCIA IDE controller register | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor, /* controller minor number */ - int reg, /* register index to access */ - uint16_t value /* value to write */ - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| | -\*=========================================================================*/ -{ - uint32_t port = IDE_Controller_Table[minor].port1; - -#ifdef DEBUG_OUT - printk("mbx8xx_pcmciaide_write_reg(0x%x,0x%x)\r\n",reg,value & 0xff); -#endif - if (reg == IDE_REGISTER_DATA_WORD) { -#ifdef DATAREG_16BIT - *(volatile uint16_t*)(port+reg) = value; -#else - *(volatile uint8_t*)(port+reg) = value >> 8; - *(volatile uint8_t*)(port+reg+1) = value; -#endif - } - else { - *(volatile uint8_t*)(port+reg)= value; - } -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static void mbx8xx_pcmciaide_read_block -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| read a PCMCIA IDE controller register | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor, - uint32_t block_size, - rtems_blkdev_sg_buffer *bufs, - uint32_t *cbuf, - uint32_t *pos - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| | -\*=========================================================================*/ -{ - uint32_t port = IDE_Controller_Table[minor].port1; - uint16_t cnt = 0; -#ifdef DEBUG_OUT - printk("mbx8xx_pcmciaide_read_block()\r\n"); -#endif -#ifdef DATAREG_16BIT - uint16_t *lbuf = (uint16_t*) - ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); -#else - uint8_t *lbuf = (uint8_t*) - ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); -#endif - uint32_t llength = bufs[(*cbuf)].length; - - while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) - & IDE_REGISTER_STATUS_DRQ) && - (cnt < block_size)) { -#ifdef DATAREG_16BIT - *lbuf++ = *(volatile uint16_t*)(port+8); /* 16 bit data port */ - cnt += 2; - (*pos) += 2; -#else - *lbuf++ = *(volatile uint8_t*)(port+IDE_REGISTER_DATA); - cnt += 1; - (*pos) += 1; -#endif - if ((*pos) == llength) { - (*pos) = 0; - (*cbuf)++; - lbuf = bufs[(*cbuf)].buffer; - llength = bufs[(*cbuf)].length; - } - } -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static void mbx8xx_pcmciaide_write_block -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| write a PCMCIA IDE controller register | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor, - uint32_t block_size, - rtems_blkdev_sg_buffer *bufs, - uint32_t *cbuf, - uint32_t *pos - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| | -\*=========================================================================*/ -{ - uint32_t port = IDE_Controller_Table[minor].port1; - uint16_t cnt = 0; - -#ifdef DEBUG_OUT - printk("mbx8xx_pcmciaide_write_block()\r\n"); -#endif -#ifdef DATA_REG_16BIT - uint16_t *lbuf = (uint16_t*) - ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); -#else - uint8_t *lbuf = (uint8_t*) - ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); -#endif - uint32_t llength = bufs[(*cbuf)].length; - - while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) - & IDE_REGISTER_STATUS_DRQ) && - (cnt < block_size)) { -#ifdef DATAREG_16BIT - *(volatile uint16_t*)(port+8) = *lbuf++; /* 16 bit data port */ - cnt += 2; - (*pos) += 2; -#else - *(volatile uint8_t*)(port+IDE_REGISTER_DATA) = *lbuf++; - cnt += 1; - (*pos) += 1; -#endif - if ((*pos) == llength) { - (*pos) = 0; - (*cbuf)++; - lbuf = bufs[(*cbuf)].buffer; - llength = bufs[(*cbuf)].length; - } - } -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static int mbx8xx_pcmciaide_control -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| control interface for controller | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor, /* controller minor number */ - uint32_t cmd, /* command to send */ - void * arg /* optional argument */ - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| | -\*=========================================================================*/ -{ - return 0; -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -static rtems_status_code mbx8xx_pcmciaide_config_io_speed -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| set up transfer speed, if possible | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int minor, /* controller minor number */ - uint16_t modes_avail /* optional argument */ - ) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| rtems_status_code | -\*=========================================================================*/ -{ - return RTEMS_SUCCESSFUL; -} - -/* - * The following table configures the functions used for IDE drivers - * in this BSP. - */ - -ide_ctrl_fns_t mbx8xx_pcmciaide_ctrl_fns = { - mbx8xx_pcmciaide_probe, - mbx8xx_pcmciaide_initialize, - mbx8xx_pcmciaide_control, - mbx8xx_pcmciaide_read_reg, - mbx8xx_pcmciaide_write_reg, - mbx8xx_pcmciaide_read_block, - mbx8xx_pcmciaide_write_block, - mbx8xx_pcmciaide_config_io_speed -}; diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h deleted file mode 100644 index 98258d49be..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - unsigned int sc_siumcr; - unsigned int sc_sypcr; - unsigned int sc_swt; - char res1[2]; - unsigned short sc_swsr; - unsigned int sc_sipend; - unsigned int sc_simask; - unsigned int sc_siel; - unsigned int sc_sivec; - unsigned int sc_tesr; - char res2[0xc]; - unsigned int sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - unsigned int pcmc_pbr0; - unsigned int pcmc_por0; - unsigned int pcmc_pbr1; - unsigned int pcmc_por1; - unsigned int pcmc_pbr2; - unsigned int pcmc_por2; - unsigned int pcmc_pbr3; - unsigned int pcmc_por3; - unsigned int pcmc_pbr4; - unsigned int pcmc_por4; - unsigned int pcmc_pbr5; - unsigned int pcmc_por5; - unsigned int pcmc_pbr6; - unsigned int pcmc_por6; - unsigned int pcmc_pbr7; - unsigned int pcmc_por7; - char res1[0x20]; - unsigned int pcmc_pgcra; - unsigned int pcmc_pgcrb; - unsigned int pcmc_pscr; - char res2[4]; - unsigned int pcmc_pipr; - char res3[4]; - unsigned int pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - unsigned int memc_br0; - unsigned int memc_or0; - unsigned int memc_br1; - unsigned int memc_or1; - unsigned int memc_br2; - unsigned int memc_or2; - unsigned int memc_br3; - unsigned int memc_or3; - unsigned int memc_br4; - unsigned int memc_or4; - unsigned int memc_br5; - unsigned int memc_or5; - unsigned int memc_br6; - unsigned int memc_or6; - unsigned int memc_br7; - unsigned int memc_or7; - char res1[0x24]; - unsigned int memc_mar; - unsigned int memc_mcr; - char res2[4]; - unsigned int memc_mamr; - unsigned int memc_mbmr; - unsigned short memc_mstat; - unsigned short memc_mptpr; - unsigned int memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - unsigned short sit_tbscr; - unsigned int sit_tbreff0; - unsigned int sit_tbreff1; - char res1[0x14]; - unsigned short sit_rtcsc; - unsigned int sit_rtc; - unsigned int sit_rtsec; - unsigned int sit_rtcal; - char res2[0x10]; - unsigned short sit_piscr; - char res3[2]; - unsigned int sit_pitc; - unsigned int sit_pitr; - char res4[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) -#define TBSCR_REFA ((unsigned short)0x0080) -#define TBSCR_REFB ((unsigned short)0x0040) -#define TBSCR_REFAE ((unsigned short)0x0008) -#define TBSCR_REFBE ((unsigned short)0x0004) -#define TBSCR_TBF ((unsigned short)0x0002) -#define TBSCR_TBE ((unsigned short)0x0001) - -#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) -#define RTCSC_SEC ((unsigned short)0x0080) -#define RTCSC_ALR ((unsigned short)0x0040) -#define RTCSC_38K ((unsigned short)0x0010) -#define RTCSC_SIE ((unsigned short)0x0008) -#define RTCSC_ALE ((unsigned short)0x0004) -#define RTCSC_RTF ((unsigned short)0x0002) -#define RTCSC_RTE ((unsigned short)0x0001) - -#define PISCR_PIRQ_MASK ((unsigned short)0xff00) -#define PISCR_PS ((unsigned short)0x0080) -#define PISCR_PIE ((unsigned short)0x0004) -#define PISCR_PTF ((unsigned short)0x0002) -#define PISCR_PTE ((unsigned short)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - unsigned int car_sccr; - unsigned int car_plprcr; - unsigned int car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - unsigned int sitk_tbscrk; - unsigned int sitk_tbreff0k; - unsigned int sitk_tbreff1k; - unsigned int sitk_tbk; - char res1[0x10]; - unsigned int sitk_rtcsck; - unsigned int sitk_rtck; - unsigned int sitk_rtseck; - unsigned int sitk_rtcalk; - char res2[0x10]; - unsigned int sitk_piscrk; - unsigned int sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - unsigned int cark_sccrk; - unsigned int cark_plprcrk; - unsigned int cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* LCD interface. MPC821 Only. -*/ -typedef struct lcd { - unsigned short lcd_lcolr[16]; - char res[0x20]; - unsigned int lcd_lccr; - unsigned int lcd_lchcr; - unsigned int lcd_lcvcr; - char res2[4]; - unsigned int lcd_lcfaa; - unsigned int lcd_lcfba; - char lcd_lcsr; - char res3[0x7]; -} lcd8xx_t; - -/* I2C -*/ -typedef struct i2c { - unsigned char i2c_i2mod; - char res1[3]; - unsigned char i2c_i2add; - char res2[3]; - unsigned char i2c_i2brg; - char res3[3]; - unsigned char i2c_i2com; - char res4[3]; - unsigned char i2c_i2cer; - char res5[3]; - unsigned char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - unsigned int sdma_sdar; - unsigned char sdma_sdsr; - char res3[3]; - unsigned char sdma_sdmr; - char res4[3]; - unsigned char sdma_idsr1; - char res5[3]; - unsigned char sdma_idmr1; - char res6[3]; - unsigned char sdma_idsr2; - char res7[3]; - unsigned char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - unsigned short cpic_civr; - char res[0xe]; - unsigned int cpic_cicr; - unsigned int cpic_cipr; - unsigned int cpic_cimr; - unsigned int cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - unsigned short iop_padir; - unsigned short iop_papar; - unsigned short iop_paodr; - unsigned short iop_padat; - char res1[8]; - unsigned short iop_pcdir; - unsigned short iop_pcpar; - unsigned short iop_pcso; - unsigned short iop_pcdat; - unsigned short iop_pcint; - char res2[6]; - unsigned short iop_pddir; - unsigned short iop_pdpar; - char res3[2]; - unsigned short iop_pddat; - char res4[8]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - unsigned short cpmt_tgcr; - char res1[0xe]; - unsigned short cpmt_tmr1; - unsigned short cpmt_tmr2; - unsigned short cpmt_trr1; - unsigned short cpmt_trr2; - unsigned short cpmt_tcr1; - unsigned short cpmt_tcr2; - unsigned short cpmt_tcn1; - unsigned short cpmt_tcn2; - unsigned short cpmt_tmr3; - unsigned short cpmt_tmr4; - unsigned short cpmt_trr3; - unsigned short cpmt_trr4; - unsigned short cpmt_tcr3; - unsigned short cpmt_tcr4; - unsigned short cpmt_tcn3; - unsigned short cpmt_tcn4; - unsigned short cpmt_ter1; - unsigned short cpmt_ter2; - unsigned short cpmt_ter3; - unsigned short cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - unsigned int scc_gsmrl; - unsigned int scc_gsmrh; - unsigned short scc_pmsr; - char res1[2]; - unsigned short scc_todr; - unsigned short scc_dsr; - unsigned short scc_scce; - char res2[2]; - unsigned short scc_sccm; - char res3; - unsigned char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - unsigned short smc_smcmr; - char res2[2]; - unsigned char smc_smce; - char res3[3]; - unsigned char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ -typedef struct fec { - unsigned int fec_addr_low; /* LS 32 bits of station address */ - unsigned short fec_addr_high; /* MS 16 bits of address */ - unsigned short res1; - unsigned int fec_hash_table_high; - unsigned int fec_hash_table_low; - unsigned int fec_r_des_start; - unsigned int fec_x_des_start; - unsigned int fec_r_buff_size; - unsigned int res2[9]; - unsigned int fec_ecntrl; - unsigned int fec_ievent; - unsigned int fec_imask; - unsigned int fec_ivec; - unsigned int fec_r_des_active; - unsigned int fec_x_des_active; - unsigned int res3[10]; - unsigned int fec_mii_data; - unsigned int fec_mii_speed; - unsigned int res4[17]; - unsigned int fec_r_bound; - unsigned int fec_r_fstart; - unsigned int res5[6]; - unsigned int fec_x_fstart; - unsigned int res6[17]; - unsigned int fec_fun_code; - unsigned int res7[3]; - unsigned int fec_r_cntrl; - unsigned int fec_r_hash; - unsigned int res8[14]; - unsigned int fec_x_cntrl; - unsigned int res9[0x1e]; -} fec_t; - -typedef struct comm_proc { - /* General control and status registers. - */ - unsigned short cp_cpcr; - char res1[2]; - unsigned short cp_rccr; - char res2[6]; - unsigned short cp_cpmcr1; - unsigned short cp_cpmcr2; - unsigned short cp_cpmcr3; - unsigned short cp_cpmcr4; - char res3[2]; - unsigned short cp_rter; - char res4[2]; - unsigned short cp_rtmr; - char res5[0x14]; - - /* Baud rate generators. - */ - unsigned int cp_brgc1; - unsigned int cp_brgc2; - unsigned int cp_brgc3; - unsigned int cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - unsigned short cp_spmode; - char res6[4]; - unsigned char cp_spie; - char res7[3]; - unsigned char cp_spim; - char res8[2]; - unsigned char cp_spcom; - char res9[2]; - - /* Parallel Interface Port. - */ - char res10[2]; - unsigned short cp_pipc; - char res11[2]; - unsigned short cp_ptpr; - unsigned int cp_pbdir; - unsigned int cp_pbpar; - char res12[2]; - unsigned short cp_pbodr; - unsigned int cp_pbdat; - char res13[0x18]; - - /* Serial Interface and Time Slot Assignment. - */ - unsigned int cp_simode; - unsigned char cp_sigmr; - char res14; - unsigned char cp_sistr; - unsigned char cp_sicmr; - char res15[4]; - unsigned int cp_sicr; - unsigned int cp_sirp; - char res16[0x10c]; - unsigned char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - */ - fec_t cp_fec; - char res18[0x1000]; - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - */ - unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ - unsigned char res19[0xc00]; - unsigned char cp_dparam[0x400]; /* Parameter RAM */ -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - lcd8xx_t im_lcd; /* LCD (821 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h deleted file mode 100644 index eeafa10e11..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h +++ /dev/null @@ -1,97 +0,0 @@ -/* bsp.h - * - * This include file contains all board IO definitions. - * - * This file includes definitions for the MBX860 and MBX821. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MBX8XX_BSP_H -#define LIBBSP_POWERPC_MBX8XX_BSP_H - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Representation of initialization data in NVRAM - */ -typedef volatile struct nvram_config_ { - unsigned char cache_mode; /* 0xFA001000 */ - unsigned char console_mode; /* 0xFA001001 */ - unsigned char console_printk_port; /* 0xFA001002 */ - unsigned char eppcbug_smc1; /* 0xFA001003 */ - unsigned long ipaddr; /* 0xFA001004 */ - unsigned long netmask; /* 0xFA001008 */ - unsigned char enaddr[6]; /* 0xFA00100C */ - unsigned short processor_id; /* 0xFA001012 */ - unsigned long rma_start; /* 0xFA001014 */ - unsigned long vma_start; /* 0xFA001018 */ - unsigned long ramsize; /* 0xFA00101C */ -} nvram_config; - -/* - * Pointer to the base of User Area NVRAM - */ -#define nvram ((nvram_config * const) 0xFA001000) - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "scc1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach - -/* - * We need to decide how much memory will be non-cacheable. This - * will mainly be memory that will be used in DMA (network and serial - * buffers). - */ -#define NOCACHE_MEM_SIZE 512*1024 - -/* - * indicate, that BSP has IDE driver - */ -#define RTEMS_BSP_HAS_IDE_DRIVER - -extern uint32_t bsp_clock_speed; - -char serial_getc(void); - -int serial_tstc(void); - -void serial_init(void); - -int mbx8xx_console_get_configuration(void); - -void _InitMBX8xx(void); - -int BSP_disconnect_clock_handler(void); - -int BSP_connect_clock_handler (rtems_irq_hdl); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h deleted file mode 100644 index 1e0d14a8b8..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. - * This file only contains what I need for the moment, not the total - * CPM capabilities. I (or someone else) will add definitions as they - * are needed. -- Dan - * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. - */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ - -#include - -/* CPM Command register. -*/ -#define CPM_CR_RST ((unsigned short)0x8000) -#define CPM_CR_OPCODE ((unsigned short)0x0f00) -#define CPM_CR_CHAN ((unsigned short)0x00f0) -#define CPM_CR_FLG ((unsigned short)0x0001) - -/* Some commands (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((unsigned short)0x0000) -#define CPM_CR_INIT_RX ((unsigned short)0x0001) -#define CPM_CR_INIT_TX ((unsigned short)0x0002) -#define CPM_CR_STOP_TX ((unsigned short)0x0004) -#define CPM_CR_RESTART_TX ((unsigned short)0x0006) -#define CPM_CR_SET_GADDR ((unsigned short)0x0008) - -/* Channel numbers. -*/ -#define CPM_CR_CH_SCC1 ((unsigned short)0x0000) -#define CPM_CR_CH_I2C ((unsigned short)0x0001) /* I2C and IDMA1 */ -#define CPM_CR_CH_SCC2 ((unsigned short)0x0004) -#define CPM_CR_CH_SPI ((unsigned short)0x0005) /* SPI / IDMA2 / Timers */ -#define CPM_CR_CH_SCC3 ((unsigned short)0x0008) -#define CPM_CR_CH_SMC1 ((unsigned short)0x0009) /* SMC1 / DSP1 */ -#define CPM_CR_CH_SCC4 ((unsigned short)0x000c) -#define CPM_CR_CH_SMC2 ((unsigned short)0x000d) /* SMC2 / DSP2 */ - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -/* The dual ported RAM is multi-functional. Some areas can be (and are - * being) used for microcode. There is an area that can only be used - * as data ram for buffer descriptors, which is all we use right now. - * Currently the first 512 and last 256 bytes are used for microcode. - */ -#define CPM_DATAONLY_BASE ((unsigned int)0x0800) -#define CPM_DATAONLY_SIZE ((unsigned int)0x0700) -#define CPM_DP_NOSPACE ((unsigned int)0x7fffffff) - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -unsigned int m8xx_cpm_dpalloc(unsigned int size); -unsigned int m8xx_cpm_hostalloc(unsigned int size); -void m8xx_cpm_setbrg(unsigned int brg, unsigned int rate); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - unsigned short cbd_sc; /* Status and Control */ - unsigned short cbd_datlen; /* Data length in buffer */ - unsigned int cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((unsigned short)0x8000) /* Recieve is empty */ -#define BD_SC_READY ((unsigned short)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((unsigned short)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((unsigned short)0x1000) /* Interrupt on change */ -#define BD_SC_CM ((unsigned short)0x0200) /* Continous mode */ -#define BD_SC_ID ((unsigned short)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((unsigned short)0x0100) /* xmt preamble */ -#define BD_SC_BR ((unsigned short)0x0020) /* Break received */ -#define BD_SC_FR ((unsigned short)0x0010) /* Framing error */ -#define BD_SC_PR ((unsigned short)0x0008) /* Parity error */ -#define BD_SC_OV ((unsigned short)0x0002) /* Overrun */ -#define BD_SC_CD ((unsigned short)0x0001) /* ?? */ - -/* Parameter RAM offsets. -*/ -#define PROFF_SCC1 ((unsigned int)0x0000) -#define PROFF_SCC2 ((unsigned int)0x0100) -#define PROFF_SCC3 ((unsigned int)0x0200) -#define PROFF_SMC1 ((unsigned int)0x0280) -#define PROFF_SCC4 ((unsigned int)0x0300) -#define PROFF_SMC2 ((unsigned int)0x0380) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - unsigned short smc_rbase; /* Rx Buffer descriptor base address */ - unsigned short smc_tbase; /* Tx Buffer descriptor base address */ - unsigned char smc_rfcr; /* Rx function code */ - unsigned char smc_tfcr; /* Tx function code */ - unsigned short smc_mrblr; /* Max receive buffer length */ - unsigned int smc_rstate; /* Internal */ - unsigned int smc_idp; /* Internal */ - unsigned short smc_rbptr; /* Internal */ - unsigned short smc_ibc; /* Internal */ - unsigned int smc_rxtmp; /* Internal */ - unsigned int smc_tstate; /* Internal */ - unsigned int smc_tdp; /* Internal */ - unsigned short smc_tbptr; /* Internal */ - unsigned short smc_tbc; /* Internal */ - unsigned int smc_txtmp; /* Internal */ - unsigned short smc_maxidl; /* Maximum idle characters */ - unsigned short smc_tmpidl; /* Temporary idle counter */ - unsigned short smc_brklen; /* Last received break length */ - unsigned short smc_brkec; /* rcv'd break condition counter */ - unsigned short smc_brkcr; /* xmt break count register */ - unsigned short smc_rmask; /* Temporary bit mask */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((unsigned char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((unsigned short)0x0001) -#define SMCMR_TEN ((unsigned short)0x0002) -#define SMCMR_DM ((unsigned short)0x000c) -#define SMCMR_SM_GCI ((unsigned short)0x0000) -#define SMCMR_SM_UART ((unsigned short)0x0020) -#define SMCMR_SM_TRANS ((unsigned short)0x0030) -#define SMCMR_SM_MASK ((unsigned short)0x0030) -#define SMCMR_PM_EVEN ((unsigned short)0x0100) /* Even parity, else odd */ -#define SMCMR_PEN ((unsigned short)0x0200) /* Parity enable */ -#define SMCMR_SL ((unsigned short)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((unsigned short)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC Event and Mask register. -*/ -#define SMCM_TXE ((unsigned char)0x10) -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((unsigned int)0x00020000) -#define CPM_BRG_EN ((unsigned int)0x00010000) -#define CPM_BRG_EXTC_INT ((unsigned int)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((unsigned int)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((unsigned int)0x00008000) -#define CPM_BRG_ATB ((unsigned int)0x00002000) -#define CPM_BRG_CD_MASK ((unsigned int)0x00001ffe) -#define CPM_BRG_DIV16 ((unsigned int)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((unsigned int)0x00040000) -#define SCC_GSMRH_GDE ((unsigned int)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((unsigned int)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((unsigned int)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((unsigned int)0x00000000) -#define SCC_GSMRH_REVD ((unsigned int)0x00002000) -#define SCC_GSMRH_TRX ((unsigned int)0x00001000) -#define SCC_GSMRH_TTX ((unsigned int)0x00000800) -#define SCC_GSMRH_CDP ((unsigned int)0x00000400) -#define SCC_GSMRH_CTSP ((unsigned int)0x00000200) -#define SCC_GSMRH_CDS ((unsigned int)0x00000100) -#define SCC_GSMRH_CTSS ((unsigned int)0x00000080) -#define SCC_GSMRH_TFL ((unsigned int)0x00000040) -#define SCC_GSMRH_RFW ((unsigned int)0x00000020) -#define SCC_GSMRH_TXSY ((unsigned int)0x00000010) -#define SCC_GSMRH_SYNL16 ((unsigned int)0x0000000c) -#define SCC_GSMRH_SYNL8 ((unsigned int)0x00000008) -#define SCC_GSMRH_SYNL4 ((unsigned int)0x00000004) -#define SCC_GSMRH_RTSM ((unsigned int)0x00000002) -#define SCC_GSMRH_RSYN ((unsigned int)0x00000001) - -#define SCC_GSMRL_SIR ((unsigned int)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((unsigned int)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((unsigned int)0x40000000) -#define SCC_GSMRL_EDGE_POS ((unsigned int)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((unsigned int)0x00000000) -#define SCC_GSMRL_TCI ((unsigned int)0x10000000) -#define SCC_GSMRL_TSNC_3 ((unsigned int)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((unsigned int)0x08000000) -#define SCC_GSMRL_TSNC_14 ((unsigned int)0x04000000) -#define SCC_GSMRL_TSNC_INF ((unsigned int)0x00000000) -#define SCC_GSMRL_RINV ((unsigned int)0x02000000) -#define SCC_GSMRL_TINV ((unsigned int)0x01000000) -#define SCC_GSMRL_TPL_128 ((unsigned int)0x00c00000) -#define SCC_GSMRL_TPL_64 ((unsigned int)0x00a00000) -#define SCC_GSMRL_TPL_48 ((unsigned int)0x00800000) -#define SCC_GSMRL_TPL_32 ((unsigned int)0x00600000) -#define SCC_GSMRL_TPL_16 ((unsigned int)0x00400000) -#define SCC_GSMRL_TPL_8 ((unsigned int)0x00200000) -#define SCC_GSMRL_TPL_NONE ((unsigned int)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((unsigned int)0x00180000) -#define SCC_GSMRL_TPP_01 ((unsigned int)0x00100000) -#define SCC_GSMRL_TPP_10 ((unsigned int)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((unsigned int)0x00000000) -#define SCC_GSMRL_TEND ((unsigned int)0x00040000) -#define SCC_GSMRL_TDCR_32 ((unsigned int)0x00030000) -#define SCC_GSMRL_TDCR_16 ((unsigned int)0x00020000) -#define SCC_GSMRL_TDCR_8 ((unsigned int)0x00010000) -#define SCC_GSMRL_TDCR_1 ((unsigned int)0x00000000) -#define SCC_GSMRL_RDCR_32 ((unsigned int)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((unsigned int)0x00008000) -#define SCC_GSMRL_RDCR_8 ((unsigned int)0x00004000) -#define SCC_GSMRL_RDCR_1 ((unsigned int)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((unsigned int)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((unsigned int)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((unsigned int)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((unsigned int)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((unsigned int)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((unsigned int)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((unsigned int)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((unsigned int)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((unsigned int)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((unsigned int)0x00000000) -#define SCC_GSMRL_DIAG_LE ((unsigned int)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((unsigned int)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((unsigned int)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((unsigned int)0x00000000) -#define SCC_GSMRL_ENR ((unsigned int)0x00000020) -#define SCC_GSMRL_ENT ((unsigned int)0x00000010) -#define SCC_GSMRL_MODE_ENET ((unsigned int)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((unsigned int)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((unsigned int)0x00000008) -#define SCC_GSMRL_MODE_V14 ((unsigned int)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((unsigned int)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((unsigned int)0x00000005) -#define SCC_GSMRL_MODE_UART ((unsigned int)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((unsigned int)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((unsigned int)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((unsigned int)0x00000000) - -#define SCC_TODR_TOD ((unsigned short)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - unsigned short scc_rbase; /* Rx Buffer descriptor base address */ - unsigned short scc_tbase; /* Tx Buffer descriptor base address */ - unsigned char scc_rfcr; /* Rx function code */ - unsigned char scc_tfcr; /* Tx function code */ - unsigned short scc_mrblr; /* Max receive buffer length */ - unsigned int scc_rstate; /* Internal */ - unsigned int scc_idp; /* Internal */ - unsigned short scc_rbptr; /* Internal */ - unsigned short scc_ibc; /* Internal */ - unsigned int scc_rxtmp; /* Internal */ - unsigned int scc_tstate; /* Internal */ - unsigned int scc_tdp; /* Internal */ - unsigned short scc_tbptr; /* Internal */ - unsigned short scc_tbc; /* Internal */ - unsigned int scc_txtmp; /* Internal */ - unsigned int scc_rcrc; /* Internal */ - unsigned int scc_tcrc; /* Internal */ -} sccp_t; - -/* Function code bits. -*/ -#define SCC_EB ((unsigned char)0x10) /* Set big endian byte order */ - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - unsigned int sen_cpres; /* Preset CRC */ - unsigned int sen_cmask; /* Constant mask for CRC */ - unsigned int sen_crcec; /* CRC Error counter */ - unsigned int sen_alec; /* alignment error counter */ - unsigned int sen_disfc; /* discard frame counter */ - unsigned short sen_pads; /* Tx short frame pad character */ - unsigned short sen_retlim; /* Retry limit threshold */ - unsigned short sen_retcnt; /* Retry limit counter */ - unsigned short sen_maxflr; /* maximum frame length register */ - unsigned short sen_minflr; /* minimum frame length register */ - unsigned short sen_maxd1; /* maximum DMA1 length */ - unsigned short sen_maxd2; /* maximum DMA2 length */ - unsigned short sen_maxd; /* Rx max DMA */ - unsigned short sen_dmacnt; /* Rx DMA counter */ - unsigned short sen_maxb; /* Max BD byte count */ - unsigned short sen_gaddr1; /* Group address filter */ - unsigned short sen_gaddr2; - unsigned short sen_gaddr3; - unsigned short sen_gaddr4; - unsigned int sen_tbuf0data0; /* Save area 0 - current frame */ - unsigned int sen_tbuf0data1; /* Save area 1 - current frame */ - unsigned int sen_tbuf0rba; /* Internal */ - unsigned int sen_tbuf0crc; /* Internal */ - unsigned short sen_tbuf0bcnt; /* Internal */ - unsigned short sen_paddrh; /* physical address (MSB) */ - unsigned short sen_paddrm; - unsigned short sen_paddrl; /* physical address (LSB) */ - unsigned short sen_pper; /* persistence */ - unsigned short sen_rfbdptr; /* Rx first BD pointer */ - unsigned short sen_tfbdptr; /* Tx first BD pointer */ - unsigned short sen_tlbdptr; /* Tx last BD pointer */ - unsigned int sen_tbuf1data0; /* Save area 0 - current frame */ - unsigned int sen_tbuf1data1; /* Save area 1 - current frame */ - unsigned int sen_tbuf1rba; /* Internal */ - unsigned int sen_tbuf1crc; /* Internal */ - unsigned short sen_tbuf1bcnt; /* Internal */ - unsigned short sen_txlen; /* Tx Frame length counter */ - unsigned short sen_iaddr1; /* Individual address filter */ - unsigned short sen_iaddr2; - unsigned short sen_iaddr3; - unsigned short sen_iaddr4; - unsigned short sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - unsigned short sen_taddrh; /* temp address (MSB) */ - unsigned short sen_taddrm; - unsigned short sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PA_ENET_RXD ((unsigned short)0x0001) -#define PA_ENET_TXD ((unsigned short)0x0002) -#define PA_ENET_TCLK ((unsigned short)0x0200) -#define PA_ENET_RCLK ((unsigned short)0x0800) -#define PC_ENET_TENA ((unsigned short)0x0001) -#define PC_ENET_CLSN ((unsigned short)0x0010) -#define PC_ENET_RENA ((unsigned short)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((unsigned int)0x000000ff) -#define SICR_ENET_CLKRT ((unsigned int)0x0000003d) - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((unsigned short)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((unsigned short)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((unsigned short)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((unsigned short)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((unsigned short)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((unsigned short)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PMSR) as used by Ethernet. -*/ -#define SCC_PMSR_HBC ((unsigned short)0x8000) /* Enable heartbeat */ -#define SCC_PMSR_FC ((unsigned short)0x4000) /* Force collision */ -#define SCC_PMSR_RSH ((unsigned short)0x2000) /* Receive short frames */ -#define SCC_PMSR_IAM ((unsigned short)0x1000) /* Check individual hash */ -#define SCC_PMSR_ENCRC ((unsigned short)0x0800) /* Ethernet CRC mode */ -#define SCC_PMSR_PRO ((unsigned short)0x0200) /* Promiscuous mode */ -#define SCC_PMSR_BRO ((unsigned short)0x0100) /* Catch broadcast pkts */ -#define SCC_PMSR_SBT ((unsigned short)0x0080) /* Special backoff timer */ -#define SCC_PMSR_LPB ((unsigned short)0x0040) /* Set Loopback mode */ -#define SCC_PMSR_SIP ((unsigned short)0x0020) /* Sample Input Pins */ -#define SCC_PMSR_LCW ((unsigned short)0x0010) /* Late collision window */ -#define SCC_PMSR_NIB22 ((unsigned short)0x000a) /* Start frame search */ -#define SCC_PMSR_FDE ((unsigned short)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((unsigned short)0x8000) -#define BD_ENET_RX_WRAP ((unsigned short)0x2000) -#define BD_ENET_RX_INTR ((unsigned short)0x1000) -#define BD_ENET_RX_LAST ((unsigned short)0x0800) -#define BD_ENET_RX_FIRST ((unsigned short)0x0400) -#define BD_ENET_RX_MISS ((unsigned short)0x0100) -#define BD_ENET_RX_LG ((unsigned short)0x0020) -#define BD_ENET_RX_NO ((unsigned short)0x0010) -#define BD_ENET_RX_SH ((unsigned short)0x0008) -#define BD_ENET_RX_CR ((unsigned short)0x0004) -#define BD_ENET_RX_OV ((unsigned short)0x0002) -#define BD_ENET_RX_CL ((unsigned short)0x0001) -#define BD_ENET_RX_STATS ((unsigned short)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((unsigned short)0x8000) -#define BD_ENET_TX_PAD ((unsigned short)0x4000) -#define BD_ENET_TX_WRAP ((unsigned short)0x2000) -#define BD_ENET_TX_INTR ((unsigned short)0x1000) -#define BD_ENET_TX_LAST ((unsigned short)0x0800) -#define BD_ENET_TX_TC ((unsigned short)0x0400) -#define BD_ENET_TX_DEF ((unsigned short)0x0200) -#define BD_ENET_TX_HB ((unsigned short)0x0100) -#define BD_ENET_TX_LC ((unsigned short)0x0080) -#define BD_ENET_TX_RL ((unsigned short)0x0040) -#define BD_ENET_TX_RCMASK ((unsigned short)0x003c) -#define BD_ENET_TX_UN ((unsigned short)0x0002) -#define BD_ENET_TX_CSL ((unsigned short)0x0001) -#define BD_ENET_TX_STATS ((unsigned short)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - unsigned int scc_res1; /* Reserved */ - unsigned int scc_res2; /* Reserved */ - unsigned short scc_maxidl; /* Maximum idle chars */ - unsigned short scc_idlc; /* temp idle counter */ - unsigned short scc_brkcr; /* Break count register */ - unsigned short scc_parec; /* receive parity error counter */ - unsigned short scc_frmec; /* receive framing error counter */ - unsigned short scc_nosec; /* receive noise counter */ - unsigned short scc_brkec; /* receive break condition counter */ - unsigned short scc_brkln; /* last received break length */ - unsigned short scc_uaddr1; /* UART address character 1 */ - unsigned short scc_uaddr2; /* UART address character 2 */ - unsigned short scc_rtemp; /* Temp storage */ - unsigned short scc_toseq; /* Transmit out of sequence char */ - unsigned short scc_char1; /* control character 1 */ - unsigned short scc_char2; /* control character 2 */ - unsigned short scc_char3; /* control character 3 */ - unsigned short scc_char4; /* control character 4 */ - unsigned short scc_char5; /* control character 5 */ - unsigned short scc_char6; /* control character 6 */ - unsigned short scc_char7; /* control character 7 */ - unsigned short scc_char8; /* control character 8 */ - unsigned short scc_rccm; /* receive control character mask */ - unsigned short scc_rccr; /* receive control character register */ - unsigned short scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((unsigned short)0x1000) -#define UART_SCCM_GLT ((unsigned short)0x0800) -#define UART_SCCM_AB ((unsigned short)0x0200) -#define UART_SCCM_IDL ((unsigned short)0x0100) -#define UART_SCCM_GRA ((unsigned short)0x0080) -#define UART_SCCM_BRKE ((unsigned short)0x0040) -#define UART_SCCM_BRKS ((unsigned short)0x0020) -#define UART_SCCM_CCR ((unsigned short)0x0008) -#define UART_SCCM_BSY ((unsigned short)0x0004) -#define UART_SCCM_TX ((unsigned short)0x0002) -#define UART_SCCM_RX ((unsigned short)0x0001) - -/* The SCC PMSR when used as a UART. -*/ -#define SCU_PMSR_FLC ((unsigned short)0x8000) -#define SCU_PMSR_SL ((unsigned short)0x4000) -#define SCU_PMSR_CL ((unsigned short)0x3000) -#define SCU_PMSR_UM ((unsigned short)0x0c00) -#define SCU_PMSR_FRZ ((unsigned short)0x0200) -#define SCU_PMSR_RZS ((unsigned short)0x0100) -#define SCU_PMSR_SYN ((unsigned short)0x0080) -#define SCU_PMSR_DRT ((unsigned short)0x0040) -#define SCU_PMSR_PEN ((unsigned short)0x0010) -#define SCU_PMSR_RPM ((unsigned short)0x000c) -#define SCU_PMSR_REVP ((unsigned short)0x0008) -#define SCU_PMSR_TPM ((unsigned short)0x0003) -#define SCU_PMSR_TEVP ((unsigned short)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - unsigned int st_cpres; /* Preset CRC */ - unsigned int st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -#define CPMVEC_NR 32 -#define CPMVEC_PIO_PC15 ((unsigned short)0x1f) -#define CPMVEC_SCC1 ((unsigned short)0x1e) -#define CPMVEC_SCC2 ((unsigned short)0x1d) -#define CPMVEC_SCC3 ((unsigned short)0x1c) -#define CPMVEC_SCC4 ((unsigned short)0x1b) -#define CPMVEC_PIO_PC14 ((unsigned short)0x1a) -#define CPMVEC_TIMER1 ((unsigned short)0x19) -#define CPMVEC_PIO_PC13 ((unsigned short)0x18) -#define CPMVEC_PIO_PC12 ((unsigned short)0x17) -#define CPMVEC_SDMA_CB_ERR ((unsigned short)0x16) -#define CPMVEC_IDMA1 ((unsigned short)0x15) -#define CPMVEC_IDMA2 ((unsigned short)0x14) -#define CPMVEC_TIMER2 ((unsigned short)0x12) -#define CPMVEC_RISCTIMER ((unsigned short)0x11) -#define CPMVEC_I2C ((unsigned short)0x10) -#define CPMVEC_PIO_PC11 ((unsigned short)0x0f) -#define CPMVEC_PIO_PC10 ((unsigned short)0x0e) -#define CPMVEC_TIMER3 ((unsigned short)0x0c) -#define CPMVEC_PIO_PC9 ((unsigned short)0x0b) -#define CPMVEC_PIO_PC8 ((unsigned short)0x0a) -#define CPMVEC_PIO_PC7 ((unsigned short)0x09) -#define CPMVEC_TIMER4 ((unsigned short)0x07) -#define CPMVEC_PIO_PC6 ((unsigned short)0x06) -#define CPMVEC_SPI ((unsigned short)0x05) -#define CPMVEC_SMC1 ((unsigned short)0x04) -#define CPMVEC_SMC2 ((unsigned short)0x03) -#define CPMVEC_PIO_PC5 ((unsigned short)0x02) -#define CPMVEC_PIO_PC4 ((unsigned short)0x01) -#define CPMVEC_ERROR ((unsigned short)0x00) - -extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((unsigned int)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((unsigned int)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((unsigned int)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((unsigned int)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((unsigned int)0x0000e000) /* Core interrrupt */ -#define CICR_HP_MASK ((unsigned int)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((unsigned int)0x00000080) /* Int. enable */ -#define CICR_SPS ((unsigned int)0x00000001) /* SCC Spread */ -#endif /* __CPM_8XX__ */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h deleted file mode 100644 index 4d8166847d..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h +++ /dev/null @@ -1,366 +0,0 @@ -/** - * @file - * @ingroup powerpc_mbx8xx - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) -#if BSP_INSTRUCTION_CACHE_ENABLED -/* - * 50 MHz processor, cache enabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 1 -#define CALLING_OVERHEAD_CLOCK_SET 1 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 0 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#else -/* - * 50 MHz processor, cache disabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 -#define CALLING_OVERHEAD_TASK_CREATE 7 -#define CALLING_OVERHEAD_TASK_IDENT 6 -#define CALLING_OVERHEAD_TASK_START 5 -#define CALLING_OVERHEAD_TASK_RESTART 5 -#define CALLING_OVERHEAD_TASK_DELETE 4 -#define CALLING_OVERHEAD_TASK_SUSPEND 4 -#define CALLING_OVERHEAD_TASK_RESUME 4 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 -#define CALLING_OVERHEAD_TASK_MODE 5 -#define CALLING_OVERHEAD_TASK_GET_NOTE 5 -#define CALLING_OVERHEAD_TASK_SET_NOTE 5 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 19 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 -#define CALLING_OVERHEAD_CLOCK_GET 20 -#define CALLING_OVERHEAD_CLOCK_SET 19 -#define CALLING_OVERHEAD_CLOCK_TICK 3 - -#define CALLING_OVERHEAD_TIMER_CREATE 5 -#define CALLING_OVERHEAD_TIMER_IDENT 4 -#define CALLING_OVERHEAD_TIMER_DELETE 5 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 21 -#define CALLING_OVERHEAD_TIMER_RESET 4 -#define CALLING_OVERHEAD_TIMER_CANCEL 4 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 6 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 6 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5 - -#define CALLING_OVERHEAD_EVENT_SEND 5 -#define CALLING_OVERHEAD_EVENT_RECEIVE 5 -#define CALLING_OVERHEAD_SIGNAL_CATCH 4 -#define CALLING_OVERHEAD_SIGNAL_SEND 5 -#define CALLING_OVERHEAD_PARTITION_CREATE 7 -#define CALLING_OVERHEAD_PARTITION_IDENT 6 -#define CALLING_OVERHEAD_PARTITION_DELETE 4 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 5 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 5 -#define CALLING_OVERHEAD_REGION_CREATE 7 -#define CALLING_OVERHEAD_REGION_IDENT 5 -#define CALLING_OVERHEAD_REGION_DELETE 4 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 6 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5 -#define CALLING_OVERHEAD_PORT_CREATE 6 -#define CALLING_OVERHEAD_PORT_IDENT 5 -#define CALLING_OVERHEAD_PORT_DELETE 4 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 6 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 6 - -#define CALLING_OVERHEAD_IO_INITIALIZE 6 -#define CALLING_OVERHEAD_IO_OPEN 6 -#define CALLING_OVERHEAD_IO_CLOSE 6 -#define CALLING_OVERHEAD_IO_READ 6 -#define CALLING_OVERHEAD_IO_WRITE 6 -#define CALLING_OVERHEAD_IO_CONTROL 6 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 5 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 - -#endif /* BSP_INSTRUCTION_CACHE_ENABLED */ - -#else -#if BSP_INSTRUCTION_CACHE_ENABLED -/* - * 40 MHz processor, cache enabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 1 -#define CALLING_OVERHEAD_CLOCK_SET 1 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#else -/* - * 40 MHz processor, cache disabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 3 -#define CALLING_OVERHEAD_TASK_CREATE 6 -#define CALLING_OVERHEAD_TASK_IDENT 5 -#define CALLING_OVERHEAD_TASK_START 5 -#define CALLING_OVERHEAD_TASK_RESTART 4 -#define CALLING_OVERHEAD_TASK_DELETE 4 -#define CALLING_OVERHEAD_TASK_SUSPEND 4 -#define CALLING_OVERHEAD_TASK_RESUME 4 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 -#define CALLING_OVERHEAD_TASK_MODE 4 -#define CALLING_OVERHEAD_TASK_GET_NOTE 5 -#define CALLING_OVERHEAD_TASK_SET_NOTE 5 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 17 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 3 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 -#define CALLING_OVERHEAD_CLOCK_GET 17 -#define CALLING_OVERHEAD_CLOCK_SET 17 -#define CALLING_OVERHEAD_CLOCK_TICK 3 - -#define CALLING_OVERHEAD_TIMER_CREATE 4 -#define CALLING_OVERHEAD_TIMER_IDENT 4 -#define CALLING_OVERHEAD_TIMER_DELETE 5 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 5 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 19 -#define CALLING_OVERHEAD_TIMER_RESET 4 -#define CALLING_OVERHEAD_TIMER_CANCEL 4 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 6 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 5 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 4 - -#define CALLING_OVERHEAD_EVENT_SEND 5 -#define CALLING_OVERHEAD_EVENT_RECEIVE 5 -#define CALLING_OVERHEAD_SIGNAL_CATCH 4 -#define CALLING_OVERHEAD_SIGNAL_SEND 4 -#define CALLING_OVERHEAD_PARTITION_CREATE 6 -#define CALLING_OVERHEAD_PARTITION_IDENT 5 -#define CALLING_OVERHEAD_PARTITION_DELETE 4 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 5 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 5 -#define CALLING_OVERHEAD_REGION_CREATE 6 -#define CALLING_OVERHEAD_REGION_IDENT 5 -#define CALLING_OVERHEAD_REGION_DELETE 4 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 6 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5 -#define CALLING_OVERHEAD_PORT_CREATE 6 -#define CALLING_OVERHEAD_PORT_IDENT 5 -#define CALLING_OVERHEAD_PORT_DELETE 4 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 5 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 5 - -#define CALLING_OVERHEAD_IO_INITIALIZE 5 -#define CALLING_OVERHEAD_IO_OPEN 5 -#define CALLING_OVERHEAD_IO_CLOSE 5 -#define CALLING_OVERHEAD_IO_READ 5 -#define CALLING_OVERHEAD_IO_WRITE 5 -#define CALLING_OVERHEAD_IO_CONTROL 5 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 3 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 - -#endif /* BSP_INSTRUCTION_CACHE_ENABLED */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h deleted file mode 100644 index 266f985348..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/mbx.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MBX boards. This was originally created for the - * MBX860, and probably needs revisions for other boards (like the 821). - * When this file gets out of control, we can split it up into more - * meaningful pieces. - * - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - */ -#ifndef __MACH_MBX_DEFS -#define __MACH_MBX_DEFS - -/* A Board Information structure that is given to a program when - * EPPC-Bug starts it up. - */ -typedef struct bd_info { - unsigned int bi_tag; /* Should be 0x42444944 "BDID" */ - unsigned int bi_size; /* Size of this structure */ - unsigned int bi_revision; /* revision of this structure */ - unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */ - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned int bi_clun; /* Boot device controller */ - unsigned int bi_dlun; /* Boot device logical dev */ -} bd_t; - -/* Memory map for the MBX as configured by EPPC-Bug. We could reprogram - * The SIU and PCI bridge, and try to use larger MMU pages, but the - * performance gain is not measureable and it certainly complicates the - * generic MMU model. - * - * In a effort to minimize memory usage for embedded applications, any - * PCI driver or ISA driver must request or map the region required by - * the device. For convenience (and since we can map up to 4 Mbytes with - * a single page table page), the MMU initialization will map the - * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI - * Bridge CSRs 1:1 into the kernel address space. - */ -#define PCI_ISA_IO_ADDR ((unsigned int)0x80000000) -#define PCI_ISA_IO_SIZE ((unsigned int)(512 * 1024 * 1024)) -#define PCI_ISA_MEM_ADDR ((unsigned int)0xc0000000) -#define PCI_ISA_MEM_SIZE ((unsigned int)(512 * 1024 * 1024)) -#define PCMCIA_MEM_ADDR ((unsigned int)0xe0000000) -#define PCMCIA_MEM_SIZE ((unsigned int)(64 * 1024 * 1024)) -#define PCMCIA_DMA_ADDR ((unsigned int)0xe4000000) -#define PCMCIA_DMA_SIZE ((unsigned int)(64 * 1024 * 1024)) -#define PCMCIA_ATTRB_ADDR ((unsigned int)0xe8000000) -#define PCMCIA_ATTRB_SIZE ((unsigned int)(64 * 1024 * 1024)) -#define PCMCIA_IO_ADDR ((unsigned int)0xec000000) -#define PCMCIA_IO_SIZE ((unsigned int)(64 * 1024 * 1024)) -#define NVRAM_ADDR ((unsigned int)0xfa000000) -#define NVRAM_SIZE ((unsigned int)(1 * 1024 * 1024)) -#define MBX_CSR_ADDR ((unsigned int)0xfa100000) -#define MBX_CSR_SIZE ((unsigned int)(1 * 1024 * 1024)) -#define IMAP_ADDR ((unsigned int)0xfa200000) -#define IMAP_SIZE ((unsigned int)(64 * 1024)) -#define PCI_CSR_ADDR ((unsigned int)0xfa210000) -#define PCI_CSR_SIZE ((unsigned int)(64 * 1024)) - -#define MBX_CSR2 (MBX_CSR_ADDR+1) -#endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c deleted file mode 100644 index 58bd045330..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * - * This file contains the implementation of the function described in irq.h - * - * Copyright (c) 2009 embedded brains GmbH. - * - * Copyright (C) 1998, 1999 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -volatile unsigned int ppc_cached_irq_mask; - -/* - * Check if symbolic IRQ name is an SIU IRQ - */ -static inline int is_siu_irq(const rtems_irq_number irqLine) -{ - return (((int) irqLine <= BSP_SIU_IRQ_MAX_OFFSET) & - ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET) - ); -} - -/* - * Check if symbolic IRQ name is an CPM IRQ - */ -static inline int is_cpm_irq(const rtems_irq_number irqLine) -{ - return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & - ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) - ); -} - -/* - * masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. - * - */ -const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = -{ - /* IRQ0 ILVL0 IRQ1 ILVL1 */ - 0x00000000, 0x80000000, 0xC0000000, 0xE0000000, - - /* IRQ2 ILVL2 IRQ3 ILVL3 */ - 0xF0000000, 0xF8000000, 0xFC000000, 0xFE000000, - - /* IRQ4 ILVL4 IRQ5 ILVL5 */ - 0xFF000000, 0xFF800000, 0xFFC00000, 0xFFE00000, - - /* IRQ6 ILVL6 IRQ7 ILVL7 */ - 0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000 -}; - -static int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine) -{ - int cpm_irq_index; - - if (!is_cpm_irq(irqLine)) - return 1; - - cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_irq_index); - - return 0; -} - -static int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine) -{ - int cpm_irq_index; - - if (!is_cpm_irq(irqLine)) - return 1; - - cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); - - return 0; -} - -int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine) -{ - int cpm_irq_index; - - if (!is_cpm_irq(irqLine)) - return 0; - - cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); - return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); -} - -int BSP_irq_enable_at_siu(const rtems_irq_number irqLine) -{ - int siu_irq_index; - - if (!is_siu_irq(irqLine)) - return 1; - - siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); - ppc_cached_irq_mask |= (1 << (31-siu_irq_index)); - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; - - return 0; -} - -int BSP_irq_disable_at_siu(const rtems_irq_number irqLine) -{ - int siu_irq_index; - - if (!is_siu_irq(irqLine)) - return 1; - - siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); - ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; - - return 0; -} - -int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine) -{ - int siu_irq_index; - - if (!is_siu_irq(irqLine)) - return 0; - - siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); - return ppc_cached_irq_mask & (1 << (31-siu_irq_index)); -} - -#ifdef DISPATCH_HANDLER_STAT -volatile unsigned int maxLoop = 0; -#endif - -/* - * High level IRQ handler called from shared_raw_irq_code_entry - */ -static int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) -{ - register unsigned int irq; - register unsigned cpmIntr; /* boolean */ - register unsigned oldMask; /* old siu pic masks */ - register unsigned msr; - register unsigned new_msr; -#ifdef DISPATCH_HANDLER_STAT - unsigned loopCounter; -#endif - /* - * Handle decrementer interrupt - */ - if (excNum == ASM_DEC_VECTOR) { - _CPU_MSR_GET(msr); - new_msr = msr | MSR_EE; - _CPU_MSR_SET(new_msr); - - bsp_interrupt_handler_dispatch(BSP_DECREMENTER); - - _CPU_MSR_SET(msr); - return 0; - } - /* - * Handle external interrupt generated by SIU on PPC core - */ -#ifdef DISPATCH_HANDLER_STAT - loopCounter = 0; -#endif - while (1) { - if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { -#ifdef DISPATCH_HANDLER_STAT - if (loopCounter > maxLoop) maxLoop = loopCounter; -#endif - break; - } - irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); - cpmIntr = (irq == BSP_CPM_INTERRUPT); - /* - * Disable the interrupt of the same and lower priority. - */ - oldMask = ppc_cached_irq_mask; - ppc_cached_irq_mask = oldMask & SIU_IvectMask[irq]; - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; - /* - * Acknowledge current interrupt. This has no effect on internal level interrupt. - */ - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); - - if (cpmIntr) { - /* - * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. - * We must before acknowledege the current irq at CPM level to avoid trigerring - * the interrupt again. - */ - /* - * Acknowledge and get the vector. - */ - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1; - irq = (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr >> 11); - /* - * transform IRQ to normalized irq table index. - */ - irq += BSP_CPM_IRQ_LOWEST_OFFSET; - /* - * Unmask CPM interrupt at SIU level - */ - ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT)); - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; - } - /* - * make sure, that the masking operations in - * ICTL and MSR are executed in order - */ - __asm__ volatile("sync":::"memory"); - - _CPU_MSR_GET(msr); - new_msr = msr | MSR_EE; - _CPU_MSR_SET(new_msr); - - bsp_interrupt_handler_dispatch(irq); - - _CPU_MSR_SET(msr); - - /* - * make sure, that the masking operations in - * ICTL and MSR are executed in order - */ - __asm__ volatile("sync":::"memory"); - - if (cpmIntr) { - irq -= BSP_CPM_IRQ_LOWEST_OFFSET; - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq); - } - ppc_cached_irq_mask = oldMask; - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; -#ifdef DISPATCH_HANDLER_STAT - ++ loopCounter; -#endif - } - return 0; -} - -static void BSP_SIU_irq_init(void) -{ - /* - * In theory we should initialize two registers at least : - * SIMASK, SIEL. SIMASK is reset at 0 value meaning no interrupt. But - * we should take care that a monitor may have restoreed to another value. - * If someone find a reasonnable value for SIEL, AND THE NEED TO CHANGE IT - * please feel free to add it here. - */ - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = 0; - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 0xffff0000; - ppc_cached_irq_mask = 0; - ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel; -} - -/* - * Initialize CPM interrupt management - */ -static void -BSP_CPM_irq_init(void) -{ - /* - * Initialize the CPM interrupt controller. - */ - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr = -#ifdef mpc860 - (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | -#else - (CICR_SCB_SCC2 | CICR_SCA_SCC1) | -#endif - ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; - - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; -} - -rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum) -{ - if (is_cpm_irq(irqnum)) { - /* - * Enable interrupt at PIC level - */ - BSP_irq_enable_at_cpm (irqnum); - } - - if (is_siu_irq(irqnum)) { - /* - * Enable interrupt at SIU level - */ - BSP_irq_enable_at_siu (irqnum); - } - - return RTEMS_SUCCESSFUL; -} - -rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum) -{ - if (is_cpm_irq(irqnum)) { - /* - * disable interrupt at PIC level - */ - BSP_irq_disable_at_cpm (irqnum); - } - if (is_siu_irq(irqnum)) { - /* - * disable interrupt at OPENPIC level - */ - BSP_irq_disable_at_siu (irqnum); - } - - return RTEMS_SUCCESSFUL; -} - -rtems_status_code bsp_interrupt_facility_initialize() -{ - /* Install exception handler */ - if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) { - return RTEMS_IO_ERROR; - } - if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) { - return RTEMS_IO_ERROR; - } - - /* Initialize the interrupt controller */ - BSP_SIU_irq_init(); - BSP_CPM_irq_init(); - - /* - * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been - * set up in BSP_CPM_irq_init. - */ - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; - BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT); - - return RTEMS_SUCCESSFUL; -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h deleted file mode 100644 index b79ea96690..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h +++ /dev/null @@ -1,184 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MBX8XX_IRQ_IRQ_H -#define LIBBSP_POWERPC_MBX8XX_IRQ_IRQ_H - -#include - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -extern volatile unsigned int ppc_cached_irq_mask; - -/* - * Symblolic IRQ names and related definitions. - */ - - /* - * SIU IRQ handler related definitions - */ -#define BSP_SIU_IRQ_NUMBER 16 /* 16 reserved but in the future... */ -#define BSP_SIU_IRQ_LOWEST_OFFSET 0 -#define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER - 1) - /* - * CPM IRQ handlers related definitions - * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE - */ -#define BSP_CPM_IRQ_NUMBER 32 -#define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_NUMBER + BSP_SIU_IRQ_LOWEST_OFFSET) -#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1) - /* - * PowerPc exceptions handled as interrupt where a rtems managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER 1 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - /* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET) - /* - * Some SIU IRQ symbolic name definition. Please note that - * INT IRQ are defined but a single one will be used to - * redirect all CPM interrupt. - */ -#define BSP_SIU_EXT_IRQ_0 0 -#define BSP_SIU_INT_IRQ_0 1 - -#define BSP_SIU_EXT_IRQ_1 2 -#define BSP_SIU_INT_IRQ_1 3 - -#define BSP_SIU_EXT_IRQ_2 4 -#define BSP_SIU_INT_IRQ_2 5 - -#define BSP_SIU_EXT_IRQ_3 6 -#define BSP_SIU_INT_IRQ_3 7 - -#define BSP_SIU_EXT_IRQ_4 8 -#define BSP_SIU_INT_IRQ_4 9 - -#define BSP_SIU_EXT_IRQ_5 10 -#define BSP_SIU_INT_IRQ_5 11 - -#define BSP_SIU_EXT_IRQ_6 12 -#define BSP_SIU_INT_IRQ_6 13 - -#define BSP_SIU_EXT_IRQ_7 14 -#define BSP_SIU_INT_IRQ_7 15 - /* - * Symbolic name for CPM interrupt on SIU Internal level 2 - */ -#define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2 -#define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6 -#define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3 - /* - * Some CPM IRQ symbolic name definition - */ -#define BSP_CPM_IRQ_ERROR BSP_CPM_IRQ_LOWEST_OFFSET -#define BSP_CPM_IRQ_PARALLEL_IO_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 1) -#define BSP_CPM_IRQ_PARALLEL_IO_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 2) -#define BSP_CPM_IRQ_SMC2_OR_PIP (BSP_CPM_IRQ_LOWEST_OFFSET + 3) -#define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4) -#define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 5) -#define BSP_CPM_IRQ_PARALLEL_IO_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 6) -#define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 7) - -#define BSP_CPM_IRQ_PARALLEL_IO_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 9) -#define BSP_CPM_IRQ_PARALLEL_IO_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 10) -#define BSP_CPM_IRQ_PARALLEL_IO_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 11) -#define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 12) - -#define BSP_CPM_IRQ_PARALLEL_IO_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 14) -#define BSP_CPM_IRQ_PARALLEL_IO_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 15) -#define BSP_CPM_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 16) -#define BSP_CPM_RISC_TIMER_TABLE (BSP_CPM_IRQ_LOWEST_OFFSET + 17) -#define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 18) - -#define BSP_CPM_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20) -#define BSP_CPM_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 21) -#define BSP_CPM_SDMA_CHANNEL_BUS_ERR (BSP_CPM_IRQ_LOWEST_OFFSET + 22) -#define BSP_CPM_IRQ_PARALLEL_IO_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 23) -#define BSP_CPM_IRQ_PARALLEL_IO_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 24) -#define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 25) -#define BSP_CPM_IRQ_PARALLEL_IO_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 26) -#define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 27) -#define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 28) -#define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 29) -#define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 30) -#define BSP_CPM_IRQ_PARALLEL_IO_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 31) - /* - * Some Processor exception handled as rtems IRQ symbolic name definition - */ -#define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -#define CPM_INTERRUPT - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ -/* - * ------------------------ PPC SIU Mngt Routines ------- - */ - -/* - * function to disable a particular irq at 8259 level. After calling - * this function, even if the device asserts the interrupt line it will - * not be propagated further to the processor - */ -int BSP_irq_disable_at_siu (const rtems_irq_number irqLine); -/* - * function to enable a particular irq at 8259 level. After calling - * this function, if the device asserts the interrupt line it will - * be propagated further to the processor - */ -int BSP_irq_enable_at_siu (const rtems_irq_number irqLine); -/* - * function to acknoledge a particular irq at 8259 level. After calling - * this function, if a device asserts an enabled interrupt line it will - * be propagated further to the processor. Mainly usefull for people - * writting raw handlers as this is automagically done for rtems managed - * handlers. - */ -int BSP_irq_ack_at_siu (const rtems_irq_number irqLine); -/* - * function to check if a particular irq is enabled at 8259 level. After calling - */ -int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine); - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); - -extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_001.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_001.cfg deleted file mode 100644 index dc3a69836f..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_001.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX821-001 card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx821_001 -8XX_CPU_TYPE=821 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002.cfg deleted file mode 100644 index e8e1a7ce6d..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX821-001 card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx821_002 -8XX_CPU_TYPE=821 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002b.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002b.cfg deleted file mode 100644 index 093b646d58..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx821_002b.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX821-002b card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx821_002b -8XX_CPU_TYPE=821 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_001b.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_001b.cfg deleted file mode 100644 index 10fa89fbed..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_001b.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX860-001b card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx860_001b -8XX_CPU_TYPE=860 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_002.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_002.cfg deleted file mode 100644 index cc4617aa27..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_002.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX860-002 card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx860_002 -8XX_CPU_TYPE=860 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_005b.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_005b.cfg deleted file mode 100644 index 748f68a0d7..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_005b.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX860-005b card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx860_005b -8XX_CPU_TYPE=860 - -# The 860_005b has 16M ram : org = 0x0, l = 16M -MBX8xx_LDFLAGS=-Wl,--defsym -Wl,HeapSize=0x100000 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_1b.cfg b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_1b.cfg deleted file mode 100644 index beb9027cfb..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx860_1b.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# Config file for a PowerPC MPC860-based MBX821-002b card. -# - -# -# All MBX8xx configurations share the same base file, only a few -# parameters differ. -# - -RTEMS_MBX_MODEL=mbx860_001b -8XX_CPU_TYPE=860 - -include $(RTEMS_ROOT)/make/custom/mbx8xx.inc diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc deleted file mode 100644 index fcfda3189f..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc +++ /dev/null @@ -1,57 +0,0 @@ -# -# Config file for a PowerPC MPC821- or MPC860-based MBX card -# -# This file is derived from: -# -# Config file for a PowerPC 403 based helas403 card -# Config file for MPC860 based Ethernet Comm Board -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=powerpc -RTEMS_CPU_MODEL=mpc$(8XX_CPU_TYPE) - -# This section makes the target dependent options file. -# -# Note that RTEMS_BSP matches the RTEMS_MBX_MODEL. Its value must be -# defined in targopts.h, so the few places that require different code -# for different MBX models can be distinguished. The value of -# RTEMS_BSP is already defined in targopts.h and is one of: -# mbx860_001 mbx821_001 -# mbx860_002 mbx821_002 -# mbx860_003 mbx821_003 -# mbx860_004 mbx821_004 -# mbx860_005 mbx821_005 -# mbx860_001b mbx821_001b -# mbx860_002b mbx821_002b -# mbx860_003b mbx821_003b -# mbx860_004b mbx821_004b -# mbx860_005b mbx821_005b -# mbx860_006b mbx821_006b - -# The specific CPU model is defined, so the few places that require -# different code for the MPC860 and MPC821 can be distinguished. -# Either mpc860 or mpc821 is defined. -# -# MBX8xx-specific options: -# - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -# -CPU_CFLAGS = -mcpu=$(8XX_CPU_TYPE) -Dmpc$(8XX_CPU_TYPE) -D$(RTEMS_MBX_MODEL) \ - -meabi -msdata=sysv -fno-common - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -fno-keep-inline-functions -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections -LDFLAGS += $(MBX8xx_LDFLAGS) - -define bsp-post-link - cp $(basename $@)$(EXEEXT) $(basename $@)$(DOWNEXT) - $(STRIP) $(basename $@)$(DOWNEXT) - $(default-bsp-post-link) -endef diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c deleted file mode 100644 index 2e4295d7bf..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c +++ /dev/null @@ -1,1743 +0,0 @@ -/* - * RTEMS/TCPIP driver for MPC8xx SCC1 Ethernet - * - * Modified for MPC860 by Jay Monkman (jmonkman@frasca.com) - * - * This supports Ethernet on either SCC1 or the FEC of the MPC860T. - * Right now, we only do 10 Mbps, even with the FEC. The function - * rtems_enet_driver_attach determines which one to use. Currently, - * only one may be used at a time. - * - * Based on the MC68360 network driver by - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * This supports ethernet on SCC1. Right now, we only do 10 Mbps. - * - * Modifications by Darlene Stewart - * and Charles-Antoine Gauthier - * Copyright (c) 1999, National Research Council of Canada - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include -#include - -/* - * Number of interfaces supported by this driver - */ -#define NIFACES 1 - -/* - * Default number of buffer descriptors set aside for this driver. - * The number of transmit buffer descriptors has to be quite large - * since a single frame often uses four or more buffer descriptors. - */ -#define RX_BUF_COUNT 32 -#define TX_BUF_COUNT 8 -#define TX_BD_PER_BUF 4 - -#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255") - -/* - * RTEMS event used by interrupt handler to signal daemons. - * This must *not* be the same event used by the TCP/IP task synchronization. - */ -#define INTERRUPT_EVENT RTEMS_EVENT_1 - -/* - * RTEMS event used to start transmit daemon. - * This must not be the same as INTERRUPT_EVENT. - */ -#define START_TRANSMIT_EVENT RTEMS_EVENT_2 - -/* - * Receive buffer size -- Allow for a full ethernet packet plus CRC (1518). - * Round off to nearest multiple of RBUF_ALIGN. - */ -#define MAX_MTU_SIZE 1518 -#define RBUF_ALIGN 4 -#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN) - -#if (MCLBYTES < RBUF_SIZE) -# error "Driver must have MCLBYTES > RBUF_SIZE" -#endif - -/* - * Per-device data - */ -struct m8xx_enet_struct { - struct arpcom arpcom; - struct mbuf **rxMbuf; - struct mbuf **txMbuf; - int acceptBroadcast; - int rxBdCount; - int txBdCount; - int txBdHead; - int txBdTail; - int txBdActiveCount; - m8xxBufferDescriptor_t *rxBdBase; - m8xxBufferDescriptor_t *txBdBase; - rtems_id rxDaemonTid; - rtems_id txDaemonTid; - - /* - * Statistics - */ - unsigned long rxInterrupts; - unsigned long rxNotFirst; - unsigned long rxNotLast; - unsigned long rxGiant; - unsigned long rxNonOctet; - unsigned long rxRunt; - unsigned long rxBadCRC; - unsigned long rxOverrun; - unsigned long rxCollision; - - unsigned long txInterrupts; - unsigned long txDeferred; - unsigned long txHeartbeat; - unsigned long txLateCollision; - unsigned long txRetryLimit; - unsigned long txUnderrun; - unsigned long txLostCarrier; - unsigned long txRawWait; -}; -static struct m8xx_enet_struct enet_driver[NIFACES]; - -static void m8xx_scc1_ethernet_on(const rtems_irq_connect_data* ptr) -{ -} - -static void m8xx_scc1_ethernet_off(const rtems_irq_connect_data* ptr) -{ - /* - * Please put relevant code there - */ -} - -static void m8xx_scc1_ethernet_isOn(const rtems_irq_connect_data* ptr) -{ - BSP_irq_enabled_at_cpm (ptr->name); -} - -/* - * SCC1 interrupt handler - */ -static void m8xx_scc1_interrupt_handler (void *unused) -{ - /* Frame received? */ - if ((m8xx.scc1.sccm & 0x8) && (m8xx.scc1.scce & 0x8)) { - m8xx.scc1.scce = 0x8; /* Clear receive frame int */ - m8xx.scc1.sccm &= ~0x8; /* Disable receive frame ints */ - enet_driver[0].rxInterrupts++; /* Rx int has occurred */ - rtems_bsdnet_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); - } - - /* Buffer transmitted or transmitter error? */ - if ((m8xx.scc1.sccm & 0x12) && (m8xx.scc1.scce & 0x12)) { - m8xx.scc1.scce = 0x12; /* Clear Tx int */ - m8xx.scc1.sccm &= ~0x12; /* Disable Tx ints */ - enet_driver[0].txInterrupts++; /* Tx int has occurred */ - rtems_bsdnet_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT); - } -} - -#ifdef MPC860T -/* - * FEC interrupt handler - */ -static void m860_fec_interrupt_handler () -{ - /* - * Frame received? - */ - if (m8xx.fec.ievent & M8xx_FEC_IEVENT_RFINT) { - m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT; - enet_driver[0].rxInterrupts++; - rtems_bsdnet_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); - } - - /* - * Buffer transmitted or transmitter error? - */ - if (m8xx.fec.ievent & M8xx_FEC_IEVENT_TFINT) { - m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT; - enet_driver[0].txInterrupts++; - rtems_bsdnet_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT); - } -} -#endif - -static rtems_irq_connect_data ethernetSCC1IrqData = { - BSP_CPM_IRQ_SCC1, - (rtems_irq_hdl) m8xx_scc1_interrupt_handler, - 0, - (rtems_irq_enable) m8xx_scc1_ethernet_on, - (rtems_irq_disable) m8xx_scc1_ethernet_off, - (rtems_irq_is_enabled)m8xx_scc1_ethernet_isOn -}; - -/* - * Initialize the ethernet hardware - */ -static void -m8xx_enet_initialize (struct m8xx_enet_struct *sc) -{ - int i; - unsigned char *hwaddr; - - /* - * Configure port A - * PA15 is enet RxD. Set PAPAR(15) to 1, PADIR(15) to 0. - * PA14 is enet TxD. Set PAPAR(14) to 1, PADIR(14) to 0, PAODR(14) to 0. - * PA7 is input CLK1. Set PAPAR(7) to 1, PADIR(7) to 0. - * PA6 is input CLK2. Set PAPAR(6) to 1, PADIR(6) to 0. - */ - m8xx.papar |= 0x303; - m8xx.padir &= ~0x303; - m8xx.paodr &= ~0x2; - - /* - * Configure port C - * PC11 is CTS1*. Set PCPAR(11) to 0, PCDIR(11) to 0, and PCSO(11) to 1. - * PC10 is CD1*. Set PCPAR(10) to 0, PCDIR(10) to 0, and PCSO(10) to 1. - */ - m8xx.pcpar &= ~0x30; - m8xx.pcdir &= ~0x30; - m8xx.pcso |= 0x30; - - /* - * Connect CLK1 and CLK2 to SCC1 in the SICR. - * CLK1 is TxClk, CLK2 is RxClk. No grant mechanism, SCC1 is directly - * connected to the NMSI pins. - * R1CS = 0b101 (CLK2) - * T1CS = 0b100 (CLK1) - */ - m8xx.sicr |= 0x2C; - - /* - * Initialize SDMA configuration register - */ - m8xx.sdcr = 1; - - /* - * Allocate mbuf pointers - */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, - M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, - M_MBUF, M_NOWAIT); - if (!sc->rxMbuf || !sc->txMbuf) - rtems_panic ("No memory for mbuf pointers"); - - /* - * Set receiver and transmitter buffer descriptor bases - */ - sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount); - sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); - m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx; - m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx; - - /* - * Send "Init parameters" command - */ - m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1); - - /* - * Set receive and transmit function codes - */ - m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); - m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); - - /* - * Set maximum receive buffer length - */ - m8xx.scc1p.mrblr = RBUF_SIZE; - - /* - * Set CRC parameters - */ - m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF; - m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3; - - /* - * Clear diagnostic counters - */ - m8xx.scc1p.un.ethernet.crcec = 0; - m8xx.scc1p.un.ethernet.alec = 0; - m8xx.scc1p.un.ethernet.disfc = 0; - - /* - * Set pad value - */ - m8xx.scc1p.un.ethernet.pads = 0x8888; - - /* - * Set retry limit - */ - m8xx.scc1p.un.ethernet.ret_lim = 15; - - /* - * Set maximum and minimum frame length - */ - m8xx.scc1p.un.ethernet.mflr = 1518; - m8xx.scc1p.un.ethernet.minflr = 64; - m8xx.scc1p.un.ethernet.maxd1 = MAX_MTU_SIZE; - m8xx.scc1p.un.ethernet.maxd2 = MAX_MTU_SIZE; - - /* - * Clear group address hash table - */ - m8xx.scc1p.un.ethernet.gaddr1 = 0; - m8xx.scc1p.un.ethernet.gaddr2 = 0; - m8xx.scc1p.un.ethernet.gaddr3 = 0; - m8xx.scc1p.un.ethernet.gaddr4 = 0; - - /* - * Set our physical address - */ - hwaddr = sc->arpcom.ac_enaddr; - - m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4]; - m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2]; - m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0]; - - /* - * Aggressive retry - */ - m8xx.scc1p.un.ethernet.p_per = 0; - - /* - * Clear individual address hash table - */ - m8xx.scc1p.un.ethernet.iaddr1 = 0; - m8xx.scc1p.un.ethernet.iaddr2 = 0; - m8xx.scc1p.un.ethernet.iaddr3 = 0; - m8xx.scc1p.un.ethernet.iaddr4 = 0; - - /* - * Clear temp address - */ - m8xx.scc1p.un.ethernet.taddr_l = 0; - m8xx.scc1p.un.ethernet.taddr_m = 0; - m8xx.scc1p.un.ethernet.taddr_h = 0; - - /* - * Set up receive buffer descriptors - */ - for (i = 0 ; i < sc->rxBdCount ; i++) { - (sc->rxBdBase + i)->status = 0; - } - - /* - * Set up transmit buffer descriptors - */ - for (i = 0 ; i < sc->txBdCount ; i++) { - (sc->txBdBase + i)->status = 0; - sc->txMbuf[i] = NULL; - } - sc->txBdHead = sc->txBdTail = 0; - sc->txBdActiveCount = 0; - - /* - * Clear any outstanding events - */ - m8xx.scc1.scce = 0xFFFF; - - /* - * Set up interrupts - */ - if (!BSP_install_rtems_irq_handler (ðernetSCC1IrqData)) { - rtems_panic ("Can't attach M8xx SCC1 interrupt handler\n"); - } - m8xx.scc1.sccm = 0; /* No interrupts unmasked till necessary */ - - /* - * Set up General SCC Mode Register - * Ethernet configuration - */ - m8xx.scc1.gsmr_h = 0x0; - m8xx.scc1.gsmr_l = 0x1088000c; - - /* - * Set up data synchronization register - * Ethernet synchronization pattern - */ - m8xx.scc1.dsr = 0xd555; - - /* - * Set up protocol-specific mode register - * No Heartbeat check - * No force collision - * Discard short frames - * Individual address mode - * Ethernet CRC - * Not promisuous - * Ignore/accept broadcast packets as specified - * Normal backoff timer - * No loopback - * No input sample at end of frame - * 64-byte limit for late collision - * Wait 22 bits before looking for start of frame delimiter - * Disable full-duplex operation - */ - m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100); - - /* - * Enable the TENA (RTS1*) pin - */ - m8xx.pcpar |= 0x1; - m8xx.pcdir &= ~0x1; - - /* - * Enable receiver and transmitter - */ - m8xx.scc1.gsmr_l = 0x1088003c; -} - -#ifdef MPC860T -/* - * Please organize FEC controller code better by moving code from - * m860_fec_initialize_hardware to m8xx_fec_ethernet_on - */ -static void m8xx_fec_ethernet_on(){}; -static void m8xx_fec_ethernet_off(){}; -static int m8xx_fec_ethernet_isOn (const rtems_irq_connect_data* ptr) -{ - return BSP_irq_enabled_at_siu (ptr->name); -} - -static rtems_irq_connect_data ethernetFECIrqData = { - BSP_FAST_ETHERNET_CTRL, - (rtems_irq_hdl) m8xx_fec_interrupt_handler, - (rtems_irq_enable) m8xx_fec_ethernet_on, - (rtems_irq_disable) m8xx_fec_ethernet_off, - (rtems_irq_is_enabled)m8xx_fec_ethernet_isOn -}; - -static void -m860_fec_initialize_hardware (struct m860_enet_struct *sc) -{ - int i; - unsigned char *hwaddr; - rtems_status_code status; - - /* - * Issue reset to FEC - */ - m8xx.fec.ecntrl=0x1; - - /* - * Put ethernet transciever in reset - */ - m8xx.pgcra |= 0x80; - - /* - * Configure I/O ports - */ - m8xx.pdpar = 0x1fff; - m8xx.pddir = 0x1c58; - - /* - * Take ethernet transciever out of reset - */ - m8xx.pgcra &= ~0x80; - - /* - * Set SIU interrupt level to LVL2 - * - */ - m8xx.fec.ivec = ((((unsigned) BSP_FAST_ETHERNET_CTRL)/2) << 29); - - /* - * Set the TX and RX fifo sizes. For now, we'll split it evenly - */ - /* If you uncomment these, the FEC will not work right. - m8xx.fec.r_fstart = ((m8xx.fec.r_bound & 0x3ff) >> 2) & 0x3ff; - m8xx.fec.x_fstart = 0; - */ - - /* - * Set our physical address - */ - hwaddr = sc->arpcom.ac_enaddr; - - m8xx.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) | - (hwaddr[2] << 8) | (hwaddr[3] << 0); - m8xx.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16); - - /* - * Clear the hash table - */ - m8xx.fec.hash_table_high = 0; - m8xx.fec.hash_table_low = 0; - - /* - * Set up receive buffer size - */ - m8xx.fec.r_buf_size = 0x5f0; /* set to 1520 */ - - /* - * Allocate mbuf pointers - */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, - M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, - M_MBUF, M_NOWAIT); - if (!sc->rxMbuf || !sc->txMbuf) - rtems_panic ("No memory for mbuf pointers"); - - /* - * Set receiver and transmitter buffer descriptor bases - */ - sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount); - sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); - m8xx.fec.r_des_start = (int)sc->rxBdBase; - m8xx.fec.x_des_start = (int)sc->txBdBase; - - /* - * Set up Receive Control Register: - * Not promiscuous mode - * MII mode - * Half duplex - * No loopback - */ - m8xx.fec.r_cntrl = 0x00000006; - - /* - * Set up Transmit Control Register: - * Half duplex - * No heartbeat - */ - m8xx.fec.x_cntrl = 0x00000000; - - /* - * Set up DMA function code: - * Big-endian - * DMA functino code = 0 - */ - m8xx.fec.fun_code = 0x78000000; - - /* - * Initialize SDMA configuration register - * SDMA ignores FRZ - * FEC not aggressive - * FEC arbitration ID = 0 => U-bus arbitration = 6 - * RISC arbitration ID = 1 => U-bus arbitration = 5 - */ - m8xx.sdcr = 1; - - /* - * Set MII speed to 2.5 MHz for 25 Mhz system clock - */ - m8xx.fec.mii_speed = 0x0a; - m8xx.fec.mii_data = 0x58021000; - - /* - * Set up receive buffer descriptors - */ - for (i = 0 ; i < sc->rxBdCount ; i++) - (sc->rxBdBase + i)->status = 0; - - /* - * Set up transmit buffer descriptors - */ - for (i = 0 ; i < sc->txBdCount ; i++) { - (sc->txBdBase + i)->status = 0; - sc->txMbuf[i] = NULL; - } - sc->txBdHead = sc->txBdTail = 0; - sc->txBdActiveCount = 0; - - /* - * Mask all FEC interrupts and clear events - */ - m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | - M8xx_FEC_IEVENT_RFINT; - m8xx.fec.ievent = ~0; - - /* - * Set up interrupts - */ - if (!BSP_install_rtems_irq_handler (ðernetFECIrqData)) - rtems_panic ("Can't attach M860 FEC interrupt handler\n"); - -} -#endif - -/* - * Soak up buffer descriptors that have been sent. - * Note that a buffer descriptor can't be retired as soon as it becomes - * ready. The MPC860 manual (MPC860UM/AD 07/98 Rev.1) and the MPC821 - * manual state that, "If an Ethernet frame is made up of multiple - * buffers, the user should not reuse the first buffer descriptor until - * the last buffer descriptor of the frame has had its ready bit cleared - * by the CPM". - */ -static void -m8xx_Enet_retire_tx_bd (struct m8xx_enet_struct *sc) -{ - uint16_t status; - int i; - int nRetired; - struct mbuf *m, *n; - - i = sc->txBdTail; - nRetired = 0; - while ((sc->txBdActiveCount != 0) - && (((status = (sc->txBdBase + i)->status) & M8xx_BD_READY) == 0)) { - /* - * See if anything went wrong - */ - if (status & (M8xx_BD_DEFER | - M8xx_BD_HEARTBEAT | - M8xx_BD_LATE_COLLISION | - M8xx_BD_RETRY_LIMIT | - M8xx_BD_UNDERRUN | - M8xx_BD_CARRIER_LOST)) { - /* - * Check for errors which stop the transmitter. - */ - if (status & (M8xx_BD_LATE_COLLISION | - M8xx_BD_RETRY_LIMIT | - M8xx_BD_UNDERRUN)) { - if (status & M8xx_BD_LATE_COLLISION) - enet_driver[0].txLateCollision++; - if (status & M8xx_BD_RETRY_LIMIT) - enet_driver[0].txRetryLimit++; - if (status & M8xx_BD_UNDERRUN) - enet_driver[0].txUnderrun++; - - /* - * Restart the transmitter - */ - /* FIXME: this should get executed only if using the SCC */ - m8xx_cp_execute_cmd (M8xx_CR_OP_RESTART_TX | M8xx_CR_CHAN_SCC1); - } - if (status & M8xx_BD_DEFER) - enet_driver[0].txDeferred++; - if (status & M8xx_BD_HEARTBEAT) - enet_driver[0].txHeartbeat++; - if (status & M8xx_BD_CARRIER_LOST) - enet_driver[0].txLostCarrier++; - } - nRetired++; - if (status & M8xx_BD_LAST) { - /* - * A full frame has been transmitted. - * Free all the associated buffer descriptors. - */ - sc->txBdActiveCount -= nRetired; - while (nRetired) { - nRetired--; - m = sc->txMbuf[sc->txBdTail]; - MFREE (m, n); - (void) n; - if (++sc->txBdTail == sc->txBdCount) - sc->txBdTail = 0; - } - } - if (++i == sc->txBdCount) - i = 0; - } -} - -/* - * reader task - */ -static void -scc_rxDaemon (void *arg) -{ - struct m8xx_enet_struct *sc = (struct m8xx_enet_struct *)arg; - struct ifnet *ifp = &sc->arpcom.ac_if; - struct mbuf *m; - uint16_t status; - m8xxBufferDescriptor_t *rxBd; - int rxBdIndex; - - /* - * Allocate space for incoming packets and start reception - */ - for (rxBdIndex = 0 ; ;) { - rxBd = sc->rxBdBase + rxBdIndex; - MGETHDR (m, M_WAIT, MT_DATA); - MCLGET (m, M_WAIT); - m->m_pkthdr.rcvif = ifp; - sc->rxMbuf[rxBdIndex] = m; - rxBd->buffer = mtod (m, void *); - rxBd->status = M8xx_BD_EMPTY | M8xx_BD_INTERRUPT; - if (++rxBdIndex == sc->rxBdCount) { - rxBd->status |= M8xx_BD_WRAP; - break; - } - } - - /* - * Input packet handling loop - */ - rxBdIndex = 0; - for (;;) { - rxBd = sc->rxBdBase + rxBdIndex; - - /* - * Wait for packet if there's not one ready - */ - if ((status = rxBd->status) & M8xx_BD_EMPTY) { - /* - * Clear old events - */ - m8xx.scc1.scce = 0x8; - - /* - * Wait for packet - * Note that the buffer descriptor is checked - * *before* the event wait -- this catches the - * possibility that a packet arrived between the - * `if' above, and the clearing of the event register. - */ - while ((status = rxBd->status) & M8xx_BD_EMPTY) { - rtems_event_set events; - - /* - * Unmask RXF (Full frame received) event - */ - m8xx.scc1.sccm |= 0x8; - - rtems_bsdnet_event_receive (INTERRUPT_EVENT, - RTEMS_WAIT|RTEMS_EVENT_ANY, - RTEMS_NO_TIMEOUT, - &events); - } - } - - /* - * Check that packet is valid - */ - if ((status & (M8xx_BD_LAST | - M8xx_BD_FIRST_IN_FRAME | - M8xx_BD_LONG | - M8xx_BD_NONALIGNED | - M8xx_BD_SHORT | - M8xx_BD_CRC_ERROR | - M8xx_BD_OVERRUN | - M8xx_BD_COLLISION)) == - (M8xx_BD_LAST | - M8xx_BD_FIRST_IN_FRAME)) { - /* - * Pass the packet up the chain. - * FIXME: Packet filtering hook could be done here. - */ - struct ether_header *eh; - - /* - * Invalidate the buffer for this descriptor - */ - rtems_cache_invalidate_multiple_data_lines((const void *)rxBd->buffer, rxBd->length); - - m = sc->rxMbuf[rxBdIndex]; - m->m_len = m->m_pkthdr.len = rxBd->length - - sizeof(uint32_t) - - sizeof(struct ether_header); - eh = mtod (m, struct ether_header *); - m->m_data += sizeof(struct ether_header); - ether_input (ifp, eh, m); - - /* - * Allocate a new mbuf - */ - MGETHDR (m, M_WAIT, MT_DATA); - MCLGET (m, M_WAIT); - m->m_pkthdr.rcvif = ifp; - sc->rxMbuf[rxBdIndex] = m; - rxBd->buffer = mtod (m, void *); - } - else { - /* - * Something went wrong with the reception - */ - if (!(status & M8xx_BD_LAST)) - sc->rxNotLast++; - if (!(status & M8xx_BD_FIRST_IN_FRAME)) - sc->rxNotFirst++; - if (status & M8xx_BD_LONG) - sc->rxGiant++; - if (status & M8xx_BD_NONALIGNED) - sc->rxNonOctet++; - if (status & M8xx_BD_SHORT) - sc->rxRunt++; - if (status & M8xx_BD_CRC_ERROR) - sc->rxBadCRC++; - if (status & M8xx_BD_OVERRUN) - sc->rxOverrun++; - if (status & M8xx_BD_COLLISION) - sc->rxCollision++; - } - - /* - * Reenable the buffer descriptor - */ - rxBd->status = (status & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) | - M8xx_BD_EMPTY; - - /* - * Move to next buffer descriptor - */ - if (++rxBdIndex == sc->rxBdCount) - rxBdIndex = 0; - } -} - -#ifdef MPC860T -static void -fec_rxDaemon (void *arg) -{ - struct m8xx_enet_struct *sc = (struct m8xx_enet_struct *)arg; - struct ifnet *ifp = &sc->arpcom.ac_if; - struct mbuf *m; - uint16_t status; - m8xxBufferDescriptor_t *rxBd; - int rxBdIndex; - - /* - * Allocate space for incoming packets and start reception - */ - for (rxBdIndex = 0 ; ;) { - rxBd = sc->rxBdBase + rxBdIndex; - MGETHDR (m, M_WAIT, MT_DATA); - MCLGET (m, M_WAIT); - m->m_pkthdr.rcvif = ifp; - sc->rxMbuf[rxBdIndex] = m; - rxBd->buffer = mtod (m, void *); - rxBd->status = M8xx_BD_EMPTY; - m8xx.fec.r_des_active = 0x1000000; - if (++rxBdIndex == sc->rxBdCount) { - rxBd->status |= M8xx_BD_WRAP; - break; - } - } - - /* - * Input packet handling loop - */ - rxBdIndex = 0; - for (;;) { - rxBd = sc->rxBdBase + rxBdIndex; - - /* - * Wait for packet if there's not one ready - */ - if ((status = rxBd->status) & M8xx_BD_EMPTY) { - /* - * Clear old events - */ - m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT; - - /* - * Wait for packet - * Note that the buffer descriptor is checked - * *before* the event wait -- this catches the - * possibility that a packet arrived between the - * `if' above, and the clearing of the event register. - */ - while ((status = rxBd->status) & M8xx_BD_EMPTY) { - rtems_event_set events; - - /* - * Unmask RXF (Full frame received) event - */ - m8xx.fec.ievent |= M8xx_FEC_IEVENT_RFINT; - - rtems_bsdnet_event_receive (INTERRUPT_EVENT, - RTEMS_WAIT|RTEMS_EVENT_ANY, - RTEMS_NO_TIMEOUT, - &events); - } - } - - /* - * Check that packet is valid - */ - if (status & M8xx_BD_LAST) { - /* - * Pass the packet up the chain. - * FIXME: Packet filtering hook could be done here. - */ - struct ether_header *eh; - - /* - * Invalidate the buffer for this descriptor - */ - rtems_cache_invalidate_multiple_data_lines((const void *)rxBd->buffer, rxBd->length); - - m = sc->rxMbuf[rxBdIndex]; - m->m_len = m->m_pkthdr.len = rxBd->length - - sizeof(uint32_t) - - sizeof(struct ether_header); - eh = mtod (m, struct ether_header *); - m->m_data += sizeof(struct ether_header); - ether_input (ifp, eh, m); - - /* - * Allocate a new mbuf - */ - MGETHDR (m, M_WAIT, MT_DATA); - MCLGET (m, M_WAIT); - m->m_pkthdr.rcvif = ifp; - sc->rxMbuf[rxBdIndex] = m; - rxBd->buffer = mtod (m, void *); - } - else { - /* - * Something went wrong with the reception - */ - if (!(status & M8xx_BD_LAST)) - sc->rxNotLast++; - if (status & M8xx_BD_LONG) - sc->rxGiant++; - if (status & M8xx_BD_NONALIGNED) - sc->rxNonOctet++; - if (status & M8xx_BD_SHORT) - sc->rxRunt++; - if (status & M8xx_BD_CRC_ERROR) - sc->rxBadCRC++; - if (status & M8xx_BD_OVERRUN) - sc->rxOverrun++; - if (status & M8xx_BD_COLLISION) - sc->rxCollision++; - } - /* - * Reenable the buffer descriptor - */ - rxBd->status = (status & M8xx_BD_WRAP) | - M8xx_BD_EMPTY; - m8xx.fec.r_des_active = 0x1000000; - /* - * Move to next buffer descriptor - */ - if (++rxBdIndex == sc->rxBdCount) - rxBdIndex = 0; - } -} -#endif - -static void -scc_sendpacket (struct ifnet *ifp, struct mbuf *m) -{ - struct m8xx_enet_struct *sc = ifp->if_softc; - volatile m8xxBufferDescriptor_t *firstTxBd, *txBd; - struct mbuf *l = NULL; - uint16_t status; - int nAdded; - - /* - * Free up buffer descriptors - */ - m8xx_Enet_retire_tx_bd (sc); - - /* - * Set up the transmit buffer descriptors. - * No need to pad out short packets since the - * hardware takes care of that automatically. - * No need to copy the packet to a contiguous buffer - * since the hardware is capable of scatter/gather DMA. - */ - nAdded = 0; - txBd = firstTxBd = sc->txBdBase + sc->txBdHead; - for (;;) { - /* - * Wait for buffer descriptor to become available. - */ - if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { - /* - * Clear old events - */ - m8xx.scc1.scce = 0x12; - - /* - * Wait for buffer descriptor to become available. - * Note that the buffer descriptors are checked - * *before* * entering the wait loop -- this catches - * the possibility that a buffer descriptor became - * available between the `if' above, and the clearing - * of the event register. - * This is to catch the case where the transmitter - * stops in the middle of a frame -- and only the - * last buffer descriptor in a frame can generate - * an interrupt. - */ - m8xx_Enet_retire_tx_bd (sc); - while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { - rtems_event_set events; - - /* - * Unmask TXB (buffer transmitted) and - * TXE (transmitter error) events. - */ - m8xx.scc1.sccm |= 0x12; - rtems_bsdnet_event_receive (INTERRUPT_EVENT, - RTEMS_WAIT|RTEMS_EVENT_ANY, - RTEMS_NO_TIMEOUT, - &events); - m8xx_Enet_retire_tx_bd (sc); - } - } - - /* - * Don't set the READY flag till the - * whole packet has been readied. - */ - status = nAdded ? M8xx_BD_READY : 0; - - /* - * FIXME: Why not deal with empty mbufs at at higher level? - * The IP fragmentation routine in ip_output - * can produce packet fragments with zero length. - * I think that ip_output should be changed to get - * rid of these zero-length mbufs, but for now, - * I'll deal with them here. - */ - if (m->m_len) { - /* - * Fill in the buffer descriptor - */ - txBd->buffer = mtod (m, void *); - txBd->length = m->m_len; - - /* - * Flush the buffer for this descriptor - */ - rtems_cache_flush_multiple_data_lines((const void *)txBd->buffer, txBd->length); - - sc->txMbuf[sc->txBdHead] = m; - nAdded++; - if (++sc->txBdHead == sc->txBdCount) { - status |= M8xx_BD_WRAP; - sc->txBdHead = 0; - } - l = m; - m = m->m_next; - } - else { - /* - * Just toss empty mbufs - */ - struct mbuf *n; - MFREE (m, n); - m = n; - if (l != NULL) - l->m_next = m; - } - - /* - * Set the transmit buffer status. - * Break out of the loop if this mbuf is the last in the frame. - */ - if (m == NULL) { - if (nAdded) { - status |= M8xx_BD_PAD | M8xx_BD_LAST | M8xx_BD_TX_CRC | M8xx_BD_INTERRUPT; - txBd->status = status; - firstTxBd->status |= M8xx_BD_READY; - sc->txBdActiveCount += nAdded; - } - break; - } - txBd->status = status; - txBd = sc->txBdBase + sc->txBdHead; - } -} - -#ifdef MPC860T -static void -fec_sendpacket (struct ifnet *ifp, struct mbuf *m) -{ - struct m8xx_enet_struct *sc = ifp->if_softc; - volatile m8xxBufferDescriptor_t *firstTxBd, *txBd; - /* struct mbuf *l = NULL; */ - uint16_t status; - int nAdded; - - /* - * Free up buffer descriptors - */ - m8xx_Enet_retire_tx_bd (sc); - - /* - * Set up the transmit buffer descriptors. - * No need to pad out short packets since the - * hardware takes care of that automatically. - * No need to copy the packet to a contiguous buffer - * since the hardware is capable of scatter/gather DMA. - */ - nAdded = 0; - txBd = firstTxBd = sc->txBdBase + sc->txBdHead; - for (;;) { - /* - * Wait for buffer descriptor to become available. - */ - if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { - /* - * Clear old events - */ - m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT; - - /* - * Wait for buffer descriptor to become available. - * Note that the buffer descriptors are checked - * *before* * entering the wait loop -- this catches - * the possibility that a buffer descriptor became - * available between the `if' above, and the clearing - * of the event register. - * This is to catch the case where the transmitter - * stops in the middle of a frame -- and only the - * last buffer descriptor in a frame can generate - * an interrupt. - */ - m8xx_Enet_retire_tx_bd (sc); - while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { - rtems_event_set events; - - /* - * Unmask TXB (buffer transmitted) and - * TXE (transmitter error) events. - */ - m8xx.fec.ievent |= M8xx_FEC_IEVENT_TFINT; - rtems_bsdnet_event_receive (INTERRUPT_EVENT, - RTEMS_WAIT|RTEMS_EVENT_ANY, - RTEMS_NO_TIMEOUT, - &events); - m8xx_Enet_retire_tx_bd (sc); - } - } - - /* - * Don't set the READY flag till the - * whole packet has been readied. - */ - status = nAdded ? M8xx_BD_READY : 0; - - /* - * FIXME: Why not deal with empty mbufs at at higher level? - * The IP fragmentation routine in ip_output - * can produce packet fragments with zero length. - * I think that ip_output should be changed to get - * rid of these zero-length mbufs, but for now, - * I'll deal with them here. - */ - if (m->m_len) { - /* - * Fill in the buffer descriptor - */ - txBd->buffer = mtod (m, void *); - txBd->length = m->m_len; - - /* - * Flush the buffer for this descriptor - */ - rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length); - - sc->txMbuf[sc->txBdHead] = m; - nAdded++; - if (++sc->txBdHead == sc->txBdCount) { - status |= M8xx_BD_WRAP; - sc->txBdHead = 0; - } - /* l = m;*/ - m = m->m_next; - } - else { - /* - * Just toss empty mbufs - */ - struct mbuf *n; - MFREE (m, n); - m = n; - /* - if (l != NULL) - l->m_next = m; - */ - } - - /* - * Set the transmit buffer status. - * Break out of the loop if this mbuf is the last in the frame. - */ - if (m == NULL) { - if (nAdded) { - status |= M8xx_BD_LAST | M8xx_BD_TX_CRC; - txBd->status = status; - firstTxBd->status |= M8xx_BD_READY; - m8xx.fec.x_des_active = 0x1000000; - sc->txBdActiveCount += nAdded; - } - break; - } - txBd->status = status; - txBd = sc->txBdBase + sc->txBdHead; - } -} -#endif - -/* - * Driver transmit daemon - */ -static void -scc_txDaemon (void *arg) -{ - struct m8xx_enet_struct *sc = (struct m8xx_enet_struct *)arg; - struct ifnet *ifp = &sc->arpcom.ac_if; - struct mbuf *m; - rtems_event_set events; - - for (;;) { - /* - * Wait for packet - */ - rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events); - - /* - * Send packets till queue is empty - */ - for (;;) { - /* - * Get the next mbuf chain to transmit. - */ - IF_DEQUEUE(&ifp->if_snd, m); - if (!m) - break; - scc_sendpacket (ifp, m); - } - ifp->if_flags &= ~IFF_OACTIVE; - } -} - -#ifdef MPC860T -void -fec_txDaemon (void *arg) -{ - struct m8xx_enet_struct *sc = (struct m8xx_enet_struct *)arg; - struct ifnet *ifp = &sc->arpcom.ac_if; - struct mbuf *m; - rtems_event_set events; - - for (;;) { - /* - * Wait for packet - */ - rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, - &events); - - /* - * Send packets till queue is empty - */ - for (;;) { - /* - * Get the next mbuf chain to transmit. - */ - IF_DEQUEUE(&ifp->if_snd, m); - if (!m) - break; - fec_sendpacket (ifp, m); - } - ifp->if_flags &= ~IFF_OACTIVE; - } -} -#endif - -/* - * Send packet (caller provides header). - */ -static void -m8xx_enet_start (struct ifnet *ifp) -{ - struct m8xx_enet_struct *sc = ifp->if_softc; - - rtems_bsdnet_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); - ifp->if_flags |= IFF_OACTIVE; -} - -/* - * Initialize and start the device - */ -static void -scc_init (void *arg) -{ - struct m8xx_enet_struct *sc = arg; - struct ifnet *ifp = &sc->arpcom.ac_if; - - if (sc->txDaemonTid == 0) { - - /* - * Set up SCC hardware - */ - m8xx_enet_initialize (sc); - - /* - * Start driver tasks - */ - sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc); - sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc); - - } - - /* - * Set flags appropriately - */ - if (ifp->if_flags & IFF_PROMISC) - m8xx.scc1.psmr |= 0x200; - else - m8xx.scc1.psmr &= ~0x200; - - /* - * Tell the world that we're running. - */ - ifp->if_flags |= IFF_RUNNING; - - /* - * Enable receiver and transmitter - */ - m8xx.scc1.gsmr_l |= 0x30; -} - -#ifdef MPC860T -static void -fec_init (void *arg) -{ - struct m8xx_enet_struct *sc = arg; - struct ifnet *ifp = &sc->arpcom.ac_if; - - if (sc->txDaemonTid == 0) { - - /* - * Set up SCC hardware - */ - m8xx_fec_initialize_hardware (sc); - - /* - * Start driver tasks - */ - sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, fec_txDaemon, sc); - sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, fec_rxDaemon, sc); - - } - - /* - * Set flags appropriately - */ - if (ifp->if_flags & IFF_PROMISC) - m8xx.fec.r_cntrl |= 0x8; - else - m8xx.fec.r_cntrl &= ~0x8; - - /* - * Tell the world that we're running. - */ - ifp->if_flags |= IFF_RUNNING; - - /* - * Enable receiver and transmitter - */ - m8xx.fec.ecntrl = 0x2; -} -#endif - -/* - * Stop the device - */ -static void -scc_stop (struct m8xx_enet_struct *sc) -{ - struct ifnet *ifp = &sc->arpcom.ac_if; - - ifp->if_flags &= ~IFF_RUNNING; - - /* - * Shut down receiver and transmitter - */ - m8xx.scc1.gsmr_l &= ~0x30; -} - -#ifdef MPC860T -static void -fec_stop (struct m8xx_enet_struct *sc) -{ - struct ifnet *ifp = &sc->arpcom.ac_if; - - ifp->if_flags &= ~IFF_RUNNING; - - /* - * Shut down receiver and transmitter - */ - m8xx.fec.ecntrl = 0x0; -} -#endif - -/* - * Show interface statistics - */ -static void -enet_stats (struct m8xx_enet_struct *sc) -{ - printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); - printf (" Not First:%-8lu", sc->rxNotFirst); - printf (" Not Last:%-8lu\n", sc->rxNotLast); - printf (" Giant:%-8lu", sc->rxGiant); - printf (" Runt:%-8lu", sc->rxRunt); - printf (" Non-octet:%-8lu\n", sc->rxNonOctet); - printf (" Bad CRC:%-8lu", sc->rxBadCRC); - printf (" Overrun:%-8lu", sc->rxOverrun); - printf (" Collision:%-8lu\n", sc->rxCollision); - printf (" Discarded:%-8lu\n", (unsigned long)m8xx.scc1p.un.ethernet.disfc); - - printf (" Tx Interrupts:%-8lu", sc->txInterrupts); - printf (" Deferred:%-8lu", sc->txDeferred); - printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); - printf (" No Carrier:%-8lu", sc->txLostCarrier); - printf ("Retransmit Limit:%-8lu", sc->txRetryLimit); - printf (" Late Collision:%-8lu\n", sc->txLateCollision); - printf (" Underrun:%-8lu", sc->txUnderrun); - printf (" Raw output wait:%-8lu\n", sc->txRawWait); -} - -/* - * Driver ioctl handler - */ -static int -scc_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_t data) -{ - struct m8xx_enet_struct *sc = ifp->if_softc; - int error = 0; - - switch (command) { - case SIOCGIFADDR: - case SIOCSIFADDR: - ether_ioctl (ifp, command, data); - break; - - case SIOCSIFFLAGS: - switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { - case IFF_RUNNING: - scc_stop (sc); - break; - - case IFF_UP: - scc_init (sc); - break; - - case IFF_UP | IFF_RUNNING: - scc_stop (sc); - scc_init (sc); - break; - - default: - break; - } - break; - - case SIO_RTEMS_SHOW_STATS: - enet_stats (sc); - break; - - /* - * FIXME: All sorts of multicast commands need to be added here! - */ - default: - error = EINVAL; - break; - } - return error; -} - -#ifdef MPC860T -static int -fec_ioctl (struct ifnet *ifp, int command, caddr_t data) -{ - struct m8xx_enet_struct *sc = ifp->if_softc; - int error = 0; - - switch (command) { - case SIOCGIFADDR: - case SIOCSIFADDR: - ether_ioctl (ifp, command, data); - break; - - case SIOCSIFFLAGS: - switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { - case IFF_RUNNING: - fec_stop (sc); - break; - - case IFF_UP: - fec_init (sc); - break; - - case IFF_UP | IFF_RUNNING: - fec_stop (sc); - fec_init (sc); - break; - - default: - break; - } - break; - - case SIO_RTEMS_SHOW_STATS: - enet_stats (sc); - break; - - /* - * FIXME: All sorts of multicast commands need to be added here! - */ - default: - error = EINVAL; - break; - } - return error; -} -#endif - -/* - * Attach an SCC driver to the system - */ -static int -rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) -{ - struct m8xx_enet_struct *sc; - struct ifnet *ifp; - int mtu; - int unitNumber; - char *unitName; -#if NVRAM_CONFIGURE == 1 - char *pAddr; - unsigned long addr; -#endif - - /* - * Parse driver name - */ - if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0) - return 0; - - /* - * Is driver free? - */ - if ((unitNumber <= 0) || (unitNumber > NIFACES)) { - printf ("Bad SCC unit number.\n"); - return 0; - } - sc = &enet_driver[unitNumber - 1]; - ifp = &sc->arpcom.ac_if; - if (ifp->if_softc != NULL) { - printf ("Driver already in use.\n"); - return 0; - } - - /* - * Process options - */ -#if NVRAM_CONFIGURE == 1 - - /* Configure from NVRAM */ - if ( (addr = nvram->ipaddr) ) { - /* We have a non-zero entry, copy the value */ - if ( (pAddr = malloc ( INET_ADDR_MAX_BUF_SIZE, 0, M_NOWAIT )) ) - config->ip_address = (char *)inet_ntop(AF_INET, &addr, pAddr, INET_ADDR_MAX_BUF_SIZE -1 ); - else - rtems_panic("Can't allocate ip_address buffer!\n"); - } - - if ( (addr = nvram->netmask) ) { - /* We have a non-zero entry, copy the value */ - if ( (pAddr = malloc ( INET_ADDR_MAX_BUF_SIZE, 0, M_NOWAIT )) ) - config->ip_netmask = (char *)inet_ntop(AF_INET, &addr, pAddr, INET_ADDR_MAX_BUF_SIZE -1 ); - else - rtems_panic("Can't allocate ip_netmask buffer!\n"); - } - - /* Ethernet address requires special handling -- it must be copied into - * the arpcom struct. The following if construct serves only to give the - * User Area NVRAM parameter the highest priority. - * - * If the ethernet address is specified in NVRAM, go ahead and copy it. - * (ETHER_ADDR_LEN = 6 bytes). - */ - if ( nvram->enaddr[0] || nvram->enaddr[1] || nvram->enaddr[2] ) { - /* Anything in the first three bytes indicates a non-zero entry, copy value */ - memcpy ((void *)sc->arpcom.ac_enaddr, &nvram->enaddr, ETHER_ADDR_LEN); - } - else if ( config->hardware_address ) { - /* There is no entry in NVRAM, but there is in the ifconfig struct, so use it. */ - memcpy ((void *)sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); - } - else { - /* There is no ethernet address provided, so it could be read - * from the Ethernet protocol block of SCC1 in DPRAM. - */ - rtems_panic("No Ethernet address specified!\n"); - } - -#else /* NVRAM_CONFIGURE != 1 */ - - if (config->hardware_address) { - memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); - } - else { - /* There is no ethernet address provided, so it could be read - * from the Ethernet protocol block of SCC1 in DPRAM. - */ - rtems_panic("No Ethernet address specified!\n"); - } - -#endif /* NVRAM_CONFIGURE != 1 */ - - if (config->mtu) - mtu = config->mtu; - else - mtu = ETHERMTU; - if (config->rbuf_count) - sc->rxBdCount = config->rbuf_count; - else - sc->rxBdCount = RX_BUF_COUNT; - if (config->xbuf_count) - sc->txBdCount = config->xbuf_count; - else - sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; - sc->acceptBroadcast = !config->ignore_broadcast; - - /* - * Set up network interface values - */ - ifp->if_softc = sc; - ifp->if_unit = unitNumber; - ifp->if_name = unitName; - ifp->if_mtu = mtu; - ifp->if_init = scc_init; - ifp->if_ioctl = scc_ioctl; - ifp->if_start = m8xx_enet_start; - ifp->if_output = ether_output; - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; - if (ifp->if_snd.ifq_maxlen == 0) - ifp->if_snd.ifq_maxlen = ifqmaxlen; - - /* - * Attach the interface - */ - if_attach (ifp); - ether_ifattach (ifp); - return 1; -}; - -#ifdef MPC860T -int -rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) -{ - struct m8xx_enet_struct *sc; - struct ifnet *ifp; - int mtu; - int unitNumber; - char *unitName; - - /* - * Parse driver name - */ - if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0) - return 0; - - /* - * Is driver free? - */ - if ((unitNumber <= 0) || (unitNumber > NIFACES)) { - printf ("Bad SCC unit number.\n"); - return 0; - } - sc = &enet_driver[unitNumber - 1]; - ifp = &sc->arpcom.ac_if; - if (ifp->if_softc != NULL) { - printf ("Driver already in use.\n"); - return 0; - } - - /* - * Process options - */ - if (config->hardware_address) { - memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); - } - else { - /* FIXME to read the enaddr from NVRAM */ - } - if (config->mtu) - mtu = config->mtu; - else - mtu = ETHERMTU; - if (config->rbuf_count) - sc->rxBdCount = config->rbuf_count; - else - sc->rxBdCount = RX_BUF_COUNT; - if (config->xbuf_count) - sc->txBdCount = config->xbuf_count; - else - sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; - sc->acceptBroadcast = !config->ignore_broadcast; - - /* - * Set up network interface values - */ - ifp->if_softc = sc; - ifp->if_unit = unitNumber; - ifp->if_name = unitName; - ifp->if_mtu = mtu; - ifp->if_init = fec_init; - ifp->if_ioctl = fec_ioctl; - ifp->if_start = m8xx_enet_start; - ifp->if_output = ether_output; - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; - if (ifp->if_snd.ifq_maxlen == 0) - ifp->if_snd.ifq_maxlen = ifqmaxlen; - - /* - * Attach the interface - */ - if_attach (ifp); - ether_ifattach (ifp); - return 1; -}; -#endif - -int -rtems_enet_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) -{ - -#ifdef MPC860T - if ((m8xx.fec.mii_data & 0xffff) == 0x2000) { -/* rtems_scc1_driver_attach(config);*/ - return rtems_fec_driver_attach(config); - } - else { -#endif - return rtems_scc1_driver_attach(config); -#ifdef MPC860T - } -#endif -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am deleted file mode 100644 index 43ca5a99a1..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am +++ /dev/null @@ -1,95 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - -$(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs -PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs - -$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h - -$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h - -$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h - -$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h - -$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h - -$(PROJECT_INCLUDE)/bsp/mbx.h: include/mbx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mbx.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mbx.h - -$(PROJECT_INCLUDE)/bsp/commproc.h: include/commproc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/commproc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/commproc.h - -$(PROJECT_INCLUDE)/bsp/8xx_immap.h: include/8xx_immap.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/8xx_immap.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/8xx_immap.h - -$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h - -$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h - -$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h - -$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds -PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds - -$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) -TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) - -$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT) -TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT) - diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/start/start.S b/c/src/lib/libbsp/powerpc/mbx8xx/start/start.S deleted file mode 100644 index 380a24d330..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/start/start.S +++ /dev/null @@ -1,434 +0,0 @@ -/* start.S - * - * This file contains the entry veneer for RTEMS programs - * on the MBX8xx board. - * It jumps to the BSP which is responsible for performing - * all remaining initialization. - * - * This file is based on several others: - * - * (1) start360.s from the gen68360 BSP by - * W. Eric Norum (eric@skatter.usask.ca) - * with the following copyright and license: - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * (2) start.s for the eth_comm port by - * Jay Monkman (jmonkman@fracsa.com), - * which itself is based on the - * - * (3) dlentry.s for the Papyrus BSP, written by: - * Andrew Bray - * with the following copyright and license: - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * (4) start860.S for the MBX821/MBX860, written by: - * Darlene A. Stewart - * Copyright (c) 1999, National Research Council of Canada - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Modifications (for MBX8xx) of respective RTEMS files: - * Copyright (c) 1999, National Research Council of Canada - */ - -#include - -/* - * The initial stack is set to run BELOW the code base address. - * (between the vectors and text sections) - * - * All the entry veneer has to do is to clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Play compiler and provide some DWARF information. - * - * CHANGE TO SUIT YOUR SETUP! - */ - - .section .entry,"ax",@progbits -.L_text_b: -.L_LC1: - .previous - -.section .debug_sfnames -.L_sfnames_b: - .byte "rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/" - .byte 0 -.L_F0: - .byte "start.S" - .byte 0 - .previous - -.section .line -.L_line_b: - .4byte .L_line_e-.L_line_b - .4byte .L_text_b -.L_LE1: -.L_line_last: - .4byte 0x0 - .2byte 0xffff - .4byte .L_text_e-.L_text_b -.L_line_e: - .previous - -.section .debug_srcinfo -.L_srcinfo_b: - .4byte .L_line_b - .4byte .L_sfnames_b - .4byte .L_text_b - .4byte .L_text_e - .4byte 0xffffffff - .4byte .L_LE1-.L_line_b - .4byte .L_F0-.L_sfnames_b - .4byte .L_line_last-.L_line_b - .4byte 0xffffffff - .previous - -.section .debug_pubnames - .4byte .L_debug_b - .4byte .L_P0 - .byte "start" - .byte 0 - .4byte 0x0 - .byte 0 - .previous - -.section .debug_aranges - .4byte .L_debug_b - .4byte .L_text_b - .4byte .L_text_e-.L_text_b - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0x0 - .4byte 0x0 - .previous - -.section .debug -.L_debug_b: -.L_D1: - .4byte .L_D1_e-.L_D1 - .2byte 0x11 /* TAG_compile_unit */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D2 - .2byte 0x38 /* AT_name */ - .byte "start.S" - .byte 0 - .2byte 0x258 /* AT_producer */ - .byte "GAS 2.5.2" - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x106 /* AT_stmt_list */ - .4byte .L_line_b - .2byte 0x1b8 /* AT_comp_dir */ - .byte "rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/" - .byte 0 - .2byte 0x8006 /* AT_sf_names */ - .4byte .L_sfnames_b - .2byte 0x8016 /* AT_src_info */ - .4byte .L_srcinfo_b -.L_D1_e: -.L_P0: -.L_D3: - .4byte .L_D3_e-.L_D3 - .2byte 0x6 /* TAG_global_subroutine */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D4 - .2byte 0x38 /* AT_name */ - .byte "start" - .byte 0 - .2byte 0x278 /* AT_prototyped */ - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x8041 /* AT_body_begin */ - .4byte .L_text_b - .2byte 0x8051 /* AT_body_end */ - .4byte .L_text_e -.L_D3_e: - -.L_D4: - .4byte .L_D4_e-.L_D4 - .align 2 -.L_D4_e: -.L_D2: - .previous - -/* - * Tell C's eabi-ctor's that we have an atexit function, - * and that it is to register __do_global_dtors. - */ - EXTERN_PROC(atexit) - PUBLIC_VAR(__atexit) - .section ".sdata","aw" - .align 2 -SYM(__atexit): - EXT_PROC_REF(atexit)@fixup - .previous - - .section ".fixup","aw" - .align 2 - EXT_SYM_REF(__atexit) - .previous - -/* That should do it */ - -/* - * Put the entry point in its own section. That way, we can guarantee - * to put it first in the .text section in the linker script. - */ - .section .entry - - PUBLIC_VAR (_start) -SYM(_start): - bl .startup /* or bl .spin */ -base_addr: - -/* - * Parameters from linker - */ -toc_pointer: - .long __GOT_START__ -bss_length: - .long bss.size -bss_addr: - .long bss.start - -PUBLIC_VAR (text_addr) -text_addr: - .long text.start - -PUBLIC_VAR (text_length) -text_length: - .long text.size - -/* - * Spin, if necessary, to acquire control from debugger (CodeWarrior). - */ -spin: - .long 0x0001 -.spin: - lis r3, spin@ha - lwz r3, spin@l(r3) - cmpwi r3, 0x1 - beq .spin -/* - * test function: blink orange led once - */ -#define LEDBLINK_DELAY (5*1000*1000) -#define LEDPORT 0xFA100001 -#define LEDMASK 0xf0 -#define LEDON 0x00 -#define LEDOFF 0x08 - - PUBLIC_VAR(ledblink) -SYM(ledblink): - lis r3,LEDBLINK_DELAY>>16 -ledblink1: - subi r3,r3,1 - cmpi 0,1,r3,0 - bne ledblink1 - /* - * turn orange led off - */ - lis r3,LEDPORT@ha - lbz r0,LEDPORT@l(r3) - andi. r0,r0,LEDMASK - ori r0,r0,LEDOFF - stb r0,LEDPORT@l(r3) - - lis r3,LEDBLINK_DELAY>>16 -ledblink2: - subi r3,r3,1 - cmpi 0,1,r3,0 - bne ledblink2 - /* - * turn orange led on - */ - lis r3,LEDPORT@ha - lbz r0,LEDPORT@l(r3) - andi. r0,r0,LEDMASK - ori r0,r0,LEDON - stb r0,LEDPORT@l(r3) - - blr -/* - * #define LOADED_BY_EPPCBUG - */ -#define LOADED_BY_EPPCBUG -#define EARLY_CONSOLE -/* - * Initialization code - */ -.startup: - /* Get the start address. */ - mflr r1 -#ifdef LOADED_BY_EPPCBUG - /* Save pointer to residual/board data */ - lis r9,eppcbugInfo@ha - stw r3,eppcbugInfo@l(r9) -#endif - /* Initialize essential registers. */ - bl initregs - nop - - /* - * C_setup. - */ - - /* set toc */ - lwz r2, toc_pointer-base_addr(r1) - - /* Set up stack pointer = beginning of text section - 56 */ - addi r1, r1, -56-4 - - /* Initialize the memory mapped MPC821 registers (done in C). */ - EXTERN_PROC (_InitMBX8xx) - bl PROC (_InitMBX8xx) - nop - - /* Clear the bss section. */ - bl bssclr - nop -#if defined(EARLY_CONSOLE) && defined(LOADED_BY_EPPCBUG) - EXTERN_PROC (serial_init) - bl PROC (serial_init) -#endif - lis r5,environ@ha - la r5,environ@l(r5) /* environp */ - /* clear argc command line */ - xor r3, r3, r3 - - EXTERN_PROC (boot_card) - bl PROC (boot_card) /* call the first C routine */ - nop - - /* we should never return from boot_card, but in case we do ... */ - /* The next instructions are dependent on your runtime environment */ - - /* Return to EPPCBug */ - lis r10, 0x0400 /* Data cache disable */ - mtspr 568, r10 - isync - - mtspr 560, r10 /* Instruction cache disable */ - isync - -stop_here: - li r10, 0x0F00 /* .RETURN */ - sc - - b stop_here - nop - -/* - * bssclr - zero out bss - */ -bssclr: - lis r3, base_addr@ha - addi r3, r3, base_addr@l - lwz r4, bss_addr-base_addr(r3) /* Start of bss */ - lwz r5, bss_length-base_addr(r3) /* Length of bss */ - - rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss - return */ - mtctr r5 /* set ctr reg */ - - li r5,0x0000 /* r5 = 0 */ -clear_bss: - stw r5,0(r4) /* store r6 */ - addi r4,r4,0x4 /* update r4 */ - bdnz clear_bss /* dec counter and loop */ - - blr /* return */ - -/* - * initregs - * Initialize the MSR and basic core PowerPC registers - * - * Register usage: - * r0 - scratch - */ -initregs: - /* - * Disable address translation. We should already be running in real space, - * so this should be a no-op, i.e. no need to switch instruction stream - * addresses from virtual space to real space. Other bits set the processor - * for big-endian mode, exceptions vectored to 0x000n_nnnn (vectors are - * already in low memory!), no execution tracing, machine check exceptions - * enabled, floating-point not available (MPC8xx has none), supervisor - * priviledge level, external interrupts disabled, power management - * disabled (normal operation mode). - */ - li r0, 0x1000 /* MSR_ME */ - mtmsr r0 /* Context-synchronizing */ - isync - - /* - * Clear the exception handling registers. - * Note SPRG3 is reserved for use by EPPCBug on the MBX8xx. - */ - li r0, 0x0000 - mtdar r0 - mtspr sprg0, r0 - mtspr sprg1, r0 - mtspr sprg2, r0 - mtspr srr0, r0 - mtspr srr1, r0 - - mr r6, r0 - mr r7, r0 - mr r8, r0 - mr r9, r0 - mr r10, r0 - mr r11, r0 - mr r12, r0 - mr r13, r0 - mr r14, r0 - mr r15, r0 - mr r16, r0 - mr r17, r0 - mr r18, r0 - mr r19, r0 - mr r20, r0 - mr r21, r0 - mr r22, r0 - mr r23, r0 - mr r24, r0 - mr r25, r0 - mr r26, r0 - mr r27, r0 - mr r28, r0 - mr r29, r0 - mr r30, r0 - mr r31, r0 - - blr /* return */ - -.L_text_e: diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c deleted file mode 100644 index 9b63afbe98..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * This routine does the bulk of the system initialization. - */ - -/* - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modifications for MBX860: - * Copyright (c) 1999, National Research Council of Canada - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -SPR_RW(SPRG1) - -int bsp_interrupt_initialize(void); - -/* - * Driver configuration parameters - */ -uint32_t bsp_clicks_per_usec; -uint32_t bsp_clock_speed; -uint32_t bsp_serial_per_sec; /* Serial clocks per second */ -bool bsp_serial_external_clock; -bool bsp_serial_xon_xoff; -bool bsp_serial_cts_rts; -uint32_t bsp_serial_rate; -uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ -uint32_t bsp_timer_least_valid; /* Least valid number from timer */ -bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ - -extern char IntrStack_start []; -extern char intrStack []; - -void BSP_panic(char *s) -{ - printk("%s PANIC %s\n",_RTEMS_version, s); - __asm__ __volatile ("sc"); -} - -void _BSP_Fatal_error(unsigned int v) -{ - printk("%s PANIC ERROR %x\n",_RTEMS_version, v); - __asm__ __volatile ("sc"); -} - -/* - * bsp_start() - * - * Board-specific initialization code. Called from the generic boot_card() - * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function - * does some of the board independent initialization. It is called from the - * MBX8xx entry point _start() defined in - * rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S - * - * _start() has set up a stack, has zeroed the .bss section, has turned off - * interrupts, and placed the processor in the supervisor mode. boot_card() - * has left the processor in that state when bsp_start() was called. - * - * RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF! - * ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL - * ADDRESSES. Software-controlled address translation would be required - * otherwise. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * Return values: NONE - */ -void bsp_start(void) -{ - /* - * Get CPU identification dynamically. Note that the get_ppc_cpu_type() - * function stores the result in global variables so that it can be used - * later... - */ - get_ppc_cpu_type(); - get_ppc_cpu_revision(); - - mmu_init(); - - /* - * Enable instruction and data caches. Do not force writethrough mode. - */ -#if NVRAM_CONFIGURE == 1 - if ( nvram->cache_mode & 0x02 ) - rtems_cache_enable_instruction(); - if ( nvram->cache_mode & 0x01 ) - rtems_cache_enable_data(); -#else -#if BSP_INSTRUCTION_CACHE_ENABLED - rtems_cache_enable_instruction(); -#endif -#if BSP_DATA_CACHE_ENABLED - rtems_cache_enable_data(); -#endif -#endif - - /* Initialize exception handler */ - ppc_exc_initialize( - (uintptr_t) IntrStack_start, - (uintptr_t) intrStack - (uintptr_t) IntrStack_start - ); - - /* Initalize interrupt support */ - bsp_interrupt_initialize(); - - /* - * initialize the device driver parameters - */ - -#if ( defined(mbx860_001b) || \ - defined(mbx860_002b) || \ - defined(mbx860_003b) || \ - defined(mbx860_003b) || \ - defined(mbx860_004b) || \ - defined(mbx860_005b) || \ - defined(mbx860_006b) || \ - defined(mbx821_001b) || \ - defined(mbx821_002b) || \ - defined(mbx821_003b) || \ - defined(mbx821_004b) || \ - defined(mbx821_005b) || \ - defined(mbx821_006b)) - bsp_clicks_per_usec = 0; /* for 32768Hz extclk */ -#else - bsp_clicks_per_usec = 1; /* for 4MHz extclk */ -#endif - rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000); - - bsp_serial_per_sec = 10000000; - bsp_serial_external_clock = true; - bsp_serial_xon_xoff = false; - bsp_serial_cts_rts = true; - bsp_serial_rate = 9600; -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - bsp_clock_speed = 50000000; - bsp_timer_average_overhead = 3; - bsp_timer_least_valid = 3; -#else - bsp_clock_speed = 40000000; - bsp_timer_average_overhead = 3; - bsp_timer_least_valid = 3; -#endif - - m8xx.scc2.sccm=0; - m8xx.scc2p.rbase=0; - m8xx.scc2p.tbase=0; - m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); - -#ifdef SHOW_MORE_INIT_SETTINGS - printk("Exit from bspstart\n"); -#endif - -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c.nocache b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c.nocache deleted file mode 100644 index c7f4718a07..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c.nocache +++ /dev/null @@ -1,107 +0,0 @@ -/* bspstart.c - * - * This set of routines starts the application. It includes application, - * board, and monitor specific initialization and configuration. - * The generic CPU dependent initialization has been performed - * before this routine is invoked. - * - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modifications for MBX860: - * Copyright (c) 1999, National Research Council of Canada - */ - -#include - -/* - * Driver configuration parameters - */ -uint32_t bsp_clicks_per_usec; -uint32_t bsp_serial_per_sec; /* Serial clocks per second */ -bool bsp_serial_external_clock; -bool bsp_serial_xon_xoff; -bool bsp_serial_cts_rts; -uint32_t bsp_serial_rate; -uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ -uint32_t bsp_timer_least_valid; /* Least valid number from timer */ -bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ - -/* - * bsp_start() - * - * Board-specific initialization code. Called from the generic boot_card() - * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function - * does some of the board independent initialization. It is called from the - * MBX8xx entry point _start() defined in - * rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S - * - * _start() has set up a stack, has zeroed the .bss section, has turned off - * interrupts, and placed the processor in the supervisor mode. boot_card() - * has left the processor in that state when bsp_start() was called. - * - * RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF! - * ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL - * ADDRESSES. Software-controlled address translation would be required - * otherwise. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * Return values: NONE - */ -void bsp_start(void) -{ - uint32_t r1; - - mmu_init(); - - /* - * Enable instruction and data caches. Do not force writethrough mode. - */ - #ifdef INSTRUCTION_CACHE_ENABLE - r1 = M8xx_CACHE_CMD_ENABLE; - _mtspr( M8xx_IC_CST, r1 ); - _isync; - #endif - - /* - * Warning: EPPCBug 1.1 chokes to death if the data cache is turned on. - * Set DATA_CACHE_ENABLE to zero in mbx8xx.cfg if EPPCBUG is used. - */ - #ifdef DATA_CACHE_ENABLE - r1 = M8xx_CACHE_CMD_ENABLE; - _mtspr( M8xx_DC_CST, r1 ); - _isync; - #endif - - /* - * initialize the device driver parameters - */ - bsp_clicks_per_usec = 1; /* for 4MHz extclk */ - bsp_serial_per_sec = 10000000; - bsp_serial_external_clock = 1; - bsp_serial_xon_xoff = 0; - bsp_serial_cts_rts = 1; - bsp_serial_rate = 9600; -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - bsp_clock_speed = 50000000; - bsp_timer_average_overhead = 3; - bsp_timer_least_valid = 3; -#else - bsp_clock_speed = 40000000; - bsp_timer_average_overhead = 3; - bsp_timer_least_valid = 3; -#endif - - m8xx.scc2.sccm=0; - m8xx.scc2p.rbase=0; - m8xx.scc2p.tbase=0; - m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); -} - diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c deleted file mode 100644 index 93fb2e9e4b..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c +++ /dev/null @@ -1,644 +0,0 @@ -/* - * imbx8xx.c - * - * MBX860/MBX821 initialization routines. - * - * Copyright (c) 1999, National Research Council of Canada - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - -/* - * EPPCBug rev 1.1 is stupid. It clears the interrupt mask register - * in the SIU when it takes control, but does not restore it before - * returning control to the program. We thus keep a copy of the - * register, and restore it from gdb using the hook facilities. - * - * We arrange for simask_copy to be initialized to zero so that - * it resides in the .data section. This avoids having gdb set - * the mask to crud before we get to initialize explicitly. Of - * course, the code will not be safely restartable, but then again, - * a lot of the library code isn't either, so there! - */ -uint32_t simask_copy = 0; - -#if 0 -/* - * The memory controller's UPMA Ram array values. - * The values in table 2-6 and 2-7 in the "MBX Series Embedded - * Controller Programmer's Reference Guide", part number MBXA/PG2, - * differ from the ones in the older MBX Programmer's Guide, part - * number MBXA/PG1. We are assuming that the values in MBXA/PG1 - * are for the older MBX boards whose part number does not have - * the "B" suffix, but we have discovered that the values from - * MBXA/PG2 work better, even for the older boards. - * - * THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and - * MBX860-002. USE WITH CARE! - * - * NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B - * as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz. - * We think the MBX821_001B is an entry level board and thus is 50 MHz, - */ -static uint32_t upmaTable[64] = { - -#if ( defined(mbx860_001b) || \ - defined(mbx821_001b) || \ - defined(mbx821_001) ) - - /* 50 MHz MBX */ - /* - * Note: For the mbx821_001, the following values (from the - * MBXA/PG2 manual) work better than, but are different - * from those published in the original MBXA/PG1 manual and - * initialized by EPPCBug 1.1. In particular, the original - * burst-write values do not work! Also, the following values - * facilitate higher performance. - */ - /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, - 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, - - /* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04, - 0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, - 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04, - 0x10AF0C04, 0xF0AFC000, 0xF3BF4805, 0xFFFFC005, - - /* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, - 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* Refresh 60ns. (offset 0x30 in UPM RAM) */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* Exception. (offset 0x3c in UPM RAM) */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 - -#elif ( defined(mbx860_002b) || \ - defined(mbx860_003b) || \ - defined(mbx860_004b) || \ - defined(mbx860_005b) || \ - defined(mbx860_006b) || \ - defined(mbx821_002b) || \ - defined(mbx821_003b) || \ - defined(mbx821_004b) || \ - defined(mbx821_005b) || \ - defined(mbx821_006b) || \ - defined(mbx860_001) || \ - defined(mbx860_002) || \ - defined(mbx860_003) || \ - defined(mbx860_004) || \ - defined(mbx860_005) || \ - defined(mbx821_002) || \ - defined(mbx821_003) || \ - defined(mbx821_004) || \ - defined(mbx821_005) ) - - /* 40 MHz MBX */ - /* - * Note: For the older MBX models (i.e. without the "b" - * suffix, e.g. mbx860_001), the following values (from the - * MBXA/PG2 manual) work better than, but are different - * from those published in the original MBXA/PG1 manual and - * initialized by EPPCBug 1.1. In particular, the following - * burst-read and burst-write values facilitate higher - * performance. - */ - /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, - 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */ - 0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x33FF4804, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */ - 0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* Refresh 60ns. (offset 0x30 in UPM RAM) */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* Exception. (offset 0x3c in UPM RAM) */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 -#else -#error "MBX board model not specified." -#endif -}; -#endif - -#if ( !defined(EPPCBUG_VECTORS) ) - extern uint32_t simask_copy; -#endif - -/* - * Initialize MBX8xx - */ -void _InitMBX8xx (void) -{ - register uint32_t r1; - - /* - * Initialize the Debug Enable Register (DER) to an appropriate - * value for EPPCBug debugging. - * (This value should also work for BDM debugging.) - */ - r1 = 0x70C67C07; /* All except EXTIE, ALIE, DECIE */ - _mtspr( M8xx_DER, r1 ); - - /* - * Initialize the Instruction Support Control Register (ICTRL) to a - * an appropriate value for normal operation. A different value, - * such as 0x0, may be more appropriate for debugging. - */ - r1 = 0x00000007; - _mtspr( M8xx_ICTRL, r1 ); - - /* - * Disable and invalidate the instruction and data caches. - */ - r1 = M8xx_CACHE_CMD_DISABLE; - _mtspr( M8xx_IC_CST, r1 ); - _isync; - r1 = M8xx_CACHE_CMD_UNLOCKALL; - _mtspr( M8xx_IC_CST, r1 ); - _isync; - r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ - _mtspr( M8xx_IC_CST, r1 ); - _isync; - - r1 = M8xx_CACHE_CMD_DISABLE; - _mtspr( M8xx_DC_CST, r1 ); - _isync; - r1 = M8xx_CACHE_CMD_UNLOCKALL; - _mtspr( M8xx_DC_CST, r1 ); - _isync; - r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ - _mtspr( M8xx_DC_CST, r1 ); - _isync; - - /* - * Initialize the Internal Memory Map Register (IMMR) - * - * Use the value in MBXA/PG2, which is also the value that EPPC-Bug - * programmed into our boards. The alternative is the value in - * MBXA/PG1: 0xFFA00000. This value might well depend on the revision - * of the firmware. - * - * THIS VALUE IS ALSO DECLARED IN THE linkcmds FILE and mmutlbtab.c! - */ - r1 = 0xFA200000; - _mtspr( M8xx_IMMR, r1 ); - - /* - * Get the SIU interrupt mask. - * imd: accessing m8xx.* should not occure before setting up the immr ! - */ - simask_copy = m8xx.simask; - - /* - * Initialize the SIU Module Configuration Register (SIUMCR) - * m8xx.siumcr = 0x00602900, the default MBX and firmware value. - */ - m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | - M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME; - - /* - * Initialize the System Protection Control Register (SYPCR). - * The SYPCR can only be written once after Reset. - * - Enable bus monitor - * - Disable software watchdog timer - * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value. - */ - m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | - M8xx_SYPCR_BME | M8xx_SYPCR_SWF; - - /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */ - m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */ - - /* Initialize the Transfer Error Status Register (TESR) */ - m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */ - - /* Initialize the SDMA Configuration Register (SDCR) */ - m8xx.sdcr = 0x00000001; /* Default firmware value. */ - - /* - * Initialize the Timebase Status and Control Register (TBSCR) - * m8xx.tbscr = 0x00C3, default MBX and firmware value. - */ - m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */ - m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | - M8xx_TBSCR_TBF | M8xx_TBSCR_TBE; - - /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */ - m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */ - m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */ - - /* Unlock other Real-Time Clock registers */ - m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */ - m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */ - m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */ - - /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */ - m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */ - m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ - - /* Initialize the System Clock and Reset Control Register (SCCR) - * Set the clock sources and division factors: - * Timebase Source is GCLK2 / 16 - * Real-Time Clock Select is EXTCLK (4.192MHz) - * Real-Time Clock Divide is /4 - */ - m8xx.sccrk = M8xx_UNLOCK_KEY; /* unlock SCCR */ - m8xx.sccr = 0x02800000; /* for MBX860/MBX821 */ - -#if 0 /* IMD hack: do not init PLL after EPPCbug load */ - /* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */ - /* - set the clock speed and set normal power mode */ - m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */ -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.plprcr = 0x5F500000; -#elif ( defined(mbx860_005b) || \ - defined(mbx860_002b) || \ - defined(mbx860_003b) || \ - defined(mbx860_004b) || \ - defined(mbx860_006b) || \ - defined(mbx821_002b) || \ - defined(mbx821_003b) || \ - defined(mbx821_004b) || \ - defined(mbx821_005b) || \ - defined(mbx821_006b) ) - /* Set the multiplication factor to 0 and clear the timer interrupt status*/ - m8xx.plprcr = 0x00005000; -#elif ( defined(mbx860_001) || \ - defined(mbx860_002) || \ - defined(mbx860_003) || \ - defined(mbx860_004) || \ - defined(mbx860_005) || \ - defined(mbx821_002) || \ - defined(mbx821_003) || \ - defined(mbx821_004) || \ - defined(mbx821_005)) - m8xx.plprcr = 0x4C400000; -#else -#error "MBX board not defined" -#endif -#endif - /* Unlock the timebase and decrementer registers. */ - m8xx.tbk = M8xx_UNLOCK_KEY; - /* - * Initialize decrementer register to a large value to - * guarantee that a decrementer interrupt will not be - * generated before the kernel is fully initialized. - */ - r1 = 0x7FFFFFFF; - _mtspr( M8xx_DEC, r1 ); - - /* Initialize the timebase register (TB is 64 bits) */ - r1 = 0x00000000; - _mtspr( M8xx_TBU_WR, r1 ); - _mtspr( M8xx_TBL_WR, r1 ); - -#if 0 /* IMD hack: do not init UPMs after EPPCbug load */ - /* - * Memory Controller Initialization - */ - - /* - * User Programmable Machine A (UPMA) Initialization - * - * If this initialization code is running from DRAM, it is very - * dangerous to change the value of any UPMA Ram array word from - * what the firmware (EPPCBug) initialized it to. Thus we don't - * initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug - * has done the appropriate initialization. - * - * An exception to our rule, is that, for the older MBX boards - * (those without the "B" suffix, e.g. MBX821-001 and MBX860-002), - * we do re-initialize the burst-read and burst-write values with - * values that are more efficient. Also, in the MBX821 case, - * the burst-write original values set by EPPCBug do not work! - * This change can be done safely because the caches have not yet - * been activated. - * - * The RAM array of UPMA is initialized by writing to each of - * its 64 32-bit RAM locations. - * Note: UPM register initialization should occur before - * initialization of the corresponding BRx and ORx registers. - */ -#if ( !defined(EPPCBUG_VECTORS) ) - for( i = 0; i < 64; ++i ) { - m8xx.mdr = upmaTable[i]; - m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i); - } -#elif ( defined(mbx860_001) || \ - defined(mbx860_002) || \ - defined(mbx860_003) || \ - defined(mbx860_004) || \ - defined(mbx860_005) || \ - defined(mbx821_001) || \ - defined(mbx821_002) || \ - defined(mbx821_003) || \ - defined(mbx821_004) || \ - defined(mbx821_005) ) - /* Replace the burst-read and burst-write values with better ones. */ - /* burst-read values */ - for( i = 8; i < 24; ++i ) { - m8xx.mdr = upmaTable[i]; - m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i); - } - /* burst-write values */ - for( i = 32; i < 48; ++i ) { - m8xx.mdr = upmaTable[i]; - m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i); - } -#endif - -#if ( !defined(EPPCBUG_VECTORS) ) - /* - * Initialize the memory periodic timer. - * Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) - * m8xx.mptpr = 0x0200; - */ - m8xx.mptpr = M8xx_MPTPR_PTP(0x2); - - /* - * Initialize the Machine A Mode Register (MAMR) - * - * ASSUMES THAT DIMMs ARE NOT INSTALLED! - * - * Without DIMMs: - * m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz). - * - * With DIMMs: - * m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz). - */ -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | - M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; -#else - m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | - M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; -#endif -#endif /* ! defined(EPPCBUG_VECTORS) */ - - /* - * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7) - * Note: For all chip selects, ORx should be programmed before BRx, - * except when programming the boot chip select (CS0) after hardware - * reset, in which case, BR0 should be programmed before OR0. - * - * MPC860/MPX821 Memory Map Summary: - * S-ADDR E-ADDR CS PS PE WP MS BI V DESCRIPTION - * FE000000 FE7FFFFF 0 32 N N GPCM Y Y Soldered FLASH Memory - * 00000000 00zFFFFF 1 32 N N UPMA N Y Local DRAM Memory - * 00X00000 0XXXXXXX 2 0 N N UPMA N N DIMM Memory - Bank #0 - * 00X00000 0XXXXXXX 3 0 N N UPMA N N DIMM Memory - Bank #1 - * FA000000 FA1FFFFF 4 8 N N GPCM Y Y NVRAM & BCSR - * 80000000 DFFFFFFF 5 32 N N GPCM Y Y PCI/ISA I/O & Memory - * FA210000 FA21FFFF 6 32 N N GPCM Y Y QSpan Registers - * FC000000 FC7FFFFF 7 8 N N GPCM Y Y Socketed FLASH Memory - * - * z = 3 for 4MB installed on the motherboard, z = F for 16M - * - * NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4. - * This table assumes that the 32-bit soldered flash device is the boot ROM. - */ - - /* - * CS0 : Soldered (32-bit) Flash Memory at 0xFE000000 - * - * CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING! - * (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to - * access whatever flash device is not selected during hard reset.) - * - * MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that - * "EPPCBUG configures the reset flash device at the lower address, and the - * nonreset flash device at the higher address." If we take reset flash device - * to mean the boot flash memory, then the statement must mean that BR0 must - * point to the device at the lower address, i.e. 0xFC000000, while BR7 must - * point to the device at the highest address, i.e. 0xFE000000. - * - * THIS IS NOT THE CASE! - * - * The boot flash is always configured to start at 0xFE000000, and the other - * one to start at 0xFC000000. Changing jumper J4 only changes the width of - * the memory ports into these two region. - * - * BR0 = 0xFE000001 - * Base addr [0-16] 0b11111110000000000 = 0xFE000000 - * Address type [17-19] 0b000 - * Port size [20-21] 0b00 = 32 bits - * Parity enable [22] 0b0 = disabled - * Write protect [23] 0b0 = r/w - * Machine select [24-25] 0b00 = GPCM - * Reserved [26-30] 0b00000 - * Valid Bit [31] 0b1 = this bank is valid - * OR0 = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz - * Address mask [0-16] 0b11111111100000000 = 0xFF800000 - * Addr type mask [17-19] 0b000 = no address-type protection - * CS negation time [20] 0b1 - * ACS [21-22] 0b00 = CS output at same time as address lines - * Burst inhibit [23] 0b1 = bank does not support burst accesses - * Cycle length [24-27] 0b0011/0b0100 = 3/4 clock cycle wait states - * SETA [28] 0b0 = TA generated internally - * Timing relaxed [29] 0b0 = not relaxed - * Extended hold time [30] 0b0 = not extended - * Reserved [31] 0b0 - * - * m8xx.memc[0]._or = 0xFF800930 (40 MHz) - * m8xx.memc[0]._or = 0xFF800940 (50 MHz) - * m8xx.memc[0]._br = 0xFE000001 - */ -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | - M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(4); -#else - m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | - M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3); -#endif - m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | - M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - - /* - * CS1 : Local DRAM Memory at 0x00000000 - * m8xx.memc[1]._or = 0xFFC00400; - * m8xx.memc[1]._br = 0x00000081; - */ -#if ( defined(mbx860_001b) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | - M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); -#elif ( defined(mbx860_002b) || \ - defined(mbx860_003b) || \ - defined(mbx821_001b) || \ - defined(mbx821_002b) || \ - defined(mbx821_003b) || \ - defined(mbx860_001) || \ - defined(mbx860_002) || \ - defined(mbx860_003) || \ - defined(mbx821_001) || \ - defined(mbx821_002) || \ - defined(mbx821_003) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | - M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); -#elif ( defined(mbx860_004) || \ - defined(mbx860_005) || \ - defined(mbx860_004b) || \ - defined(mbx860_005b) || \ - defined(mbx860_006b) || \ - defined(mbx821_004) || \ - defined(mbx821_005) || \ - defined(mbx821_004b) || \ - defined(mbx821_005b) || \ - defined(mbx821_006b) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | - M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); -#else -#error "MBX board not defined" -#endif - m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | - M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V; - - /* - * CS2 : DIMM Memory - Bank #0, not present - * m8xx.memc[2]._or = 0x00000400; - * m8xx.memc[2]._br = 0x00000080; - */ - m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | - M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); - m8xx.memc[2]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | - M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ - - /* - * CS3 : DIMM Memory - Bank #1, not present - * m8xx.memc[3]._or = 0x00000400; - * m8xx.memc[3]._br = 0x00000080; - */ - m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | - M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); - m8xx.memc[3]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | - M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ - - /* - * CS4 : Battery-Backed SRAM at 0xFA000000 - * m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz - * m8xx.memc[4]._br = 0xFA000401; - */ -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.memc[4]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | - M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3); -#else - m8xx.memc[4]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | - M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(2); -#endif - m8xx.memc[4]._br = M8xx_BR_BA(0xFA000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 | - M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - - /* - * CS5 : PCI I/O and Memory at 0x80000000 - * m8xx.memc[5]._or = 0xA0000108; - * m8xx.memc[5]._br = 0x80000001; - */ - m8xx.memc[5]._or = 0xA0000000 | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_NORM | - M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(0) | M8xx_MEMC_OR_SETA; - m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | - M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - - /* - * CS6 : QSPAN Registers at 0xFA210000 - * m8xx.memc[6]._or = 0xFFFF0108; - * m8xx.memc[6]._br = 0xFA210001; - */ - m8xx.memc[6]._or = M8xx_MEMC_OR_64K | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_NORM | - M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(0) | M8xx_MEMC_OR_SETA; - m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | - M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - - /* - * CS7 : Socketed (8-bit) Flash at 0xFC000000 - * m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz - * m8xx.memc[7]._br = 0xFC000401; - */ -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.memc[7]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | - M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(4); -#else - m8xx.memc[7]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | - M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3); -#endif - m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 | - M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; -#endif /* IMD hack */ - /* - * PCMCIA initialization - */ - /* - * PCMCIA region 0: common memory - */ - m8xx.pbr0 = PCMCIA_MEM_ADDR; - m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_MEM - |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); - /* - * PCMCIA region 1: dma memory - */ - m8xx.pbr1 = PCMCIA_DMA_ADDR; - m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_DMA - |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); - /* - * PCMCIA region 2: attribute memory - */ - m8xx.pbr2 = PCMCIA_ATTRB_ADDR; - m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_ATT - |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); - /* - * PCMCIA region 3: I/O access - */ - m8xx.pbr3 = PCMCIA_IO_ADDR; - m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_IO - |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); - - /* - * PCMCIA interface general control reg - */ - m8xx.pgcra = 0; /* no special options set */ - /* - * PCMCIA interface enable reg - */ - m8xx.per =0; /* no interrupts enabled now */ -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds b/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds deleted file mode 100644 index 537e4db664..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds +++ /dev/null @@ -1,333 +0,0 @@ -/* - * This file contains directives for the GNU linker that are specific - * to the MBX860-2 board. - */ - -OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc") -OUTPUT_ARCH(powerpc) -ENTRY(_start) - -/* - * Declare some sizes. - * XXX: The assignment of ". += XyzSize;" fails in older gld's if the - * number used there is not constant. If this happens to you, edit - * the lines marked XXX below to use a constant value. - */ -StackSize = DEFINED(StackSize) ? StackSize : 0x1000; -RamBase = DEFINED(RamBase) ? RamBase : 0; -RamSize = DEFINED(RamSize) ? RamSize : 4M; -HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0; - -MEMORY - { - ram : org = 0x0, l = 4M - nvram : org = 0xfa000000, l = 32K - dpram : org = 0xfa200000, l = 16K - flash : org = 0xfc000000, l = 2M - immr : org = 0xfa200000, l = 16K - } - - -SECTIONS -{ - /* - * If the vectors are specified statically rather than created at run time, - * accumulate them starting at VMA 0x0. - */ - .vectors : - { - *(.vectors) - } >ram - - /* - * The stack will live in this area - between the vectors and - * the text section. - */ - - .text 0x10000: - { - /* Read-only sections, merged into text segment: */ - - text.start = .; - - /* Entry point is the .entry section */ - *(.entry) - *(.entry2) - - /* Actual code */ - *(.text*) - - /* C++ constructors/destructors */ - *(.gnu.linkonce.t*) - - /* Initialization and finalization code. - * - * Various files can provide initialization and finalization functions. - * The bodies of these functions are in .init and .fini sections. We - * accumulate the bodies here, and prepend function prologues from - * ecrti.o and function epilogues from ecrtn.o. ecrti.o must be linked - * first; ecrtn.o must be linked last. Because these are wildcards, it - * doesn't matter if the user does not actually link against ecrti.o and - * ecrtn.o; the linker won't look for a file to match a wildcard. The - * wildcard also means that it doesn't matter which directory ecrti.o - * and ecrtn.o are in. - */ - PROVIDE (_init = .); - *ecrti.o(.init) - *(.init) - *ecrtn.o(.init) - - PROVIDE (_fini = .); - *ecrti.o(.fini) - *(.fini) - *ecrtn.o(.init) - - /* - * C++ constructors and destructors for static objects. - * PowerPC EABI does not use crtstuff yet, so we build "old-style" - * constructor and destructor lists that begin with the list lenght - * end terminate with a NULL entry. - */ - - PROVIDE (__CTOR_LIST__ = .); - /* LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) */ - *crtbegin.o(.ctors) - *(.ctors) - *crtend.o(.ctors) - LONG(0) - PROVIDE (__CTOR_END__ = .); - - PROVIDE (__DTOR_LIST__ = .); - /* LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) */ - *crtbegin.o(.dtors) - *(.dtors) - *crtend.o(.dtors) - LONG(0) - PROVIDE (__DTOR_END__ = .); - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - __start_set_sysctl_set = .; - *(set_sysctl_*); - __stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - /* Exception frame info */ - *(.eh_frame) - - /* Miscellaneous read-only data */ - _rodata_start = . ; - *(.gnu.linkonce.r*) - *(.lit) - *(.shdata) - *(.rodata*) - *(.rodata1) - KEEP (*(SORT(.rtemsroset.*))) - *(.descriptors) - *(rom_ver) - _erodata = .; - - - /* Various possible names for the end of the .text section */ - etext = ALIGN(0x10); - _etext = .; - _endtext = .; - text.end = .; - PROVIDE (etext = .); - PROVIDE (__etext = .); - } > ram - - .tdata : { - _TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - _TLS_Data_end = .; - } >ram - - .tbss : { - _TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - _TLS_BSS_end = .; - } >ram - - _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; - _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; - _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; - _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; - _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; - _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .rel.dyn : - { - *(.rel.init) - *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) - *(.rel.fini) - *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) - *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) - *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) - *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) - *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) - *(.rel.ctors) - *(.rel.dtors) - *(.rel.got) - *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) - *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) - *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) - *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) - *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) - } >ram - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.got1) - *(.rela.got2) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - - /* R/W Data */ - .data : - { - data_start = .; - - *(.data) - *(.data.*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.data1) - - PROVIDE (__EXCEPT_START__ = .); - *(.gcc_except_table*) - PROVIDE (__EXCEPT_END__ = .); - - PROVIDE(__GOT_START__ = .); - *(.got.plt) - *(.got) - PROVIDE(__GOT_END__ = .); - - *(.got1) - - PROVIDE (__GOT2_START__ = .); - PROVIDE (_GOT2_START_ = .); - *(.got2) - PROVIDE (__GOT2_END__ = .); - PROVIDE (_GOT2_END_ = .); - - PROVIDE (__FIXUP_START__ = .); - PROVIDE (_FIXUP_START_ = .); - *(.fixup) - PROVIDE (_FIXUP_END_ = .); - PROVIDE (__FIXUP_END__ = .); - } > ram - - .sdata : { - PROVIDE (_SDA_BASE_ = 32768); - *(.sdata .sdata.* .gnu.linkonce.s.*) - } > ram - - .sbss : { - __bss_start = .; - - PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .); - *(.scommon) - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .); - } > ram - - .sdata2 : { - PROVIDE (_SDA2_BASE_ = 32768); - - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram =0 - - .sbss2 : { - *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) - } > ram =0 - - .bss : - { - bss.start = .; - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - . = ALIGN(4); - bss.end = .; - - } > ram - - bss.size = bss.end - bss.start; - text.size = text.end - text.start; - PROVIDE(_end = bss.end); - /* - * Interrupt stack setup - */ - - IntrStack_start = ALIGN(0x10); - . += 0x4000; - intrStack = .; - PROVIDE(intrStackPtr = intrStack); - - WorkAreaBase = .; - - dpram : - { - m8xx = .; - _m8xx = .; - /* . += (16 * 1024); this makes the mbx loader crash */ - } >immr - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c deleted file mode 100644 index c7001fff7f..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * mmutlbtab.c - * - * This file defines the MMU_TLB_table for the MBX8xx. - * - * Copyright (c) 1999, National Research Council of Canada - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -/* - * This MMU_TLB_table is used to statically initialize the Table Lookaside - * Buffers in the MMU of the MBX8xx board. - * - * We initialize the entries in both the instruction and data TLBs - * with the same values - a few bits relevant to the data TLB are unused - * in the instruction TLB. - * - * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and - * Real Page Number (RPN) value are supplied in the table for each TLB entry. - * - * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must - * not have more than 32 lines in it! - * - * We set up the virtual memory map so that virtual address of a - * location is equal to its real address. - */ -MMU_TLB_table_t MMU_TLB_table[] = { -#if ( defined(mbx860_001b) || \ - defined(mbx860_002b) || \ - defined(mbx860_003b) || \ - defined(mbx821_001b) || \ - defined(mbx821_002b) || \ - defined(mbx821_003b) || \ - defined(mbx860_001) || \ - defined(mbx860_002) || \ - defined(mbx860_003) || \ - defined(mbx821_001) || \ - defined(mbx821_002) || \ - defined(mbx821_003) ) - /* - * DRAM: CS1, Start address 0x00000000, 4M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, - * R/W,X for all, no ASID comparison, not cache-inhibited. - * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. - * EPN TWC RPN - */ - { 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */ - { 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */ - { 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */ - { 0x00180200, 0x05, 0x001809FD }, /* DRAM - PS=512K */ - { 0x00200200, 0x05, 0x002009FD }, /* DRAM - PS=512K */ - { 0x00280200, 0x05, 0x002809FD }, /* DRAM - PS=512K */ - { 0x00300200, 0x05, 0x003009FD }, /* DRAM - PS=512K */ - { 0x00380200, 0x05, 0x003809FF }, /* DRAM - PS=512K, cache-inhibited */ -#elif ( defined(mbx860_004) || \ - defined(mbx860_005) || \ - defined(mbx860_004b) || \ - defined(mbx860_005b) || \ - defined(mbx860_006b) || \ - defined(mbx821_004) || \ - defined(mbx821_005) || \ - defined(mbx821_004b) || \ - defined(mbx821_005b) || \ - defined(mbx821_006b) ) - /* - * DRAM: CS1, Start address 0x00000000, 16M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, - * R/W,X for all, no ASID comparison, not cache-inhibited. - * EPN TWC RPN - */ - { 0x00000200, 0x0D, 0x000009FD }, /* DRAM - PS=8M */ - { 0x00800200, 0x0D, 0x008009FD }, /* DRAM - PS=8M */ -#else -#error "MBX board not defined" -#endif - /* - * - * NVRAM: CS4, Start address 0xFA000000, 32K, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, - * R/W,X for all, no ASID comparison, cache-inhibited. - * - * EPN TWC RPN - */ - { 0xFA000200, 0x01, 0xFA0009FF }, /* NVRAM - PS=16K */ - { 0xFA004200, 0x01, 0xFA0049FF }, /* NVRAM - PS=16K */ - /* - * - * Board Control/Status Register #1/#2: CS4, Start address 0xFA100000, (4 x 8 bits?) - * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, - * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC RPN - */ - { 0xFA100200, 0x13, 0xFA1009F7 }, /* BCSR - PS=4K */ - /* - * - * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K, - * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, - * R/W,X for all, no ASID comparison, cache-inhibited. - * - * Note: We use the value in MBXA/PG2, which is also the value that - * EPPC-Bug programmed into our boards. The alternative is the value - * in MBXA/PG1: 0xFFA00000. This value might well depend on the revision - * of the firmware. - * EPN TWC RPN - */ - { 0xFA200200, 0x13, 0xFA2009FF }, /* IMMR - PS=16K */ - /* - * - * Flash: CS0, Start address 0xFE000000, 4M, (BootROM-EPPCBug) - * ASID=0x0, APG=0x0, not guarded memory, - * R/O,X for all, no ASID comparison, not cache-inhibited. - * EPN TWC RPN - */ - { 0xFE000200, 0x05, 0xFE000CFD }, /* Flash - PS=512K */ - { 0xFE080200, 0x05, 0xFE080CFD }, /* Flash - PS=512K */ - { 0xFE100200, 0x05, 0xFE100CFD }, /* Flash - PS=512K */ - { 0xFE180200, 0x05, 0xFE180CFD }, /* Flash - PS=512K */ - { 0xFE200200, 0x05, 0xFE200CFD }, /* Flash - PS=512K */ - { 0xFE280200, 0x05, 0xFE280CFD }, /* Flash - PS=512K */ - { 0xFE300200, 0x05, 0xFE300CFD }, /* Flash - PS=512K */ - { 0xFE380200, 0x05, 0xFE380CFD }, /* Flash - PS=512K */ - /* - * BootROM: CS7, Start address 0xFC000000, 4M?, (socketed FLASH) - * ASID=0x0, APG=0x0, not guarded memory, - * R/O,X for all, no ASID comparison, not cache-inhibited. - * EPN TWC RPN - */ - { 0xFC000200, 0x05, 0xFC000CFD }, /* BootROM - PS=512K */ - /* - * - * PCI/ISA I/O Space: CS5, Start address 0x80000000, 512M? - * ASID=0x0, APG=0x0, guarded memory, - * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC RPN - */ - { 0x80000200, 0x1D, 0x800009FF }, /* PCI I/O - PS=8M */ - /* - * - * PCI/ISA Memory Space: CS5, Start address 0xC0000000, 512M? - * ASID=0x0, APG=0x0, guarded memory, - * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC RPN - */ - { 0xC0000200, 0x1D, 0xC00009FF }, /* PCI Memory - PS=8M */ - /* - * - * PCI Bridge/QSPAN Registers: CS6, Start address 0xFA210000, 4K - * ASID=0x0, APG=0x0, guarded memory, - * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC RPN - */ - { 0xFA210200, 0x11, 0xFA2109F7 }, /* QSPAN - PS=4K */ - /* - * - * PCMCIA Spaces: Start address 0xE0000000, 256M? - * For each space (MEM/DMA/ATTRIB/IO) only the first 8MB are mapped - * ASID=0x0, APG=0x0, guarded memory, - * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC - * RPN - */ - { (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D, - (PCMCIA_MEM_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA Memory - PS=8M */ - - { (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D, - (PCMCIA_DMA_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA DMA - PS=8M */ - - { (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D, - (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA ATTRIB-PS=8M*/ - - { (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D, - (PCMCIA_IO_ADDR & 0xfffff000) | 0x9F7 } /* PCMCIA I/O - PS=8M */ -}; - -/* - * MMU_N_TLB_Table_Entries is defined here because the size of the - * MMU_TLB_table is only known in this file. - */ -int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) ); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/times-mbx821 b/c/src/lib/libbsp/powerpc/mbx8xx/times-mbx821 deleted file mode 100644 index 36c5e82066..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/times-mbx821 +++ /dev/null @@ -1,187 +0,0 @@ -# -# Timing Test Suite Results for the MBX821-001 -# - -Board: MBX821 -CPU: MPC821 -Clock Speed: 50 MHz -Memory Configuration: 4Mb EDO, 60ns DRAM -Wait States: - -Times Reported in: clock ticks -Timer Source: Timebase register (TMBCLK = (cpu clock speed / 16) = 3.125MHz) - -Column A: Data & instruction caches disabled (2000-05-04) -Column B: Data & instruction caches enabled (UPM/A: new burst r/w values) (2000-05-04) - -# DESCRIPTION A B -== ================================================================= ==== ==== - 1 rtems_semaphore_create 181 79 - rtems_semaphore_delete 196 55 - rtems_semaphore_obtain: available 128 12 - rtems_semaphore_obtain: not available -- NO_WAIT 128 12 - rtems_semaphore_release: no waiting tasks 162 16 - - 2 rtems_semaphore_obtain: not available -- caller blocks 405 113 - - 3 rtems_semaphore_release: task readied -- preempts caller 317 72 - - 4 rtems_task_restart: blocked task -- preempts caller 549 156 - rtems_task_restart: ready task -- preempts caller 539 150 - rtems_semaphore_release: task readied -- returns to caller 201 25 - rtems_task_create 585 153 - rtems_task_start 257 67 - rtems_task_restart: suspended task -- returns to caller 309 83 - rtems_task_delete: suspended task 555 118 - rtems_task_restart: ready task -- returns to caller 317 85 - rtems_task_restart: blocked task -- returns to caller 374 113 - rtems_task_delete: blocked task 571 130 - - 5 rtems_task_suspend: calling task 314 63 - rtems_task_resume: task readied -- preempts caller 263 49 - - 6 rtems_task_restart: calling task 385 53 - rtems_task_suspend: returns to caller 132 18 - rtems_task_resume: task readied -- returns to caller 145 20 - rtems_task_delete: ready task 574 135 - - 7 rtems_task_restart: suspended task -- preempts caller 505 111 - - 8 rtems_task_set_priority: obtain current priority 111 11 - rtems_task_set_priority: returns to caller 207 20 - rtems_task_mode: obtain current mode 56 6 - rtems_task_mode: no reschedule 70 8 - rtems_task_mode: reschedule -- returns to caller 75 32 - rtems_task_mode: reschedule -- preempts caller 292 97 - rtems_clock_set 250 25 - rtems_clock_get 6 1 - - 9 rtems_message_queue_create 751 320 - rtems_message_queue_send: no waiting tasks 241 33 - rtems_message_queue_urgent: no waiting tasks 238 39 - rtems_message_queue_receive: available 229 29 - rtems_message_queue_flush: no messages flushed 104 12 - rtems_message_queue_flush: messages flushed 127 12 - rtems_message_queue_delete 242 83 - -10 rtems_message_queue_receive: not available -- NO_WAIT 147 16 - rtems_message_queue_receive: not available -- caller blocks 416 94 - -11 rtems_message_queue_send: task readied -- preempts caller 377 82 - -12 rtems_message_queue_send: task readied -- returns to caller 262 50 - -13 rtems_message_queue_urgent: task readied -- preempts caller 377 85 - -14 rtems_message_queue_urgent: task readied -- returns to caller 262 43 - -15 rtems_event_receive: obtain current events 10 1 - rtems_event_receive: not available -- NO_WAIT 102 9 - rtems_event_receive: not available -- caller blocks 346 76 - rtems_event_send: no task readied 104 10 - rtems_event_receive: available 105 24 - rtems_event_send: task readied -- returns to caller 181 26 - -16 rtems_event_send: task readied -- preempts caller 308 78 - -17 rtems_task_set_priority: preempts caller 408 76 - -18 rtems_task_delete: calling task 749 174 - -19 rtems_signal_catch 75 9 - rtems_signal_send: returns to caller 120 35 - rtems_signal_send: signal to self 198 74 - exit ASR overhead: returns to calling task 158 63 - exit ASR overhead: returns to preempting task 249 65 - -20 rtems_partition_create 247 102 - rtems_region_create 196 78 - rtems_partition_get_buffer: available 117 26 - rtems_partition_get_buffer: not available 110 10 - rtems_partition_return_buffer 127 30 - rtems_partition_delete 145 31 - rtems_region_get_segment: available 156 19 - rtems_region_get_segment: not available -- NO_WAIT 143 36 - rtems_region_return_segment: no waiting tasks 167 15 - rtems_region_get_segment: not available -- caller blocks 429 167 - rtems_region_return_segment: task readied -- preempts caller 418 142 - rtems_region_return_segment: task readied -- returns to caller 298 71 - rtems_region_delete 146 25 - rtems_io_initialize 13 2 - rtems_io_open 9 1 - rtems_io_close 9 1 - rtems_io_read 9 1 - rtems_io_write 9 1 - rtems_io_control 9 1 - -21 rtems_task_ident 1143 139 - rtems_message_queue_ident 1115 141 - rtems_semaphore_ident 1285 158 - rtems_partition_ident 1115 132 - rtems_region_ident 1137 144 - rtems_port_ident 1115 133 - rtems_timer_ident 1117 140 - rtems_rate_monotonic_ident 1116 136 - -22 rtems_message_queue_broadcast: task readied -- returns to caller 281 84 - rtems_message_queue_broadcast: no waiting tasks 177 17 - rtems_message_queue_broadcast: task readied -- preempts caller 398 114 - -23 rtems_timer_create 127 15 - rtems_timer_fire_after: inactive 191 23 - rtems_timer_fire_after: active 204 24 - rtems_timer_cancel: active 118 15 - rtems_timer_cancel: inactive 104 13 - rtems_timer_reset: inactive 176 21 - rtems_timer_reset: active 189 22 - rtems_timer_fire_when: inactive 237 28 - rtems_timer_fire_when: active 237 28 - rtems_timer_delete: active 167 25 - rtems_timer_delete: inactive 153 23 - rtems_task_wake_when 408 83 - -24 rtems_task_wake_after: yield -- returns to caller 85 8 - rtems_task_wake_after: yields -- preempts caller 287 56 - -25 rtems_clock_tick 59 25 - -26 _ISR_Disable 3 1 - _ISR_Flash 3 0 - _ISR_Enable 1 0 - _Thread_Disable_dispatch 4 0 - _Thread_Enable_dispatch 59 6 - _Thread_Set_state 59 16 - _Thread_Disptach (NO FP) 242 52 - context switch: no floating point contexts 183 44 - context switch: self 62 2 - context switch: to another task 64 3 - context switch: restore 1st FP task 189 40 - fp context switch: save idle, restore idle 186 39 - fp context switch: save idle, restore initialized 67 4 - fp context switch: save initialized, restore initialized 67 5 - _Thread_Resume 51 24 - _Thread_Unblock 47 12 - _Thread_Ready 54 9 - _Thread_Get 33 3 - _Semaphore_Get 26 2 - _Thread_Get: invalid id 5 0 - -27 interrupt entry overhead: returns to interrupted task 0 0 - interrupt exit overhead: returns to interrupted task 1 1 - interrupt entry overhead: returns to nested interrupt 0 0 - interrupt exit overhead: returns to nested interrupt 0 0 - interrupt entry overhead: returns to preempting task - interrupt exit overhead: returns to preempting task - -28 rtems_port_create 145 55 - rtems_port_external_to_internal 101 9 - rtems_port_internal_to_external 101 9 - rtems_port_delete 144 40 - -29 rtems_rate_monotonic_create 135 57 - rtems_rate_monotonic_period: initiate period -- returns to caller 176 77 - rtems_rate_monotonic_period: obtain status 110 35 - rtems_rate_monotonic_cancel 131 50 - rtems_rate_monotonic_delete: inactive 160 61 - rtems_rate_monotonic_delete: active 178 41 - rtems_rate_monotonic_period: conclude periods -- caller blocks 284 67 diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/times-mbx860 b/c/src/lib/libbsp/powerpc/mbx8xx/times-mbx860 deleted file mode 100644 index 6bcb69d370..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/times-mbx860 +++ /dev/null @@ -1,187 +0,0 @@ -# -# Timing Test Suite Results for the MBX860-002 -# - -Board: MBX860 -CPU: MPC860 -Clock Speed: 40 MHz -Memory Configuration: 4Mb EDO, 60ns DRAM -Wait States: - -Times Reported in: clock ticks -Timer Source: Timebase register (TMBCLK = (cpu clock speed / 16) = 2.5Mhz) - -Column A: Data & instruction caches disabled (2000-05-03) -Column B: Data & instruction caches enabled (UPM/A: new burst r/w values) (2000-05-04) - -# DESCRIPTION A B -== ================================================================= ==== ==== - 1 rtems_semaphore_create 159 67 - rtems_semaphore_delete 173 52 - rtems_semaphore_obtain: available 113 26 - rtems_semaphore_obtain: not available -- NO_WAIT 113 28 - rtems_semaphore_release: no waiting tasks 144 22 - - 2 rtems_semaphore_obtain: not available -- caller blocks 346 121 - - 3 rtems_semaphore_release: task readied -- preempts caller 268 89 - - 4 rtems_task_restart: blocked task -- preempts caller 475 130 - rtems_task_restart: ready task -- preempts caller 465 132 - rtems_semaphore_release: task readied -- returns to caller 179 48 - rtems_task_create 521 154 - rtems_task_start 228 57 - rtems_task_restart: suspended task -- returns to caller 275 74 - rtems_task_delete: suspended task 494 139 - rtems_task_restart: ready task -- returns to caller 283 78 - rtems_task_restart: blocked task -- returns to caller 333 98 - rtems_task_delete: blocked task 507 144 - - 5 rtems_task_suspend: calling task 266 88 - rtems_task_resume: task readied -- preempts caller 220 61 - - 6 rtems_task_restart: calling task 334 75 - rtems_task_suspend: returns to caller 117 24 - rtems_task_resume: task readied -- returns to caller 129 29 - rtems_task_delete: ready task 510 138 - - 7 rtems_task_restart: suspended task -- preempts caller 436 135 - - 8 rtems_task_set_priority: obtain current priority 98 11 - rtems_task_set_priority: returns to caller 183 32 - rtems_task_mode: obtain current mode 51 8 - rtems_task_mode: no reschedule 62 9 - rtems_task_mode: reschedule -- returns to caller 66 25 - rtems_task_mode: reschedule -- preempts caller 246 69 - rtems_clock_set 222 35 - rtems_clock_get 6 1 - - 9 rtems_message_queue_create 667 262 - rtems_message_queue_send: no waiting tasks 215 58 - rtems_message_queue_urgent: no waiting tasks 212 53 - rtems_message_queue_receive: available 204 43 - rtems_message_queue_flush: no messages flushed 93 17 - rtems_message_queue_flush: messages flushed 113 22 - rtems_message_queue_delete 214 76 - -10 rtems_message_queue_receive: not available -- NO_WAIT 131 20 - rtems_message_queue_receive: not available -- caller blocks 357 118 - -11 rtems_message_queue_send: task readied -- preempts caller 322 109 - -12 rtems_message_queue_send: task readied -- returns to caller 234 67 - -13 rtems_message_queue_urgent: task readied -- preempts caller 322 94 - -14 rtems_message_queue_urgent: task readied -- returns to caller 234 62 - -15 rtems_event_receive: obtain current events 8 1 - rtems_event_receive: not available -- NO_WAIT 90 9 - rtems_event_receive: not available -- caller blocks 294 88 - rtems_event_send: no task readied 91 10 - rtems_event_receive: available 93 22 - rtems_event_send: task readied -- returns to caller 161 41 - -16 rtems_event_send: task readied -- preempts caller 260 84 - -17 rtems_task_set_priority: preempts caller 349 108 - -18 rtems_task_delete: calling task 652 203 - -19 rtems_signal_catch 66 9 - rtems_signal_send: returns to caller 107 41 - rtems_signal_send: signal to self 176 62 - exit ASR overhead: returns to calling task 140 56 - exit ASR overhead: returns to preempting task 207 54 - -20 rtems_partition_create 220 78 - rtems_region_create 175 71 - rtems_partition_get_buffer: available 103 21 - rtems_partition_get_buffer: not available 97 10 - rtems_partition_return_buffer 113 24 - rtems_partition_delete 128 26 - rtems_region_get_segment: available 137 27 - rtems_region_get_segment: not available -- NO_WAIT 126 36 - rtems_region_return_segment: no waiting tasks 148 31 - rtems_region_get_segment: not available -- caller blocks 366 119 - rtems_region_return_segment: task readied -- preempts caller 359 114 - rtems_region_return_segment: task readied -- returns to caller 265 72 - rtems_region_delete 129 33 - rtems_io_initialize 12 2 - rtems_io_open 9 1 - rtems_io_close 9 1 - rtems_io_read 9 1 - rtems_io_write 9 1 - rtems_io_control 9 1 - -21 rtems_task_ident 1019 137 - rtems_message_queue_ident 993 139 - rtems_semaphore_ident 1144 162 - rtems_partition_ident 993 132 - rtems_region_ident 1012 143 - rtems_port_ident 993 132 - rtems_timer_ident 994 138 - rtems_rate_monotonic_ident 993 135 - -22 rtems_message_queue_broadcast: task readied -- returns to caller 249 80 - rtems_message_queue_broadcast: no waiting tasks 157 27 - rtems_message_queue_broadcast: task readied -- preempts caller 340 94 - -23 rtems_timer_create 114 15 - rtems_timer_fire_after: inactive 170 36 - rtems_timer_fire_after: active 182 36 - rtems_timer_cancel: active 104 14 - rtems_timer_cancel: inactive 92 12 - rtems_timer_reset: inactive 156 29 - rtems_timer_reset: active 168 31 - rtems_timer_fire_when: inactive 210 43 - rtems_timer_fire_when: active 210 42 - rtems_timer_delete: active 148 24 - rtems_timer_delete: inactive 136 20 - rtems_task_wake_when 350 99 - -24 rtems_task_wake_after: yield -- returns to caller 76 10 - rtems_task_wake_after: yields -- preempts caller 242 63 - -25 rtems_clock_tick 51 19 - -26 _ISR_Disable 3 0 - _ISR_Flash 2 0 - _ISR_Enable 0 0 - _Thread_Disable_dispatch 3 0 - _Thread_Enable_dispatch 52 8 - _Thread_Set_state 51 15 - _Thread_Disptach (NO FP) 201 53 - context switch: no floating point contexts 148 44 - context switch: self 41 4 - context switch: to another task 44 5 - context switch: restore 1st FP task 154 41 - fp context switch: save idle, restore idle 152 42 - fp context switch: save idle, restore initialized 46 5 - fp context switch: save initialized, restore initialized 47 4 - _Thread_Resume 45 19 - _Thread_Unblock 42 10 - _Thread_Ready 47 8 - _Thread_Get 29 3 - _Semaphore_Get 23 2 - _Thread_Get: invalid id 5 0 - -27 interrupt entry overhead: returns to interrupted task 0 0 - interrupt exit overhead: returns to interrupted task 0 0 - interrupt entry overhead: returns to nested interrupt 0 0 - interrupt exit overhead: returns to nested interrupt 0 0 - interrupt entry overhead: returns to preempting task - interrupt exit overhead: returns to preempting task - -28 rtems_port_create 128 48 - rtems_port_external_to_internal 90 9 - rtems_port_internal_to_external 90 13 - rtems_port_delete 128 30 - -29 rtems_rate_monotonic_create 120 48 - rtems_rate_monotonic_period: initiate period -- returns to caller 156 55 - rtems_rate_monotonic_period: obtain status 98 27 - rtems_rate_monotonic_cancel 115 39 - rtems_rate_monotonic_delete: inactive 141 51 - rtems_rate_monotonic_delete: active 158 46 - rtems_rate_monotonic_period: conclude periods -- caller blocks 240 76 -- cgit v1.2.3