From 2d27725838c7e61abf092e8ca8a89f17a35cc6bf Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Mon, 25 Oct 2021 09:53:44 -0500 Subject: bsps/aarch64: Set interrupt level correctly The existing code is functional but inccorrect and blindly modifies the other masking bits. It is important to preserve those other bits since they control masking of important system events. --- bsps/aarch64/include/dev/irq/arm-gic-arch.h | 2 +- cpukit/score/cpu/aarch64/cpu.c | 16 +++++++++++----- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/bsps/aarch64/include/dev/irq/arm-gic-arch.h b/bsps/aarch64/include/dev/irq/arm-gic-arch.h index 0911320851..049a1c8555 100644 --- a/bsps/aarch64/include/dev/irq/arm-gic-arch.h +++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h @@ -49,7 +49,7 @@ extern "C" { static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector) { uint32_t interrupt_level = _CPU_ISR_Get_level(); - AArch64_interrupt_enable(1); + _CPU_ISR_Set_level(1); bsp_interrupt_handler_dispatch(vector); _CPU_ISR_Set_level(interrupt_level); } diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c index b36f55ae17..88e7ad8a8c 100644 --- a/cpukit/score/cpu/aarch64/cpu.c +++ b/cpukit/score/cpu/aarch64/cpu.c @@ -149,11 +149,17 @@ void _CPU_Context_Initialize( void _CPU_ISR_Set_level( uint32_t level ) { /* Set the mask bit if interrupts are disabled */ - level = level ? AARCH64_PSTATE_I : 0; - __asm__ volatile ( - "msr DAIF, %[level]\n" - : : [level] "r" (level) - ); + if ( level ) { + __asm__ volatile ( + "msr DAIFSet, #0x2\n" + : : [level] "r" (level) + ); + } else { + __asm__ volatile ( + "msr DAIFClr, #0x2\n" + : : [level] "r" (level) + ); + } } uint32_t _CPU_ISR_Get_level( void ) -- cgit v1.2.3