From 0cb50ab25b3e2cb9ccf0f4961e0229415e211cb7 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sat, 2 Jul 2016 14:33:11 +0200 Subject: score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib. Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment. --- cpukit/score/cpu/arm/rtems/score/arm.h | 4 ++++ cpukit/score/cpu/arm/rtems/score/cpu.h | 7 +++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h index 334e73a7ff..666ee54068 100644 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -54,6 +54,10 @@ extern "C" { #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER #endif +#if defined(__ARM_ARCH_7A__) + #define ARM_MULTILIB_CACHE_LINE_MAX_64 +#endif + #if !defined(__SOFTFP__) #if defined(__ARM_NEON__) #define ARM_MULTILIB_VFP_D32 diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 91e4ec6211..adaf8091d3 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -145,8 +145,11 @@ #define CPU_STACK_GROWS_UP FALSE -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 +#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) + #define CPU_CACHE_LINE_BYTES 32 +#else + #define CPU_CACHE_LINE_BYTES 64 +#endif #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) -- cgit v1.2.3