From 0b60c5435109d877c350168d48bd102538810c07 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 25 Apr 2018 14:50:36 +0200 Subject: bsp/haleakala: Move assembler files to bsps This patch is a part of the BSP source reorganization. Update #3285. --- bsps/powerpc/haleakala/start/dlentry.S | 237 +++++++++++++++++++++ bsps/powerpc/haleakala/start/mmu_405asm.S | 83 ++++++++ c/src/lib/libbsp/powerpc/haleakala/Makefile.am | 4 +- .../lib/libbsp/powerpc/haleakala/dlentry/dlentry.S | 237 --------------------- .../lib/libbsp/powerpc/haleakala/mmu/mmu_405asm.S | 83 -------- 5 files changed, 322 insertions(+), 322 deletions(-) create mode 100644 bsps/powerpc/haleakala/start/dlentry.S create mode 100644 bsps/powerpc/haleakala/start/mmu_405asm.S delete mode 100644 c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S delete mode 100644 c/src/lib/libbsp/powerpc/haleakala/mmu/mmu_405asm.S diff --git a/bsps/powerpc/haleakala/start/dlentry.S b/bsps/powerpc/haleakala/start/dlentry.S new file mode 100644 index 0000000000..2395d89886 --- /dev/null +++ b/bsps/powerpc/haleakala/start/dlentry.S @@ -0,0 +1,237 @@ +/* dlentry.s + * + * This file contains the entry code for RTEMS programs starting + * after download to RAM + * + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * This file contains the entry veneer for RTEMS programs + * downloaded to Papyrus. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * derived from "helas403/dlentry.S": + * + * Further changes to derive for the PPC405CR/GP/GPr/EX/EXr + * by Michael Hamel ADInstruments Ltd 2008 + */ + +#include + +/* + * The virtex ELF link scripts support three special sections: + * .entry The actual entry point + * .vectors The section containing the interrupt entry veneers. + */ + +/* + * Downloaded code loads the vectors separately to 0x00000100, + * so .entry can be over 256 bytes. + * + * The other sections are linked in the following order: + * .entry + * .text + * .data + * .bss + * see linker command file for section placement + * + * The initial stack is set to stack.end + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here was some DWARF information. IMD removed it, because we + * could not check, whether it was still correct. Sorry. + + */ + + + .section .entry + + PUBLIC_VAR (start) + PUBLIC_VAR (download_entry) + PUBLIC_VAR (__rtems_entry_point) + +SYM(start): +SYM(download_entry): +SYM(__rtems_entry_point): + + .extern SYM (boot_card) + + bl .startup /* First word is branch to reset_entry */ + + +/*--------------------------------------------------------------------------- + * Parameters from linker + *--------------------------------------------------------------------------*/ + +base_addr: +toc_pointer: + .long s.got +bss_length: + .long bss.size +bss_addr: + .long bss.start +sbss_length: + .long sbss.size +sbss_addr: + .long sbss.start +stack_top: + .long stack.end +PUBLIC_VAR (text_addr) +text_addr: + .long text.start +PUBLIC_VAR (text_length) +text_length: + .long text.size + +/*--------------------------------------------------------------------------- + * Reset_entry. + *--------------------------------------------------------------------------*/ +.startup: + /* Get entrypoint address in R1 so we can find linker variables */ + mflr r1 + + /* Initialise procesor registers generally */ + bl init405 + + /* Clear .bss and .sbss */ + bl bssclr + + /*------------------------------------------------------------------- + * C_setup. + *------------------------------------------------------------------*/ + lwz r1,stack_top - base_addr(r1) /* Now set R1 to stack_top */ + addi r1,r1,-56-4 /* start stack at text_addr - 56 */ + li r3,0 + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + + bl __eabi /* Initialise EABI: sets up r2 & r13 */ + + li r3, 0 /* command line */ + + b SYM (boot_card) /* call the first C routine */ + +/*--------------------------------------------------------------------------- + * bssclr. + *--------------------------------------------------------------------------*/ +bssclr: lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + srwi. r3,r3,2 /* div 4 to get # of words */ + li r0,0 + beq dosbss /* no bss */ + mtctr r3 /* set ctr reg */ + subi r2,r2,4 +clear_bss: stwu r0,4(r2) + bdnz clear_bss /* decrement counter and loop */ + +dosbss: lwz r2,sbss_addr-base_addr(r1) /* start of sbss set by loader */ + lwz r3,sbss_length-base_addr(r1) /* sbss length */ + slwi. r3,r3,2 /* div 4 to get # of words */ + subi r2,r2,4 + beqlr /* no sbss */ + mtctr r3 /* set ctr reg */ +clear_sbss: stwu r0,4(r2) + bdnz clear_sbss /* decrement counter and loop */ + + blr /* return */ + + +/*--------------------------------------------------------------------------- + * Generic 405 register setup + *--------------------------------------------------------------------------*/ +init405: + li r0, 0 + mtmsr r0 + mticcr r0 + mtdccr r0 + + li r3,0x7FFC # 405EX-specific + mtsgr r3 # Clear guarded mode on all storage except PCIe region + + mtsler r0 # Storage is all big-endian + mtsu0r r0 # and uncompressed + + iccci r3,0 # Invalidate the instruction cache + li r3,1 # Enable F800 0000 to FFFF FFFF + oris r3,r3,0xC000 # Enable 0000 0000 to 0FFF FFFF + mticcr r3 + isync + + li r3,0 + li r4,256 # 405 has 128 or 256 32-byte lines: do 256 + mtctr r4 # set loop ctr +dcloop: dccci 0,r3 # invalidate line + addi r3,r3,0x20 # bump to next line + bdnz dcloop + mtdcwr r0 # Select write-back caching + lis r3,0xC000 # Enable 0000 0000 to 0FFF FFFF + # mtdccr r3 # Enable data cache + + mtevpr r0 + mtesr r0 + mtxer r0 + + lwarx r3,r0,r0 # get some data/set resv bit + stwcx. r3,r0,r0 # store out and clear resv bit + + lis r3,0xDEAD + ori r3,r3,0xBEEF # Make distintive uninitialised value + mr r4, r3 + mr r5, r3 + mr r6, r3 + mr r7, r3 + mr r8, r3 + mr r9, r3 + mr r10, r3 + mr r11, r3 + mr r12, r3 + mr r13, r3 + mr r14, r3 + mr r15, r3 + mr r16, r3 + mr r17, r3 + mr r18, r3 + mr r19, r3 + mr r20, r3 + mr r21, r3 + mr r22, r3 + mr r23, r3 + mr r24, r3 + mr r25, r3 + mr r26, r3 + mr r27, r3 + mr r28, r3 + mr r29, r3 + mr r30, r3 + mr r31, r3 + + blr + +.L_text_e: + + .comm environ,4,4 diff --git a/bsps/powerpc/haleakala/start/mmu_405asm.S b/bsps/powerpc/haleakala/start/mmu_405asm.S new file mode 100644 index 0000000000..5fef5fb11f --- /dev/null +++ b/bsps/powerpc/haleakala/start/mmu_405asm.S @@ -0,0 +1,83 @@ +/* + +Low-level interface to the PPC405 MMU + +M.Hamel ADInstruments 2008 + +*/ + +#include + +/* Useful MMU SPR values */ + +#define SPR_ZPR 0x3B0 +#define SPR_PID 0x3B1 + + .text + +/* void MMU_ClearTLBs(); */ + PUBLIC_VAR(MMU_ClearTLBs) +SYM (MMU_ClearTLBs): + tlbia + isync + lis r3,0x5555 // *** Gratuitous fiddle of ZPR to 0101010101 to take it out of + mtspr SPR_ZPR,r3 // the picture + blr + +/* void MMU_SetTLBEntry(UInt8 index, UInt32 tagword, UInt32 dataword, UInt8 SPR_PID) */ + PUBLIC_VAR(MMU_SetTLBEntry) +SYM (MMU_SetTLBEntry): + mfspr r7,SPR_PID // Save the current SPR_PID + mtspr SPR_PID,r6 // Write to SPR_PID + tlbwehi r4,r3 // Write hiword + mtspr SPR_PID,r7 // Restore the SPR_PID + tlbwelo r5,r3 // Write loword + isync + blr + +/* void MMU_GetTLBEntry(UInt8 index, UInt32& tagword, UInt32& dataword, UInt8& SPR_PID) */ + PUBLIC_VAR(MMU_GetTLBEntry) +SYM (MMU_GetTLBEntry): + mfspr r7,SPR_PID // Save the current SPR_PID + tlbrehi r8,r3 // Read hiword & SPR_PID + mfspr r9,SPR_PID // Copy the SPR_PID + mtspr SPR_PID,r7 // Restore original SPR_PID so we can proceed + stw r8,0(r4) // Write to r4 pointer + stb r9,0(r6) // Write to r6 pointer + tlbrelo r8,r3 // Read loword + stw r8,0(r5) // Write to r5 pointer + blr + +/* SInt16 MMU_FindTLBEntry(UInt32 address) */ +/* Returns index of covering TLB entry (0..63), or -1 if there isn't one */ + PUBLIC_VAR(MMU_FindTLBEntry) +SYM (MMU_FindTLBEntry): + tlbsx. r3,0,r3 + beqlr + li r3,0xFFFFFFFF + blr + +/* bool mmu_enable_code(bool enable); */ + PUBLIC_VAR(mmu_enable_code) +SYM (mmu_enable_code): + li r5,0x20 // IR bit + b msrbits + +/* bool mmu_enable_data(bool enable); */ + PUBLIC_VAR(mmu_enable_data) +SYM (mmu_enable_data): + li r5,0x10 // DR bit +msrbits: cmpwi r3,0 // Common code: parameter 0? + mfmsr r4 // r4 = MSR state + beq clrBit + or r6,r4,r5 // If 1, r6 = MSR with bit set + b setmsr +clrBit: andc r6,r4,r5 // If 0 r6 = MSR with bit clear +setmsr: mtmsr r6 // Write new MSR + and. r3,r4,r5 // Result = old MSR bit + beqlr // If zero return zero + li r3,0xFF // If nonzero return byte -1 + blr + + + diff --git a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am index 6b32958bdd..43c31ec2df 100644 --- a/c/src/lib/libbsp/powerpc/haleakala/Makefile.am +++ b/c/src/lib/libbsp/powerpc/haleakala/Makefile.am @@ -24,10 +24,10 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/getentropy/getentropy librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-default.c librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/sbrk.c librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/haleakala/start/mmu_405.c -librtemsbsp_a_SOURCES += mmu/mmu_405asm.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/haleakala/start/mmu_405asm.S # dlentry -librtemsbsp_a_SOURCES += dlentry/dlentry.S +librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/haleakala/start/dlentry.S # console librtemsbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/console/uart.c diff --git a/c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S deleted file mode 100644 index 2395d89886..0000000000 --- a/c/src/lib/libbsp/powerpc/haleakala/dlentry/dlentry.S +++ /dev/null @@ -1,237 +0,0 @@ -/* dlentry.s - * - * This file contains the entry code for RTEMS programs starting - * after download to RAM - * - * Author: Thomas Doerfler - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: - * - * This file contains the entry veneer for RTEMS programs - * downloaded to Papyrus. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * derived from "helas403/dlentry.S": - * - * Further changes to derive for the PPC405CR/GP/GPr/EX/EXr - * by Michael Hamel ADInstruments Ltd 2008 - */ - -#include - -/* - * The virtex ELF link scripts support three special sections: - * .entry The actual entry point - * .vectors The section containing the interrupt entry veneers. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .text - * .data - * .bss - * see linker command file for section placement - * - * The initial stack is set to stack.end - * - * All the entry veneer has to do is to clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here was some DWARF information. IMD removed it, because we - * could not check, whether it was still correct. Sorry. - - */ - - - .section .entry - - PUBLIC_VAR (start) - PUBLIC_VAR (download_entry) - PUBLIC_VAR (__rtems_entry_point) - -SYM(start): -SYM(download_entry): -SYM(__rtems_entry_point): - - .extern SYM (boot_card) - - bl .startup /* First word is branch to reset_entry */ - - -/*--------------------------------------------------------------------------- - * Parameters from linker - *--------------------------------------------------------------------------*/ - -base_addr: -toc_pointer: - .long s.got -bss_length: - .long bss.size -bss_addr: - .long bss.start -sbss_length: - .long sbss.size -sbss_addr: - .long sbss.start -stack_top: - .long stack.end -PUBLIC_VAR (text_addr) -text_addr: - .long text.start -PUBLIC_VAR (text_length) -text_length: - .long text.size - -/*--------------------------------------------------------------------------- - * Reset_entry. - *--------------------------------------------------------------------------*/ -.startup: - /* Get entrypoint address in R1 so we can find linker variables */ - mflr r1 - - /* Initialise procesor registers generally */ - bl init405 - - /* Clear .bss and .sbss */ - bl bssclr - - /*------------------------------------------------------------------- - * C_setup. - *------------------------------------------------------------------*/ - lwz r1,stack_top - base_addr(r1) /* Now set R1 to stack_top */ - addi r1,r1,-56-4 /* start stack at text_addr - 56 */ - li r3,0 - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - - bl __eabi /* Initialise EABI: sets up r2 & r13 */ - - li r3, 0 /* command line */ - - b SYM (boot_card) /* call the first C routine */ - -/*--------------------------------------------------------------------------- - * bssclr. - *--------------------------------------------------------------------------*/ -bssclr: lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - srwi. r3,r3,2 /* div 4 to get # of words */ - li r0,0 - beq dosbss /* no bss */ - mtctr r3 /* set ctr reg */ - subi r2,r2,4 -clear_bss: stwu r0,4(r2) - bdnz clear_bss /* decrement counter and loop */ - -dosbss: lwz r2,sbss_addr-base_addr(r1) /* start of sbss set by loader */ - lwz r3,sbss_length-base_addr(r1) /* sbss length */ - slwi. r3,r3,2 /* div 4 to get # of words */ - subi r2,r2,4 - beqlr /* no sbss */ - mtctr r3 /* set ctr reg */ -clear_sbss: stwu r0,4(r2) - bdnz clear_sbss /* decrement counter and loop */ - - blr /* return */ - - -/*--------------------------------------------------------------------------- - * Generic 405 register setup - *--------------------------------------------------------------------------*/ -init405: - li r0, 0 - mtmsr r0 - mticcr r0 - mtdccr r0 - - li r3,0x7FFC # 405EX-specific - mtsgr r3 # Clear guarded mode on all storage except PCIe region - - mtsler r0 # Storage is all big-endian - mtsu0r r0 # and uncompressed - - iccci r3,0 # Invalidate the instruction cache - li r3,1 # Enable F800 0000 to FFFF FFFF - oris r3,r3,0xC000 # Enable 0000 0000 to 0FFF FFFF - mticcr r3 - isync - - li r3,0 - li r4,256 # 405 has 128 or 256 32-byte lines: do 256 - mtctr r4 # set loop ctr -dcloop: dccci 0,r3 # invalidate line - addi r3,r3,0x20 # bump to next line - bdnz dcloop - mtdcwr r0 # Select write-back caching - lis r3,0xC000 # Enable 0000 0000 to 0FFF FFFF - # mtdccr r3 # Enable data cache - - mtevpr r0 - mtesr r0 - mtxer r0 - - lwarx r3,r0,r0 # get some data/set resv bit - stwcx. r3,r0,r0 # store out and clear resv bit - - lis r3,0xDEAD - ori r3,r3,0xBEEF # Make distintive uninitialised value - mr r4, r3 - mr r5, r3 - mr r6, r3 - mr r7, r3 - mr r8, r3 - mr r9, r3 - mr r10, r3 - mr r11, r3 - mr r12, r3 - mr r13, r3 - mr r14, r3 - mr r15, r3 - mr r16, r3 - mr r17, r3 - mr r18, r3 - mr r19, r3 - mr r20, r3 - mr r21, r3 - mr r22, r3 - mr r23, r3 - mr r24, r3 - mr r25, r3 - mr r26, r3 - mr r27, r3 - mr r28, r3 - mr r29, r3 - mr r30, r3 - mr r31, r3 - - blr - -.L_text_e: - - .comm environ,4,4 diff --git a/c/src/lib/libbsp/powerpc/haleakala/mmu/mmu_405asm.S b/c/src/lib/libbsp/powerpc/haleakala/mmu/mmu_405asm.S deleted file mode 100644 index 5fef5fb11f..0000000000 --- a/c/src/lib/libbsp/powerpc/haleakala/mmu/mmu_405asm.S +++ /dev/null @@ -1,83 +0,0 @@ -/* - -Low-level interface to the PPC405 MMU - -M.Hamel ADInstruments 2008 - -*/ - -#include - -/* Useful MMU SPR values */ - -#define SPR_ZPR 0x3B0 -#define SPR_PID 0x3B1 - - .text - -/* void MMU_ClearTLBs(); */ - PUBLIC_VAR(MMU_ClearTLBs) -SYM (MMU_ClearTLBs): - tlbia - isync - lis r3,0x5555 // *** Gratuitous fiddle of ZPR to 0101010101 to take it out of - mtspr SPR_ZPR,r3 // the picture - blr - -/* void MMU_SetTLBEntry(UInt8 index, UInt32 tagword, UInt32 dataword, UInt8 SPR_PID) */ - PUBLIC_VAR(MMU_SetTLBEntry) -SYM (MMU_SetTLBEntry): - mfspr r7,SPR_PID // Save the current SPR_PID - mtspr SPR_PID,r6 // Write to SPR_PID - tlbwehi r4,r3 // Write hiword - mtspr SPR_PID,r7 // Restore the SPR_PID - tlbwelo r5,r3 // Write loword - isync - blr - -/* void MMU_GetTLBEntry(UInt8 index, UInt32& tagword, UInt32& dataword, UInt8& SPR_PID) */ - PUBLIC_VAR(MMU_GetTLBEntry) -SYM (MMU_GetTLBEntry): - mfspr r7,SPR_PID // Save the current SPR_PID - tlbrehi r8,r3 // Read hiword & SPR_PID - mfspr r9,SPR_PID // Copy the SPR_PID - mtspr SPR_PID,r7 // Restore original SPR_PID so we can proceed - stw r8,0(r4) // Write to r4 pointer - stb r9,0(r6) // Write to r6 pointer - tlbrelo r8,r3 // Read loword - stw r8,0(r5) // Write to r5 pointer - blr - -/* SInt16 MMU_FindTLBEntry(UInt32 address) */ -/* Returns index of covering TLB entry (0..63), or -1 if there isn't one */ - PUBLIC_VAR(MMU_FindTLBEntry) -SYM (MMU_FindTLBEntry): - tlbsx. r3,0,r3 - beqlr - li r3,0xFFFFFFFF - blr - -/* bool mmu_enable_code(bool enable); */ - PUBLIC_VAR(mmu_enable_code) -SYM (mmu_enable_code): - li r5,0x20 // IR bit - b msrbits - -/* bool mmu_enable_data(bool enable); */ - PUBLIC_VAR(mmu_enable_data) -SYM (mmu_enable_data): - li r5,0x10 // DR bit -msrbits: cmpwi r3,0 // Common code: parameter 0? - mfmsr r4 // r4 = MSR state - beq clrBit - or r6,r4,r5 // If 1, r6 = MSR with bit set - b setmsr -clrBit: andc r6,r4,r5 // If 0 r6 = MSR with bit clear -setmsr: mtmsr r6 // Write new MSR - and. r3,r4,r5 // Result = old MSR bit - beqlr // If zero return zero - li r3,0xFF // If nonzero return byte -1 - blr - - - -- cgit v1.2.3