From 0abe47f142691910cae4e8a8b0544e63c14a5516 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20D=C3=B6rfler?= Date: Thu, 10 Jan 2019 07:29:54 +0100 Subject: bsps/arm: Fix typo in disable cache for ARMv7-AR Update #3667. --- bsps/arm/shared/cache/cache-v7ar-disable-data.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/arm/shared/cache/cache-v7ar-disable-data.S b/bsps/arm/shared/cache/cache-v7ar-disable-data.S index b275c1d484..4b20fb268f 100644 --- a/bsps/arm/shared/cache/cache-v7ar-disable-data.S +++ b/bsps/arm/shared/cache/cache-v7ar-disable-data.S @@ -73,7 +73,7 @@ FUNCTION_ENTRY(rtems_cache_disable_data) /* Read CCSIDR */ lsl r4, r3, #1 - mcr p15, 2, r5, c0, c0, 0 + mcr p15, 2, r4, c0, c0, 0 isb mrc p15, 1, r5, c0, c0, 0 -- cgit v1.2.3