summaryrefslogtreecommitdiffstats
path: root/spec (follow)
Commit message (Collapse)AuthorAgeFilesLines
* bsps/imx: Enable clock of ETH2Christian Mauderer2022-06-091-0/+1
|
* testsuite/libtests: Add exit03 to test exit() with C++Chris Johns2022-06-092-0/+22
| | | | Updates #4661
* bsps/atsam: Fix type of optionsChristian Mauderer2022-06-072-4/+4
| | | | | | ATSAM_CONSOLE_DEVICE_INDEX and ATSAM_CONSOLE_DEVICE_TYPE have to be integers like suggested by their description. Otherwise it's not possible to select (for example) USART2 as console device.
* bsps/stm32h7: set SDRAM 1 size to 0 by default on nucleo-h743zi BSPKarel Gardas2022-06-021-0/+1
| | | | | | | Nucleo does not have any SDRAM, so 0 size is the only possible right choice here. Sponsored-By: Precidata
* bsps/stm32h7: set default linkage to flash for nucleo-h743zi BSPKarel Gardas2022-06-021-0/+1
| | | | | | | Nucleo does not have any SDRAM so default linkage to SDRAM does not make any sense here. Sponsored-By: Precidata
* bsps/stm32h7: set default printk instance on nucleo-h743zi BSP to USART3Karel Gardas2022-06-021-1/+4
| | | | | | | | This is the default configuration of the board out of the box. Any other possible/supported configuration requires soldering, so definitely not out of the box experience. Sponsored-By: Precidata
* bsps/stm32h7: add stm32h747i-disco-m4 BSP variantKarel Gardas2022-06-0220-0/+43
| | | | | | | | | This patch adds stm32h747i-disco-m4 BSP variant and puts it in sync with the stm32h747i-disco BSP variant hardware support. That means, only USART 1, 2 and UART 8 are enabled. Also SDRAM 2 is set to 32MB, SDRAM 1 size is set to 0. Sponsored-By: Precidata
* bsps/stm32h7: set default SDRAM x sizes on stm32h747i-disco BSPKarel Gardas2022-06-012-0/+2
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: disable all unsupported U(S)ARTs on stm32h747i-disco BSPKarel Gardas2022-06-017-0/+7
| | | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. That means only USART1 and 2 and UART8 are enabled. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h747i-disco BSPKarel Gardas2022-06-018-0/+33
| | | | Sponsored-By: Precidata
* bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSPKarel Gardas2022-06-012-0/+2
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSPKarel Gardas2022-06-019-0/+9
| | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSPKarel Gardas2022-06-0111-3/+66
| | | | | | | | | | | | | | | | This is minimalist configuration for the stm32h757i-eval-m4 BSP provided here. The only general enhancement worth mention is a flash origin address configuration which is needed for simplification as M4 core boots from second flash bank which starts at 0x8100000 by default. The boot address of the core may be changed by using STM32CubeProgrammer. If done so then also BSP configuration needs to be changed accordingly. As the BSP variant is running on M4 core, there is also more configuration changes required here. E.g. boot core and ABI (compilation flags) in comparison with stm32h757i-eval BSP. On the other hand, C code is shared completely with this BSP variant. Sponsored-By: Precidata
* bsps/stm32h7: move cache implementation from obj to BSPs own yml fileKarel Gardas2022-06-015-1/+4
| | | | | | | This is done in preparation for future Cortex-M4 based BSP variants which do not provide cache at all. Sponsored-By: Precidata
* bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval BSPKarel Gardas2022-05-272-1/+5
| | | | | | | | | This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
* bsps/stm32h7: provide linkcmds for SRAM, FLASH_SDRAM and SRAM_SDRAM linkingKarel Gardas2022-05-275-2/+156
| | | | Sponsored-By: Precidata
* bsps/stm32h7: add and enable test set exclusion for stm32h757i-eval BSPKarel Gardas2022-05-272-0/+21
| | | | Sponsored-By: Precidata
* bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval BSPKarel Gardas2022-05-279-2/+16
| | | | | | | This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata
* bsps/stm32h7: add configuration and enable build of stm32h757i-eval BSPKarel Gardas2022-05-277-0/+54
| | | | | | | | | | This is minimalist configuration for the stm32h757i-eval BSP provided here. The only general enhancement worth mention is boot core configuration which is needed here as this is the first dual-core board supported by stm32h7 BSP family and we need to choose boot core in order to get C files compiling well. Sponsored-By: Precidata
* testsuites/sptests: Add sppps01 testGabriel Moyano2022-05-232-0/+21
| | | | Update #2349.
* bsp/stm32h7: copy system files to nucleo-h743zi board directoryKarel Gardas2022-05-161-5/+5
| | | | | | Also adjust BSP spec file to make it buildable with board files. Sponsored-By: Precidata
* bsp/stm32h7: copy system files to stm32h743i-eval board directoryKarel Gardas2022-05-161-5/+5
| | | | | | Also adjust BSP spec file to make it buildable with board files. Sponsored-By: Precidata
* bsp/stm32h7: copy system files to stm32h7b3i-dk board directoryKarel Gardas2022-05-161-5/+5
| | | | | | Also adjust BSP spec file to make it buildable with board files. Sponsored-By: Precidata
* bsp/stm32h7: move compilation of system files to BSPs spec. filesKarel Gardas2022-05-164-8/+18
| | | | | | The patch is done in preparation for stm32h7 BSP tree refactoring. Sponsored-By: Precidata
* build: Check for psxtests prerequisitesSebastian Huber2022-05-055-4/+10
| | | | Close #4645.
* build: Remove obsolete test excludesSebastian Huber2022-04-0613-52/+0
|
* bsps: Add <dev/irq/arm-gicv3.h>Sebastian Huber2022-04-062-0/+2
| | | | | | | | Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
* unit: Test red-black treesSebastian Huber2022-04-061-0/+1
|
* unit: Add test for misaligned builtin memcpy()Sebastian Huber2022-04-061-0/+1
|
* unit: Add a unit test suiteSebastian Huber2022-04-065-0/+60
|
* bsp/stm32h7: Disable some tests for a variantSebastian Huber2022-04-061-0/+2
| | | | Making this BSP a small memory target is a bit coarse and could be improved.
* bsps/stm32h7: link to flash on STM32H7B3I-DKKarel Gardas2022-04-061-1/+4
| | | | | The patch is needed due to smaller SRAM and completely disabled SDRAM on the BSP variant.
* bsp/stm32h7: use appropriate STM32H7B3xxQ define for STM32H7B3I-DK BSP variantKarel Gardas2022-04-051-1/+4
|
* bsp/stm32h7: configure S(D)RAM values for STM32H7B3I-DK BSP variantKarel Gardas2022-04-056-6/+24
| | | | Caveat: SDRAM 1 is completely disabled for now.
* bsp/stm32h7: HSE clock value configuration for STM32H7B3I-DK BSP variantKarel Gardas2022-04-051-0/+3
|
* bsp/stm32h7: add flash latency configurationKarel Gardas2022-04-052-0/+21
|
* bsp/stm32h7: add configuration for USART1 GPIO pins, registers and alternate ↵Karel Gardas2022-04-054-0/+63
| | | | function
* bsp/stm32h7: disable UART 5, 7, 8, 9 and USART 3, 6, 10 for STM32H7B3I-DK BSPKarel Gardas2022-04-057-7/+28
|
* bsp/stm32h7: add power supply configurationKarel Gardas2022-04-052-0/+21
|
* bsp/stm32h7: add spec file for the STM32H7B3I-DK BSP variantKarel Gardas2022-04-051-0/+17
|
* rtems: Clarify scheduler of created taskSebastian Huber2022-03-291-0/+1
|
* validation: Use individual names for ident testsSebastian Huber2022-03-291-0/+1
| | | | | | Make the task configuration reusable. Update #3716.
* smp: Add fatal errorSebastian Huber2022-03-242-0/+23
| | | | | | | Add SMP-specifc SMP_FATAL_MULTITASKING_START_ON_NOT_ONLINE_PROCESSOR fatal error. This fatal error helps to diagnose a broken SMP startup sequence. Without this error a context switch using the NULL pointer for the thread control block happens which may be difficult to debug.
* validation: Test support functionsSebastian Huber2022-03-241-0/+2
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* validation: Test thread implementationSebastian Huber2022-03-244-0/+46
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* validation: Test SMP-specific aspectsSebastian Huber2022-03-243-0/+24
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* validation: Test scheduler operationsSebastian Huber2022-03-242-0/+4
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* validation: Test C libary functionsSebastian Huber2022-03-241-0/+2
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* validation: Test <sys/lock.h> mutex operationsSebastian Huber2022-03-241-0/+1
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
* validation: Test futex supportSebastian Huber2022-03-241-0/+2
| | | | | | | | | | | | The test source code is generated from specification items by the "./spec2modules.py" script contained in the git://git.rtems.org/rtems-central.git Git repository. Please read the "How-To" section in the "Software Requirements Engineering" chapter of the RTEMS Software Engineering manual to get more information about the process. Update #3716.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 01:18:42 +0000