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2022-08-08libdl: Refactor shared code in ARM and AArch64Ryan Long2-0/+2
rtl-mdreloc-arm.c was used as the basis for rtl-mdreloc-aarch64.c. This lead to some code being shared by the two files. The code was consolidated into rtl-unwind-arm.c. Closes #4686
2022-08-04build: Install <rtems/score/gcov.h>Sebastian Huber1-0/+1
Update #4670.
2022-08-03libmisc/shell: Add an 'rtems' command to report a running buildChris Johns1-0/+1
- Report version, cpu, bsp, tools and options.
2022-07-29cpukit/libdl: Add support for AArch64Ryan Long3-0/+18
rtl-mdreloc-aarch64.c and elf_machdep.h came from NetBSD. Updates #4682
2022-07-28aarch64/versal: Support DDRMC0 region 0 and 1Chris Johns1-5/+43
- Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
2022-07-26build: Move RISCV_MAXIMUM_EXTERNAL_INTERRUPTSSebastian Huber4-19/+3
2022-07-26score: Remove PRIORITY_PSEUDO_ISR thread prioritySebastian Huber1-0/+1
The uniprocessor schedulers had some special case logic for the PRIORITY_PSEUDO_ISR priority. Tasks with a priority of PRIORITY_PSEUDO_ISR were allowed to preempt a not preemptible task. If other higher priority task are made ready while a PRIORITY_PSEUDO_ISR task preempts a not preemptible task, then the other tasks run before the not preemptible task. This made the RTEMS_NO_PREEMPT mode ineffective. Remove the PRIORITY_PSEUDO_ISR special case logic. This simplifies the uniprocessor schedulers. Move the uniprocessor-specific scheduler support to the new header file <rtems/score/scheduleruniimpl.h>. Close #2365.
2022-07-25sptests/spstdc17: New testSebastian Huber2-0/+24
2022-07-25imfs: Add <rtems/imfsimpl.h>Sebastian Huber1-0/+1
2022-07-25bsps/microblaze: Fix build option definition orderAlex White3-4/+2
The build option definitions were rearranged such that the option definitions used in the linker script were not available. This caused linker errors when building.
2022-07-21sptls04: Test an external TLS objectSebastian Huber1-0/+1
2022-07-20bsps/riscv: Sort .noinit* sectionsSebastian Huber1-1/+1
Sort the .noinit* input sections by name first, then by alignment if two sections have the same name. This allows the placement of begin/end symbols to initialize some areas with a special value. Update #4678.
2022-07-20build: Add missing cxxflagsSebastian Huber82-0/+82
Update #4670.
2022-07-18spunlimited01: New testSebastian Huber2-0/+22
Update #4677.
2022-07-15score: Extend memory dirty/zero actionsSebastian Huber1-0/+1
Dirty or zero also the part of the .noinit section used by RTEMS. Close #4678.
2022-07-12irq/arm-gicv3.h: Customize CPU Interface initSebastian Huber18-6/+171
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
2022-07-07validation: Test thread idle bodiesSebastian Huber1-0/+1
Update #3716.
2022-07-07validation: Always test spurious interruptsSebastian Huber2-3/+3
Update #3716.
2022-07-06bsps/aarch64: Use MMU pages appropriatelyKinsey Moore4-12/+12
There were two bugs with MMU page use that were partially hiding each other. The linker script page table section was 4x the size it needed to be and the page table allocation routine was allocating pages PTRSIZE times larger than it needed to. On ILP32, this resulted in incorrect but functional allocation. On LP64, this resulted in allocation failures earlier than expected.
2022-07-04build: Add RTEMS_GCOV_COVERAGE optionSebastian Huber9-2/+112
Update #4670.
2022-07-04gcov: Add wrapper to dump the gcov infoSebastian Huber1-0/+2
Update #4670.
2022-07-04gcov: Add functions to dump the gcov informationSebastian Huber2-0/+4
Update #4670.
2022-07-04gcov: Add fork(), etc. gcov wrappersSebastian Huber1-0/+1
The compiler wraps fork(), etc. system calls if coverage generation is enabled. These functions must be provided by the system. For RTEMS, they just return an error status. Update #4670.
2022-07-04build: Allow separate optimization flagsSebastian Huber12-19/+92
Allow separate optimization flags for the BSP, cpukit, and tests. For example, the BSP and cpukit may be built without optimization if coverage instrumentation is enabled, however, the tests may still use optimization. Update #4670.
2022-07-04build: Fix optimization flags definition orderSebastian Huber64-128/+128
OPTIMIZATION_FLAGS must be defined before /build/bsp/bspopts is processed. Update #4670.
2022-07-04build: Add cppflags, cflags, cxxflags to groupsSebastian Huber70-1/+211
Propagate the group defined cppflags, cflags, and cxxflags from parent groups to child items through the build item context. Update #4670.
2022-07-04build: Move BSP_INCLUDES splitSebastian Huber1-0/+1
The goal is to let the build items define as much as possible.
2022-06-24bsp/stm32h7: Exclude some testsSebastian Huber1-0/+2
2022-06-24bsp/rtl22xx: Exclude exit03Sebastian Huber1-0/+1
2022-06-24tstsmallmem: Exclude exit03 and tftpfsSebastian Huber1-0/+2
2022-06-21TFTPFS: Add testsFrank Kühndel2-0/+27
Update #4666.
2022-06-21TFTPFS: Implement block and window size optionsFrank Kühndel1-1/+2
The original file cpukit/libfs/src/ftpfs/tftpDriver.c is split into two: tftpfs.c - This file contains the code from tftpDriver.c related to file system operations such as mount(), open(), read(), and so on. tftpDriver.c - In the original file remains only the code related to networking. This code implements the Trivial File Transfer Protocol (TFTP). Moreover, the code is extended to support * RFC 2347 TFTP Option Extension * RFC 2348 TFTP Blocksize Option * RFC 7440 TFTP Windowsize Option Update #4666.
2022-06-16bsps/versal: Support a 64bit RAM baseChris Johns1-1/+1
Set the constraint to be 64bits to allow the complete address range.
2022-06-14bsps/atsam: Fix type of options (part 2)Christian Mauderer2-2/+4
The patch "bsps/atsam: Fix type of options" missed to adapt some parts of the yml. With that a custom value works well. But if no value is set, configure doesn't fall back to the default value but instead just causes an error. This patch fixes that.
2022-06-10bsps/stm32h7: remove external memory initialization from nucleo-h743zi BSPKarel Gardas1-1/+0
Nucleo board does not provide any external memory so code does not have any function here anyway. Sponsored-By: Precidata
2022-06-10bsps/stm32h7: move BSP start hooks into boards subdirectoriesKarel Gardas7-0/+7
The idea here is to prepare for better per-board specialization of the hooks function code. Sponsored-By: Precidata
2022-06-10bsps/arm: fix installation of core_cm4.hKarel Gardas1-0/+1
2022-06-09bsps/imx: Enable clock of ETH2Christian Mauderer1-0/+1
2022-06-09testsuite/libtests: Add exit03 to test exit() with C++Chris Johns2-0/+22
Updates #4661
2022-06-07bsps/atsam: Fix type of optionsChristian Mauderer2-4/+4
ATSAM_CONSOLE_DEVICE_INDEX and ATSAM_CONSOLE_DEVICE_TYPE have to be integers like suggested by their description. Otherwise it's not possible to select (for example) USART2 as console device.
2022-06-02bsps/stm32h7: set SDRAM 1 size to 0 by default on nucleo-h743zi BSPKarel Gardas1-0/+1
Nucleo does not have any SDRAM, so 0 size is the only possible right choice here. Sponsored-By: Precidata
2022-06-02bsps/stm32h7: set default linkage to flash for nucleo-h743zi BSPKarel Gardas1-0/+1
Nucleo does not have any SDRAM so default linkage to SDRAM does not make any sense here. Sponsored-By: Precidata
2022-06-02bsps/stm32h7: set default printk instance on nucleo-h743zi BSP to USART3Karel Gardas1-1/+4
This is the default configuration of the board out of the box. Any other possible/supported configuration requires soldering, so definitely not out of the box experience. Sponsored-By: Precidata
2022-06-02bsps/stm32h7: add stm32h747i-disco-m4 BSP variantKarel Gardas20-0/+43
This patch adds stm32h747i-disco-m4 BSP variant and puts it in sync with the stm32h747i-disco BSP variant hardware support. That means, only USART 1, 2 and UART 8 are enabled. Also SDRAM 2 is set to 32MB, SDRAM 1 size is set to 0. Sponsored-By: Precidata
2022-06-01bsps/stm32h7: set default SDRAM x sizes on stm32h747i-disco BSPKarel Gardas2-0/+2
This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
2022-06-01bsps/stm32h7: disable all unsupported U(S)ARTs on stm32h747i-disco BSPKarel Gardas7-0/+7
This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. That means only USART1 and 2 and UART8 are enabled. Sponsored-By: Precidata
2022-06-01bsps/stm32h7: add configuration and enable build of stm32h747i-disco BSPKarel Gardas8-0/+33
Sponsored-By: Precidata
2022-06-01bsps/stm32h7: set default SDRAM x sizes on stm32h757i-eval-m4 BSPKarel Gardas2-0/+2
This means: SDRAM 1: 0 SDRAM 2: 32 MB Sponsored-By: Precidata
2022-06-01bsps/stm32h7: disable all U(S)ARTs except USART1 on stm32h757i-eval-m4 BSPKarel Gardas9-0/+9
This patch disables all U(S)ARTs which are not supported by the board itself and its provided connectors. Sponsored-By: Precidata
2022-06-01bsps/stm32h7: add configuration and enable build of stm32h757i-eval-m4 BSPKarel Gardas11-3/+66
This is minimalist configuration for the stm32h757i-eval-m4 BSP provided here. The only general enhancement worth mention is a flash origin address configuration which is needed for simplification as M4 core boots from second flash bank which starts at 0x8100000 by default. The boot address of the core may be changed by using STM32CubeProgrammer. If done so then also BSP configuration needs to be changed accordingly. As the BSP variant is running on M4 core, there is also more configuration changes required here. E.g. boot core and ABI (compilation flags) in comparison with stm32h757i-eval BSP. On the other hand, C code is shared completely with this BSP variant. Sponsored-By: Precidata
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