| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
| |
This adds a confdef option allowing an application to request mapping
machine exceptions to POSIX signals. This is required for some languages
such as Ada.
|
|
|
|
|
| |
This adds the function implementations necessary to add exception
extensions support to AArch64.
|
|
|
|
|
|
|
|
| |
This adds the set of functions necessary to allow more generic handling
of machine exceptions. This initial patch offers the ability to
manipulate a CPU_Exception_frame and resume execution using that
exception information with or without thread dispatch. These functions
are gated behind the RTEMS_EXCEPTION_EXTENSIONS configuration option.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The rate monotonic period statistics were affected by
rtems_cpu_usage_reset(). The logic to detect and work around a CPU
usage reset was broken.
The Thread_Contol::cpu_time_used is changed to contain the processor
time used throughout the entire lifetime of the thread. The new member
Thread_Contol::cpu_time_used_at_last_reset is added to contain the
processor time used at the time of the last reset through
rtems_cpu_usage_reset(). This decouples the resets of the CPU usage and
the rate monotonic period statistics.
Update #4528.
|
|
|
|
| |
Closes #4533
|
|
|
|
|
| |
This reworks the existing MicroBlaze architecture port and BSP to
achieve basic functionality using the latest RTEMS APIs.
|
|
|
|
|
|
|
|
| |
Add a stack allocator hook specifically for allocation of IDLE thread stacks.
This allows the user to decide if IDLE thread stacks are statically allocated
or handled by the same custom allocator mechanism as other thread stacks.
Closes #4524.
|
|
|
|
| |
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
|
|
|
|
|
|
|
|
|
|
| |
If SMP support is enabled and the system has exactly one processor, then
it may use an uniprocessor scheduler. The ask for help, reconsider help
request, and withdraw node operations can be NULL in this case, since
they are only used if a thread has at least one helping scheduler node.
At least two schedulers are required to get a helping node and each
scheduler involved must own at least one processor. This is not
possible on a system with exactly one processor.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The uniprocessor schedulers do not support systems with more than more
processors. So they rivially support thread pinning and thus the
SMP_FATAL_SCHEDULER_PIN_OR_UNPIN_NOT_SUPPORTED cannot happen.
Add a second default implementation for SMP schedulers which do not
support thread pinning.
Change license to BSD-2-Clause according to file history and re-licensing
agreement.
Update #3053.
|
|
|
|
|
|
|
|
|
|
| |
Split up rbtreenext.c since only _RBTree_Minimum() is used by the operating
system core services (thread queues and the EDF scheduler).
Change license to BSD-2-Clause according to file history and re-licensing
agreement.
Update #3053.
|
|
|
|
|
|
| |
Move the TOD validation to the callers of _TOD_Set(). This avoids dead code in
case only rtems_clock_set() is used in an application because rtems_clock_set()
always calls _TOD_Set() with a valid time of day.
|
|
|
|
| |
Use _Watchdog_Ticks_per_second instead.
|
|
|
|
|
|
|
|
|
|
|
|
| |
The _Thread_Dispatch() function was customized over time and now the
work is done by _Thread_Do_dispatch() and specialized wrappers. The
plain _Thread_Dispatch() is now only used in some CPU ports. Move it to
a separate file to avoid dead code in the general.
Change license to BSD-2-Clause according to file history and
re-licensing agreement.
Update #3053.
|
|
|
|
|
|
|
|
| |
Closes #3373
confstr() style update
Signed-off-by: Eshan Dhawan <eshandhawan51@gmail.com>
|
|
|
|
|
|
|
| |
Prefix the BSP family name with "bsps/" to make it distinct to the BSP
variant names.
Update #4468.
|
|
|
|
|
| |
Split up the SMP multicast action module since the use of the SMP multicast
action variants depend on the architecture and BSP.
|
|
|
|
| |
Add percpujobs.c to contain the per-CPU jobs implementation.
|
|
|
|
|
|
|
| |
- Optionally add support for 'default-by-family' to allow
option to be set by a family and so all related BSPs
Close #4468
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move _ISR_Handler() to a separate file since it is now only used if a handler
is installed by _CPU_ISR_install_raw_handler().
Statically initialize the traps for external interrupts to use the new
_SPARC_Interrupt_trap() which directly dispatches the interrupt handlers
installed by rtems_interrupt_handler_install() via the BSP-provided
_SPARC_Interrupt_dispatch().
Since the trap table is now fully statically initialized, there is no longer a
dependency on the Cache Manager in the default configuration.
Update #4458.
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap()
for all unexpected traps. This enables a proper RTEMS fatal error handling
right from the start. Do not rely on the stack and register settings which
caused an unexpected trap. Use the ISR stack of the processor to do the fatal
error handling. Save the full context which caused the trap. Fatal error
handler may use it for error logging.
Unify the _CPU_Exception_frame_print() implementations and move it to cpukit.
Update #4459.
|
|
|
|
|
|
|
|
| |
Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate
files. The goal is to make their use optional.
Update #4458.
Update #4459.
|
|
|
|
|
|
|
|
|
|
| |
The _ISR_Handler_initialization() does not touch the _ISR_Vector_table[]. Move
the definition of _ISR_Vector_table[] to a separate file.
Change license to BSD-2-Clause according to file history and re-licensing
agreement.
Update #3053.
|
|
|
|
|
|
|
|
|
| |
Make the initialization of the per-CPU data optional.
Change license to BSD-2-Clause according to file history and
re-licensing agreement.
Update #3053.
|
|
|
|
|
|
|
| |
Also updated licenses.
Closes #4400
Updates #3899
|
|
|
|
|
|
|
|
|
|
| |
Created futimens.c and utimensat.c to add support for the POSIX
methods futimens() and utimensat().
utime() and utimes() are considered obsolote by POSIX, but RTEMS
will continue to support them.
Closes #4396
|
|
|
|
|
| |
Break out system register definitions and accessors so that they're
usable by other parts of RTEMS.
|
|
|
|
|
|
|
|
|
|
| |
Move this diagnostic function to a separate file since it does not
provide a core function of the system.
Change license to BSD-2-Clause according to file history and
re-licensing agreement.
Update #3053.
|
|
|
|
|
|
|
| |
Move clock_nanosleep() to a separate file to avoid a dependency on errno
which pulls in the Newlib reentrancy support. This is an issue since
most parts which are pulled in cannot be garbage collected by the linker
due to the system initialization linker set.
|
|
|
|
|
|
|
| |
Rename _Stack_Free_nothing() in _Objects_Free_nothing() to make it
reusable for the message queue buffers.
Update #4007.
|
|
|
|
| |
This may reduce the code size a bit.
|
|
|
|
|
|
|
|
|
| |
Move rtems_calloc() since it only depends on rtems_malloc(). This may
make it easier to customize the heap allocator.
Change licence to BSD-2-Clause according to file history.
Update #3053.
|
|
|
|
| |
This reverts commit 3299dda2454a8847c670a732f6c12ef1f2cc5dd0.
|
|
|
|
| |
Update #3850
|
|
|
|
| |
Update #3850
|
|
|
|
| |
Update #3850
|
|
|
|
| |
Update #3850
|
|
|
|
| |
Update #3850
|
|
|
|
|
| |
Replace Objects_Name_or_id_lookup_errors with new Status_Control codes.
Get rid of the _Status_Object_name_errors_to_status lookup table.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Overview
========
The errata is worked around in the kernel without requiring toolchain
modifications. It is triggered the JMPL/RETT return from trap instruction
sequence never generated by the compiler and. There are also other
conditions that must must be true to trigger the errata, for example the
instruction that the trap returns to has to be a JMPL instruction. The
errata can only be triggered if certain data is corrected by ECC
(inflicted by radiation), thus it can not be triggered under normal
operation. For more information see:
www.gaisler.com/notes
Affected RTEMS target BSPs:
* GR712RC
* UT699
* UT700/699E
The work around is enabled by defining __FIX_LEON3_TN0018 at build time.
After applying the following GCC patch, GCC will set the define when
compiling for an affected multilib:
* GR712RC (-mcpu=leon3 -mfix-gr712rc)
* UT700/UT699E (-mpcu=leon3 -mfix-ut700)
* UT699 (-mcpu=leon -mfix-ut699)
When building for another multilib and TN0018 is still required, it
is possible to enable it on the RTEMS kernel configure line using the
TARGET_CFLAGS (-D__FIX_LEON3FT_TN0018) or other by other means.
The following GCC patch sets __FIX_LEON3FT_TN0018 for the affected RTEMS
multilibs:
---------
diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h
index 6570590..ddec98c 100644
--- a/gcc/config/sparc/rtemself.h
+++ b/gcc/config/sparc/rtemself.h
@@ -33,6 +33,8 @@
builtin_assert ("system=rtems"); \
if (sparc_fix_b2bst) \
builtin_define ("__FIX_LEON3FT_B2BST"); \
+ if (sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_ut699) \
+ builtin_define ("__FIX_LEON3FT_TN0018"); \
} \
while (0)
---------
Workaround Implementation
=========================
In general there are two approaches that the workaround uses:
A) avoid ECC restarting the RETT instruction
B) avoid returning from trap to a JMPL instruction
Where A) comes at a higher performance cost than B), so B) is used
where posssible. B) can be achived for certain returns from trap
handlers if trap entry is controlled by assembly, such as system calls.
A)
A special JMPL/RETT sequence where instruction cache is disabled
temporarily to avoid RETT containing ECC errors, and reading of RETT
source registers to "clean" them from incorrect ECC just before RETT
is executed.
B)
The work around prevents JMPL after system calls (TA instruction) and
modifies assembly code on return from traps jumping back to application
code. Note that for some traps the trapped instruction is always
re-executed and can therefore not trigger the errata, for example the
SAVE instruction causing window overflow or an float instruction causing
FPU disabled trap.
RTEMS SPARC traps workaround implementation:
NAME NOTE TRAP COMMENT
* window overflow 1 - 0x05 always returns to a SAVE
* window underflow 1 - 0x06 always returns to a RESTORE
* interrupt traps 2 - 0x10..1f special rett sequence workaround
* syscall 3 - 0x80 shutdown system - never returns
* ABI flush windows 2 - 0x83 special rett sequence workaround
* syscall_irqdis 4 - 0x89
* syscall_irqen 4 - 0x8A
* syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction
* syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to
B) _Internal_error() starting with SAVE
Notes:
1) no workaround needed because trap always returns to non-JMPL instruction
2) workaround implemented by special rett sequence
3) no workaround needed because system call never returns
4) workaround implemented by inserting NOP in system call generation. Thus
fall into 1) when workaround is enabled and no trap handler fix needed.
5) trap handler branches into both 1) and returning to _Internal_error()
which starts with a SAVE and besides since it shuts down the system that
RETT should never be in cache (only executed once) so fix not necessary
in this case.
Any custom trap handlers may also have to be updated. To simplify that,
helper work around assembly code in macros are available in a separate
include file <libcpu/grlib-tn-0018.h>.
Close #4155.
|
|
|
|
| |
Update #4267.
|
|
|
|
| |
Update #4267.
|
|
|
|
| |
Update #4269.
|
|
|
|
| |
Use the Python sorted() function to sort the "source" lists.
|
|
|
|
| |
Call _Thread_queue_Flush_critical() directly.
|
|
|
|
|
|
|
| |
Remove superfluous ASR_Information::signals_posted. Move code out of
trivial inline functions.
Update #4244.
|
|
|
|
|
|
|
|
|
| |
- Move the heap sbrk code into a separate routnine.
- Update heap and workspace greedy allocators to use the common
sbrk greedy support.
Closes #3982
|
|
|
|
| |
Update #4230.
|
|
|
|
|
|
| |
Rename _Nios2_ISR_Dispatch_with_shadow_non_preemptive() in
_Nios2_ISR_Dispatch_with_shadow_register_set(). Remove
_Nios2_ISR_Dispatch_with_shadow_preemptive().
|
|
|
|
|
|
|
|
| |
This BSP supports the Arm Fixed Virtual Platform. Only the Cortex-R52
processor configuration is supported by the BSP. It should be easy to
add support for other variants if needed.
Update #4202.
|