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9 daysbsps: Default to CPU counter benchmark timerSebastian Huber21-21/+21
Most BSPs which used the stubbed benachmark timer provide a CPU counter. All BSPs provide at least a stub CPU counter. Simply use the benchmark timer implementation using the CPU counter.
10 daysbsp/imx7: dl06 fails expectedlySebastian Huber2-0/+15
12 daysaarch64: always boot into EL1NSGedare Bloom5-28/+0
Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
13 daysbuild: Fix build item formatSebastian Huber2-8/+6
2021-12-22bsp/mrm332: Fix TLS support in linker command fileSebastian Huber1-2/+0
2021-12-17Remove powerpc/haleakala boardJoel Sherrill6-136/+0
Closes #4302.
2021-12-13bsps/arm: Add missing Cache Manager source fileSebastian Huber2-0/+2
2021-12-09spec: Update location of cadence I2CKinsey Moore2-3/+7
When the cadence I2C code was moved to a shared directory, the references were updated but the install locations weren't. This updates the install locations to match what out-of-tree applications expect.
2021-11-30libc: Optimize malloc() initializationSebastian Huber10-0/+10
The BSPs provide memory for the separate C Program Heap initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the separate C Program Heap and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs. Change licence to BSD-2-Clause according to file history. Update #3053.
2021-11-30score: Optimize Workspace Handler initializationSebastian Huber10-0/+10
The BSPs provide memory for the workspace initialization via _Memory_Get(). Most BSPs provide exactly one memory area. Only two BSPs provide more than one memory area (arm/altera-cyclone-v and bsps/powerpc/mpc55xxevb). Only if more than one memory area is provided, there is a need to use _Heap_Extend(). Provide two implementations to initialize the workspace handler and let the BSP select one of the implementations based on the number of provided memory areas. This gets rid of a dependency on _Heap_Extend(). It also avoids dead code sections for most BSPs.
2021-11-30build: Use common objects item for get memorySebastian Huber117-84/+210
2021-11-29bsp_specs: Delete last remnants of these.Joel Sherrill1-3/+0
Updates #3937.
2021-11-29build: Remove trailing white spaceSebastian Huber2-2/+2
2021-11-01aarch64: Break out MMU definitionsKinsey Moore4-0/+4
This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
2021-10-20spec/aarch64: Enable previously unbuildable testsKinsey Moore6-23/+0
The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due to a toolchain issue preventing them from compiling correctly. The binutils version that contains the fix has been released and integrated into RSB such that these two tests now build and operate correctly.
2021-10-13microblaze: Rework for RTEMS 6Alex White14-0/+522
This reworks the existing MicroBlaze architecture port and BSP to achieve basic functionality using the latest RTEMS APIs.
2021-09-21cpukit: Add AArch64 SMP SupportKinsey Moore3-0/+20
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
2021-09-21bsps/gicv2: Allow BSPs to define IRQ attributesKinsey Moore7-0/+7
ARM's GICv2 is configurable and its attributes vary between implementations including omission of specific interrupts. This allows BSPs to accomodate those varying implementations with customized attribute sets.
2021-09-21arm/lpc24xx: Use common test definition fileSebastian Huber4-68/+2
2021-09-14build: Remove invalid attributesSebastian Huber2-2/+0
2021-09-14bsps/arm: Fix ABI flags for Cortex-M4Sebastian Huber2-3/+5
Close #4504.
2021-09-09bsps/zynqmp: Added I2C support for ZynqMPStephen Clark5-0/+87
Added I2C drivers for ZynqMP and updated build system accordingly.
2021-09-09bsps/zynq: Moved general i2c files to shared directoriesStephen Clark1-3/+3
Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well. Moved these files to shared directory in anticipation of I2C support for ZynqMP.
2021-08-18build: Merge default-by-family into by-variantSebastian Huber682-685/+1
Prefix the BSP family name with "bsps/" to make it distinct to the BSP variant names. Update #4468.
2021-08-09bsps: Move optfdt* files to shared parent directorypranav24-246/+26
2021-07-26bsps/irq: Add rtems_interrupt_entry_install()Sebastian Huber4-9/+8
Add rtems_interrupt_entry_remove(). Split up irq-generic.c into several files. In particular, place all functions which use dynamic memory into their own file. Add optional macros to let the BSP customize the vector installation after installing the first entry and the vector removal before removing the last entry: * bsp_interrupt_vector_install() * bsp_interrupt_vector_remove() Use these new customization options in the m68k/genmcf548x BSP so re-use the generic interrupt controller support. Update #3269.
2021-07-26bsps/irq: Add rtems_interrupt_raise()Sebastian Huber3-0/+3
Add rtems_interrupt_raise_on() and rtems_interrupt_clear(). Add a default implementation which just returns RTEMS_UNSATISFIED for valid parameters. Update #3269.
2021-07-26rtems: Add rtems_interrupt_vector_enable()Sebastian Huber3-0/+3
Add rtems_interrupt_vector_disable(). Update #3269.
2021-07-26bsps/irq: Move handler iterate to separate fileSebastian Huber3-0/+3
Update #3269.
2021-07-26bsps/irq: Move get/set affinity to separate fileSebastian Huber3-0/+3
Update #3269.
2021-07-20Fixes for TMS570 BSPRobin Mueller1-1/+1
When compiling the lwIP port for the TMS570, there were issues with the BSP. Headers are expected in a folder named ti_herc which did not exist. This fixes the issue. Furthermore, there were multiple warnings about define redefinitions. This was fixed as well.
2021-07-20STM32H7 ethernet pin correctionsRobin Mueller3-0/+44
These patches were submitted a few months ago, but it was found out that the default-by-family: [] were missing in the GPIO .yml lines. This was fixed in this patch. This patch accounts for different pins for the ETH peripheral on STM32H7 devices. For example, the Nucleo H743ZI has slightly different pins than other STM32H7 boards.
2021-07-15build: Add missing default-by-familySebastian Huber2-0/+2
Update #4468.
2021-07-15build: Fix the motorola_powerpc default baudrateChris Johns1-2/+4
2021-07-15build: Use BSP family for optionsChris Johns692-0/+692
- Optionally add support for 'default-by-family' to allow option to be set by a family and so all related BSPs Close #4468
2021-07-06build: Add option to customize the LINKFLAGSSebastian Huber3-1/+19
2021-07-02bsps/imxrt: Simplify linkcmds and make it flexibleChristian Mauderer12-67/+96
Calling the memory FLASH and EXTRAM instead of FLEXSPI and SDRAM makes it simpler to support other types of external RAM. This patch also removes some of the calculations and improves names and documentation to avoid pitfalls. It removes a unnecessary memory definition. Update #4180
2021-07-02bsps/imxrt: Allow different ARM PLL settingChristian Mauderer1-0/+1
Update #4180
2021-07-01Revert "bsps/zynqmp: Allow any or all CGEMs to be enabled"Kinsey Moore5-72/+0
This reverts commit 10041a4cfc00d5f6876d3d6cfc30c23347b4cf42. This type of configuration does not belong in RTEMS and is better constrained to libbsd where the defines are actually being used.
2021-06-29spec/aarch64: fix abi flags for xilinx_versal_ilp32_vck190Gedare Bloom1-0/+1
2021-06-28bsps/zynqmp: Allow any or all CGEMs to be enabledKinsey Moore5-0/+72
Provide the options necessary to enable any combination of CGEM ethernet interfaces in LibBSD. The default is still CGEM3, so this should continue to operate as expected on typical Zynq Ultrascale+ MPSoC development hardware.
2021-06-24bsps/aarch64: replace boot options with asm switch codeGedare Bloom4-22/+0
2021-06-24bsps/aarch64: add non-secure mode and versal supportGedare Bloom9-6/+68
2021-06-24bsps/aarch64: add physical secure timerGedare Bloom2-0/+33
2021-06-24aarch64/xilinx-versal: new BSPs for qemu and vck190Gedare Bloom18-0/+516
2021-06-24sparc: More reliable bad trap handlingSebastian Huber3-3/+0
Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap() for all unexpected traps. This enables a proper RTEMS fatal error handling right from the start. Do not rely on the stack and register settings which caused an unexpected trap. Use the ISR stack of the processor to do the fatal error handling. Save the full context which caused the trap. Fatal error handler may use it for error logging. Unify the _CPU_Exception_frame_print() implementations and move it to cpukit. Update #4459.
2021-06-24bsp/generic_or1k: Remove incomplete IRQ supportSebastian Huber1-3/+1
Update #3269.
2021-06-23bsps/powerpc, bsps/shared: Move remaining legacy networking header filesVijay Kumar Banerjee2-5/+0
2021-06-09aarch64: add qemu bsps for cortex-a72Gedare Bloom12-0/+394
The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
2021-06-07arm/fvp: Remove unused GICv2 BSP optionSebastian Huber2-6/+1
Update #4202.