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This patch moves the bcm2835 system timer driver in the arm/raspberrypi directory to the shared directory and adjusts arm/raspberrypi BSP.
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Make the clock driver parameters configurable. Use the maximum counter
frequency to get the best time resolution. Decouple the CPU counter from the
timecounter. Make the tick catch up handling more robust. Add a validation
test for the tick catch up.
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Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
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This helps to provide a shared implementation of the kernel I/O support.
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Add a BSP variant without a board-specific name.
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Add a BSP variant without a board-specific name.
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The base addresses and IRQ numbers for UART 0 and 1 were interchanged.
Fix this and set BSP_CONSOLE_MINOR to 0 for this BSP family.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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The RAM origin had an unnecessary alignment requirement and the RAM
lenght had a reference that couldn't possibly be used. This removes
those obsolete option specifiers.
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This enables the VME support for the MVME2500. Note that the PCIe
support from libbsd is used. So you need the related libbsd patches for
this to work.
If the drivers in libbsd are not enabled, the linker should not pick up
anything from this patch.
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This option replaces BSP_OSCILATOR_CLOCK. It may be used in PLL setup
calculatios.
Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Remove obsolete tms570ls3137_hdk_with_loader BSP variant. With the new
memory origin/size build options this variant is no longer required.
Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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Update #4982.
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This reverts commit d1d3ceb502cf4075c28a052b36630125387e1026.
Per discussions on devel@ and Discord.
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Hi all, this is my first email patch submission and my first contribution to RTEMS, so please give any
feedback you have!
This patch enables interrupt driven data reception on USART ports on
STM32F4 series chips. This feature is gated behind the config flag
BSP_CONSOLE_USE_INTERRUPTS. If this flag is not set to True, the older
polling implementation will be used. I tested this feature on STM32F401CE
(blackpill) and STM32 Nucleo F411RE boards, with both capable of keeping
up with a 115200 baud continous data stream. With the older polling
implementation, both would drop bytes at 9600 baud. In addition, I
updated the implementation of usart_set_attributes to support changing
the baud rate of the USART port based on the input speed.
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Add the BSP option BSP_START_VECTOR_ADDRESS_TABLE_ALIGNMENT to
optionally define an alignment of the vector address table begin.
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This patch adds basic support for the following boards:
xilinx_zynq_pynq - PYNQ Z1 / Z2
xilinx_zynq_microzed - MicroZed 7010 / 7020
xilinx_zynq_picozed - PicoZed 7010 / 7015 / 7020 / 7030
xilinx_zynq_zybo - ZYBO
xilinx_zynq_zybo_z7 - ZYBO Z7-10 / Z7-20
N.b. Arty Z7-20 is basically a PYNQ Z1 - different board
color and updated Eth PHY.
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With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
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This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
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Close #4954.
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Merge the timecounter and CPU counter support for the leon3 BSP family.
Remove now unused functions from the CPU counter support of the erc32
and leon3 BSPs.
Update #4954.
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