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Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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Updates #4705
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Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
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When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
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Update #4267.
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Use the Python sorted() function to sort the "source" lists.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
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This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
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Update #3818.
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