| Commit message (Collapse) | Author | Files | Lines |
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This change allows for the pins assigned to UART7 to be reconfigured via
config.ini.
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This adds support for the STM32H750B-DK discovery kit. This kit includes
a built-in STLINKv3 debugger which provides a USB serial bridge for
USART3. USART1 is routed to the Arduino header and USART2 is routed to
the STMOD connector. This BSP reuses what would otherwise be duplicated
files from the stm32h747i-disco BSP. Note that system_stm32h7xx.c has
been imported from the STM repository with two minor changes wrapped
with #if __rtems__. This hardware has been tested with hello and ticker.
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There is no point in wasting precious memory space on enforced section
alignment for the purpose of MPU which is not implemented on M4 core
anyway.
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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The patch also enables usage of the option on imxrt and stm32h7 based BSPs.
Sponsored-By: Precidata
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The QSPI memory is initialized and used only when the BSP configure file
sets QSPI memory size to non-zero value. Currently QSPI is run in memory
mapped mode which allows future RTEMS binary linkage and upload into QSPI
memory.
Sponsored-By: Precidata
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Merge the "default" and "default-by-variant" attributes. Use an
"enabled-by" expression to select the default value based on the enabled
set. This makes it possible to select default values depending on other
options. For example you could choose memory settings based on whether
RTEMS_SMP is enabled or disabled.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
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Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
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Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a
custom representer for integer default values to format all build items.
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Updates #4705
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Propagate the group defined cppflags, cflags, and cxxflags from parent groups
to child items through the build item context.
Update #4670.
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Nucleo board does not provide any external memory so code does not have
any function here anyway.
Sponsored-By: Precidata
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The idea here is to prepare for better per-board specialization
of the hooks function code.
Sponsored-By: Precidata
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Nucleo does not have any SDRAM, so 0 size is the only possible right
choice here.
Sponsored-By: Precidata
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Nucleo does not have any SDRAM so default linkage to SDRAM does not make
any sense here.
Sponsored-By: Precidata
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This is the default configuration of the board out of the box.
Any other possible/supported configuration requires soldering,
so definitely not out of the box experience.
Sponsored-By: Precidata
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This patch adds stm32h747i-disco-m4 BSP variant and puts it in sync
with the stm32h747i-disco BSP variant hardware support. That means,
only USART 1, 2 and UART 8 are enabled. Also SDRAM 2 is set to 32MB,
SDRAM 1 size is set to 0.
Sponsored-By: Precidata
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This means:
SDRAM 1: 0
SDRAM 2: 32 MB
Sponsored-By: Precidata
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This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors. That means only USART1 and 2
and UART8 are enabled.
Sponsored-By: Precidata
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Sponsored-By: Precidata
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This means:
SDRAM 1: 0
SDRAM 2: 32 MB
Sponsored-By: Precidata
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This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.
Sponsored-By: Precidata
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This is minimalist configuration for the stm32h757i-eval-m4 BSP provided
here. The only general enhancement worth mention is a flash origin address
configuration which is needed for simplification as M4 core boots
from second flash bank which starts at 0x8100000 by default. The boot
address of the core may be changed by using STM32CubeProgrammer. If done
so then also BSP configuration needs to be changed accordingly.
As the BSP variant is running on M4 core, there is also more configuration
changes required here. E.g. boot core and ABI (compilation flags)
in comparison with stm32h757i-eval BSP. On the other hand, C code is shared
completely with this BSP variant.
Sponsored-By: Precidata
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This is done in preparation for future Cortex-M4 based BSP variants
which do not provide cache at all.
Sponsored-By: Precidata
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This means:
SDRAM 1: 0
SDRAM 2: 32 MB
Sponsored-By: Precidata
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Sponsored-By: Precidata
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Sponsored-By: Precidata
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This patch disables all U(S)ARTs which are not supported by the board
itself and its provided connectors.
Sponsored-By: Precidata
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This is minimalist configuration for the stm32h757i-eval BSP provided
here. The only general enhancement worth mention is boot core
configuration which is needed here as this is the first dual-core board
supported by stm32h7 BSP family and we need to choose boot core in order
to get C files compiling well.
Sponsored-By: Precidata
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Also adjust BSP spec file to make it buildable with board files.
Sponsored-By: Precidata
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Also adjust BSP spec file to make it buildable with board files.
Sponsored-By: Precidata
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Also adjust BSP spec file to make it buildable with board files.
Sponsored-By: Precidata
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The patch is done in preparation for stm32h7 BSP tree refactoring.
Sponsored-By: Precidata
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Making this BSP a small memory target is a bit coarse and could be improved.
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The patch is needed due to smaller SRAM and completely disabled
SDRAM on the BSP variant.
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Caveat: SDRAM 1 is completely disabled for now.
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function
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Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
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