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Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
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Add a BSP variant without a board-specific name.
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QEMU is known to fail certain tests intermittently due to clock tick
delivery issues. This defines those tests as intermittent for BSPs
intended to run on QEMU alone.
Updates #4922
Updates #4072
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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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This adds the glue code necessary to allow JFFS2 to operate on top of
NAND memory hosted by the XNandPsu peripheral/driver.
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The objxilinxsupport build object was accidentally included twice in
some of the ZynqMP BSPs by two different drivers that required it. This
commit manually deduplicates the inclusions by moving that inclusion to
the BSP. Duplication of object inclusions is considered a bug and can
cause race conditions in the build system.
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Merge the "default" and "default-by-variant" attributes. Use an
"enabled-by" expression to select the default value based on the enabled
set. This makes it possible to select default values depending on other
options. For example you could choose memory settings based on whether
RTEMS_SMP is enabled or disabled.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
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Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
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Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a
custom representer for integer default values to format all build items.
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This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.
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These files are already provided by "../../objirq".
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This adds a BSP variant for the ZynqMP BSP family to support the
Innoflight CFC-400X platform. To properly support the CFC-400X, device
trees were added to the ZynqMP platform due to both the optional
management interface as well as alternate physical configuration of the
ethernet interfaces.
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This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently
only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in
64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry
Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM
BSP.
Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently.
Mini-UART is not supported. Mini-UART is default UART on the board so it needs
to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support
for additional 4 PL011-UARTs on the board.
The raspberrypi.h includes many of the address required for the future
development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore
Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
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- Versal has IO mapped to the upper 64bit address space and
needs full 64bit addresses.
- Add xilinx_versal_aiedge for custom hardware
- Make the hardware settings the defaults and qemu as variants
Closes #4693
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Updates #4705
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- Support DDRMC0 region 0 up to 2G in size
- Support DDRMC0 region 1 with DDR memory greater than 2G
up to the DDRMC0 max amount
- Extend the heap with region 1's memory
Closes #4684
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Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
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There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
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Propagate the group defined cppflags, cflags, and cxxflags from parent groups
to child items through the build item context.
Update #4670.
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Set the constraint to be 64bits to allow the complete address range.
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Separate the Interrupt Manager implementation from the generic Arm GICv3
support. Move parts of the Arm GICv3 support into a new header file. This
helps to support systems with a clustered structure in which multiple GICv3
instances are present. For example, two clusters of two Cortex-R52 cores where
each cluster has a dedicated GICv3 instance.
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Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
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When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
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This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
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The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due
to a toolchain issue preventing them from compiling correctly. The
binutils version that contains the fix has been released and integrated
into RSB such that these two tests now build and operate correctly.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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Added I2C drivers for ZynqMP and updated build system accordingly.
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Prefix the BSP family name with "bsps/" to make it distinct to the BSP
variant names.
Update #4468.
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- Optionally add support for 'default-by-family' to allow
option to be set by a family and so all related BSPs
Close #4468
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This reverts commit 10041a4cfc00d5f6876d3d6cfc30c23347b4cf42.
This type of configuration does not belong in RTEMS and is better
constrained to libbsd where the defines are actually being used.
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Provide the options necessary to enable any combination of CGEM ethernet
interfaces in LibBSD. The default is still CGEM3, so this should
continue to operate as expected on typical Zynq Ultrascale+ MPSoC
development hardware.
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The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
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Add the BSPs for running on the ZU3EG Ultrascale+ Zynq MPSoC and alter
the option defaults necessary for them to run properly using the
standard BOOT.BIN configured for PetaLinux that comes in the Out-of-Box
package.
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Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.
In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
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The default available RAM on the A53 BSP is quite small at 8MB. This
bumps that to 128MB to avoid allocation failures in tmcontext01 caused
by large allocations on a cache size of 16MB reported by the system
registers in QEMU.
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Updates #4321
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