summaryrefslogtreecommitdiffstats
path: root/spec/build/bsps/aarch64 (follow)
Commit message (Collapse)AuthorAgeFilesLines
* bsps/shared: Add Xilinx-AXI SPI driver to wafJan Sommer2021-03-301-0/+2
| | | | Updates #4321
* bsps/xilinx_zynq: Add SPI driver to wafJan Sommer2021-03-101-0/+2
| | | | Updates #4320
* spec/aarch64: Enable previously disabled testsAlex White2021-03-082-18/+2
| | | | | This enables several testsuites that were initially disabled during development.
* spec/aarch64: Rename ZynqMP QEMU BSPsKinsey Moore2021-03-053-3/+3
| | | | | | The current ZynqMP BSPs don't have _qemu in their name as do all other RTEMS BSPs that are specifically made to run on QEMU. This fixes the naming for those ZynqMP BSP variants for easier identification.
* spec/aarch64: Remove sp37 from intermittent testsAlex White2021-03-052-2/+0
|
* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-052-2/+0
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* validation: Fix for 64-bit targetsSebastian Huber2021-03-042-6/+0
| | | | Closes #4179.
* bsps: Add default rtems_get_target_hash()Sebastian Huber2021-02-262-0/+2
| | | | Update #4267.
* build: Sort source listsSebastian Huber2021-02-242-11/+11
| | | | Use the Python sorted() function to sort the "source" lists.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-233-2/+1
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* spec: Move zynq-uart into its own objectKinsey Moore2020-12-041-0/+2
| | | | | | | Currently, zynq-uart code is always built and has some requirements for BSPs that use it. Instead of making all BSPs satisfy that requirement or working around it by setting defaults, this moves the zynq-uart code into its own spec build object so it can be included if needed.
* Add AArch64 ZynpMP BSPKinsey Moore2020-12-0413-0/+433
| | | | | | | | This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC (ZynqMP) family of chips. It is configured to be usable on the Qemu ZCU102 machine definition and should be almost trivially portable to ZynqMP development boards and custom hardware. It is also configured to be usable with libbsd.
* spec/a53: Fix SPDX linesKinsey Moore2020-12-022-4/+4
|
* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-021-1/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* spec/a53: Set conditionally failing test stateKinsey Moore2020-11-241-14/+22
| | | | | | | | | | The spintrcritical03-05 and psx12 tests are known to fail on Qemu when the host system is heavily loaded. A single run of Qemu per core during a testsuite run tends to yield positive results, but any additional load on a system will result in test failures. This patch also applies the correct expected test state for intermittent failures so that those tests will still build.
* spec/aarch64: Only apply SUBALIGN(4) to ILP32Kinsey Moore2020-11-231-0/+1
| | | | | | | The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds was previously present on LP64 builds and causes no issues within RTEMS, but causes relocation/alignment issues when building libbsd. This restricts those alignment changes to ILP32 builds.
* spec/aarch64: Ensure that libbsd can build properlyKinsey Moore2020-11-231-0/+4
| | | | | These files are required for libbsd to build against the AArch64 A53 BSPs.
* build: Fix formatSebastian Huber2020-10-126-12/+12
|
* bsps: Add Cortex-A53 ILP32 BSP variantKinsey Moore2020-10-053-1/+96
| | | | | | This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
* bsps: Add Cortex-A53 LP64 basic BSPKinsey Moore2020-10-0512-0/+341
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 08:18:52 +0000