| Commit message (Collapse) | Author | Age | Files | Lines |
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Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
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When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
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This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
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The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due
to a toolchain issue preventing them from compiling correctly. The
binutils version that contains the fix has been released and integrated
into RSB such that these two tests now build and operate correctly.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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Added I2C drivers for ZynqMP and updated build system accordingly.
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Prefix the BSP family name with "bsps/" to make it distinct to the BSP
variant names.
Update #4468.
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- Optionally add support for 'default-by-family' to allow
option to be set by a family and so all related BSPs
Close #4468
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This reverts commit 10041a4cfc00d5f6876d3d6cfc30c23347b4cf42.
This type of configuration does not belong in RTEMS and is better
constrained to libbsd where the defines are actually being used.
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Provide the options necessary to enable any combination of CGEM ethernet
interfaces in LibBSD. The default is still CGEM3, so this should
continue to operate as expected on typical Zynq Ultrascale+ MPSoC
development hardware.
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The a72 BSPs are identical to the a53 BSPs just changing a53 to a72.
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Add the BSPs for running on the ZU3EG Ultrascale+ Zynq MPSoC and alter
the option defaults necessary for them to run properly using the
standard BOOT.BIN configured for PetaLinux that comes in the Out-of-Box
package.
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Currently, the AArch64 BSPs have a hard time running on real hardware
without building the toolchain and the bsps with -mstrict-align in
multiple places. Configuring the MMU on these chips allows for unaligned
memory accesses for non-device memory which avoids requiring strict
alignment in the toolchain and in the BSPs themselves.
In writing this driver, it was found that the synchronous exception
handling code needed to be rewritten since it relied on clearing SCTLR_EL1 to
avoid thread stack misalignments in RTEMS_DEBUG mode. This is now
avoided by exactly preserving thread mode stack and flags and the new
implementation is compatible with the draft information provided on the
mailing list covering the Exception Management API.
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The default available RAM on the A53 BSP is quite small at 8MB. This
bumps that to 128MB to avoid allocation failures in tmcontext01 caused
by large allocations on a cache size of 16MB reported by the system
registers in QEMU.
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Updates #4321
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Updates #4320
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This enables several testsuites that were initially disabled during
development.
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The current ZynqMP BSPs don't have _qemu in their name as do all other
RTEMS BSPs that are specifically made to run on QEMU. This fixes the
naming for those ZynqMP BSP variants for easier identification.
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Remove usage of SUBALIGN() in aarch64 linkcmds which works around a
difference in behavior on AArch64 platforms. This is no longer necessary
since alignment is now enforced explicitly.
Closes #4178.
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Closes #4179.
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Update #4267.
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Use the Python sorted() function to sort the "source" lists.
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This avoids a function call overhead in the interrupt dispatching.
Update #4202.
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Currently, zynq-uart code is always built and has some requirements for
BSPs that use it. Instead of making all BSPs satisfy that requirement or
working around it by setting defaults, this moves the zynq-uart code
into its own spec build object so it can be included if needed.
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This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
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The spintrcritical03-05 and psx12 tests are known to fail on Qemu when
the host system is heavily loaded. A single run of Qemu per core
during a testsuite run tends to yield positive results, but any
additional load on a system will result in test failures.
This patch also applies the correct expected test state for intermittent
failures so that those tests will still build.
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The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
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These files are required for libbsd to build against the AArch64 A53
BSPs.
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This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
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This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
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