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* spec: Add QEMU test annotationsKinsey Moore2023-07-101-30/+3
| | | | | | | | | QEMU is known to fail certain tests intermittently due to clock tick delivery issues. This defines those tests as intermittent for BSPs intended to run on QEMU alone. Updates #4922 Updates #4072
* build: Use enabled by for defaultsSebastian Huber2023-01-176-15/+18
| | | | | | | | | | | | | | Merge the "default" and "default-by-variant" attributes. Use an "enabled-by" expression to select the default value based on the enabled set. This makes it possible to select default values depending on other options. For example you could choose memory settings based on whether RTEMS_SMP is enabled or disabled. The change was tested by comparing the output of ./waf bspdefaults before and after the change.
* build: Format build itemsSebastian Huber2023-01-174-4/+4
| | | | | Use yaml.dump(data, default_flow_style=False, allow_unicode=True) with a custom representer for integer default values to format all build items.
* build: Add reason to test state definitionsSebastian Huber2023-01-171-25/+34
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* spec/bsps: Do not install tm27.hChris Johns2022-08-221-1/+0
| | | | Updates #4705
* irq/arm-gicv3.h: Customize CPU Interface initSebastian Huber2022-07-122-1/+2
| | | | | | | Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
* build: Add cppflags, cflags, cxxflags to groupsSebastian Huber2022-07-041-0/+3
| | | | | | | Propagate the group defined cppflags, cflags, and cxxflags from parent groups to child items through the build item context. Update #4670.
* aarch64: always boot into EL1NSGedare Bloom2022-01-121-2/+0
| | | | | | | | | | | Always start the executive in Exception Level 1, Non-Secure mode. If we boot in EL3 Secure with GICv3 then we have to initialize the distributor and redistributor to set up G1NS interrupts early in the boot sequence before stepping down from EL3S to EL1NS. Now there is no need to distinguish between secure and non-secure world execution after the primary core boots, so get rid of the AARCH64_IS_NONSECURE configuration option.
* build: Use common objects item for get memorySebastian Huber2021-11-302-1/+2
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* aarch64: Break out MMU definitionsKinsey Moore2021-11-011-0/+1
| | | | | | This moves the AArch64 MMU memory type definitions into cpukit for use by libdebugger since remapping of memory is required to insert software breakpoints.
* spec/aarch64: Enable previously unbuildable testsKinsey Moore2021-10-201-4/+0
| | | | | | | The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due to a toolchain issue preventing them from compiling correctly. The binutils version that contains the fix has been released and integrated into RSB such that these two tests now build and operate correctly.
* build: Merge default-by-family into by-variantSebastian Huber2021-08-186-6/+0
| | | | | | | Prefix the BSP family name with "bsps/" to make it distinct to the BSP variant names. Update #4468.
* build: Use BSP family for optionsChris Johns2021-07-156-0/+6
| | | | | | | - Optionally add support for 'default-by-family' to allow option to be set by a family and so all related BSPs Close #4468
* bsps/aarch64: add non-secure mode and versal supportGedare Bloom2021-06-241-0/+2
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* bsps/a53: Increase available RAMKinsey Moore2021-05-271-1/+1
| | | | | | | The default available RAM on the A53 BSP is quite small at 8MB. This bumps that to 128MB to avoid allocation failures in tmcontext01 caused by large allocations on a cache size of 16MB reported by the system registers in QEMU.
* spec/aarch64: Enable previously disabled testsAlex White2021-03-081-9/+1
| | | | | This enables several testsuites that were initially disabled during development.
* spec/aarch64: Remove sp37 from intermittent testsAlex White2021-03-051-1/+0
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* bsps/aarch64: Resolve usage of SUBALIGN()Kinsey Moore2021-03-051-1/+0
| | | | | | | | Remove usage of SUBALIGN() in aarch64 linkcmds which works around a difference in behavior on AArch64 platforms. This is no longer necessary since alignment is now enforced explicitly. Closes #4178.
* validation: Fix for 64-bit targetsSebastian Huber2021-03-041-3/+0
| | | | Closes #4179.
* bsps: Add default rtems_get_target_hash()Sebastian Huber2021-02-261-0/+1
| | | | Update #4267.
* build: Sort source listsSebastian Huber2021-02-241-6/+6
| | | | Use the Python sorted() function to sort the "source" lists.
* bsps: Use header file for GIC architecture supportSebastian Huber2020-12-231-1/+0
| | | | | | This avoids a function call overhead in the interrupt dispatching. Update #4202.
* spec/a53: Fix SPDX linesKinsey Moore2020-12-022-4/+4
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* bsps: Move ARM GICv2 driver to bsps/sharedKinsey Moore2020-12-021-1/+1
| | | | | This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64 code.
* spec/a53: Set conditionally failing test stateKinsey Moore2020-11-241-14/+22
| | | | | | | | | | The spintrcritical03-05 and psx12 tests are known to fail on Qemu when the host system is heavily loaded. A single run of Qemu per core during a testsuite run tends to yield positive results, but any additional load on a system will result in test failures. This patch also applies the correct expected test state for intermittent failures so that those tests will still build.
* spec/aarch64: Only apply SUBALIGN(4) to ILP32Kinsey Moore2020-11-231-0/+1
| | | | | | | The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds was previously present on LP64 builds and causes no issues within RTEMS, but causes relocation/alignment issues when building libbsd. This restricts those alignment changes to ILP32 builds.
* build: Fix formatSebastian Huber2020-10-126-12/+12
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* bsps: Add Cortex-A53 ILP32 BSP variantKinsey Moore2020-10-053-1/+96
| | | | | | This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.
* bsps: Add Cortex-A53 LP64 basic BSPKinsey Moore2020-10-0510-0/+303
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with interrupt support using GICv3 and clock support using the ARM GPT.