| Commit message (Collapse) | Author | Age | Files | Lines |
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Close #3720.
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The register definition for the CP15 PMCR (performance monitor control
register) has the bits for X (export enable) and D (clock divider
enable) backwards. Correct them according to ARMv7-A/R Architecture
Reference Manual, Rev C, Section B4.1.117.
Consequences: On an implementation that starts off with D set at reset,
the clock divider will not be disabled by using RTEMS' definition of the
D bit.
Tested by using the counter on Xilinx Zynq 7020 to measure some atomic
accesses and cache flushing operations.
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Updates #3687
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Generate Doxygen output in doc and ignore this directory in Git. Add
RTEMS logo. The Doxygen documentation is now built using the source
tree. Just invoke "doxygen" in the top-level source directory.
The Doxyfile works also with at least Doxygen 1.8.13 and Doxygen 1.8.14.
Update #3705.
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Remove the priority node only in case it is active.
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This makes the @file documentation independent of the actual file name.
Update #3707.
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The system register in use for retrieval of the virtual timer value was
mistakenly copied from the physical timer value retrieval function.
Virtual timer value retrieval should use the same system register as the
virtual timer value setter.
Close #3699.
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Coverity 1399717
Updates #3686
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Coverty 1442636
Updates #3686
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space.
Coverity issue 1442540
Updates #3686
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Coverity issue 1442641
Updates #3686
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- Allow an allocator to lock the allocations. This is needed to
lock the heap allocator so the text and trampoline table are
as close together as possible to allow for the largest possible
object file size.
- Update the default heap allocator to lock the heap allocator.
- Update ELF loading to lock the allocator.
Updates #3685
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Recursive usage of the same pthread_once_t results now in a deadlock.
Previously, an error of EINVAL was returned. This usage scenario is
invalid according to the POSIX pthread_once() specification.
Close #3334.
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Updates #3687
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Close #3692
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- Add support for architecure sections that can be handled by the
architecture back end.
- Add trampoline/fixup support for PowerPC. This means the PowerPC
now supports large memory loading of applications.
- Add a bit allocator to manage small block based regions of memory.
- Add small data (sdata/sbss) support for the PowerPC. The support
makes the linker allocated small data region of memory a global
resource available to libdl loaded object files.
Updates #3687
Updates #3685
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- Add trampolines to support relocs that are out of range on
support architectures.
- Support not loading separate text/data sections in an object
file if the symbol provided in the section is a duplicate.
A base image may have pulled in part of an object and another
part needs to be dynamically loaded.
- Refactor the unresolved handling to scale to hundreds of
unresolved symbols when loading large number of files.
Updates #3685
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- Trampolines or fixups for veneers provide long jump support
for instruciton sets that implement short relative address
branches. The linker provides trampolines when creating a
static image. This patch adds trampoline support to libdl
and the ARM architecture.
- The dl09 test requires enough memory so modules are outside
the relative branch instruction ranges for the architecture.
Updates #3685
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- Fix the handling of pending objects.
- Add a constructor flags in objects to track then being called.
Closes #2921
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- Create 2 archives.
- Load 1 object file which loads 6 object files from the libraries.
Updates #3686
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- Load archive symbol tables to support searching of archives
for symbols.
- Search archive symbols and load the object file that contains
the symbol.
- Search the global and archives until all remaining unresolved symbols
are not found. Group the loaded object files in the pending queue.
- Run the object file and loaded dependents as a group before adding to the
main object list.
- Remove orphaned object files after references are removed.
Updates #3686
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Closes #3298
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Closes #3684
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We have to read the first node again once we obtained the lock since it
may have aready changed.
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We must add/remove the priority queue to the FIFO of priority queues.
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Update #3665.
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Add low level event recording infrastructure for system and user
defined events. The infrastructure is able to record high frequency
events such as
* SMP lock acquire/release,
* interrupt entry/exit,
* thread switches,
* UMA zone allocate/free, and
* Ethernet packet input/output, etc.
It allows post-mortem analysis in fatal error handlers, e.g. the last
events are in the record buffer, the newest event overwrites the oldest
event. It is possible to detect record buffer overflows for consumers
that expect a continuous stream of events, e.g. to display the system
state in real-time.
The implementation supports high-end SMP machines (more than 1GHz
processor frequency, more than four processors).
Add a new API instead. The implementation uses per-processor data
structures and no atomic read-modify-write operations. It is uses
per-processor ring buffers to record the events.
The CPU counter is used to get the time of events. It is combined with
periodic uptime events to synchronize it with CLOCK_REALTIME.
The existing capture engine tries to solve this problem also, but its
performance is not good enough for high-end production systems. The
main issues are the variable-size buffers and the use of SMP locks for
synchronization. To fix this, the API would change significantly.
Update #3665.
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This prevents a cyclic dependency between <rtems/score/cpu.h> and
<rtems/score/address.h>.
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Update #3678.
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Update #3678.
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Ensure that interrupts are disabled while acquiring an ISR lock.
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The CPU_ALIGNMENT must not be zero, this is also checked via a static
assertion. Fix formatting.
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Update #3666.
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It must be enabled, since the context switch code does not save/restore
the interrupt status.
Update #3433.
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In case the robust thread dispatch is enabled by the CPU port, then the
interrupt level must not be changed through the task mode.
Update #3000.
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Update #3000.
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Update #3000.
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