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2013-06-14score: Add _Chain_Insert_ordered_unprotected()Sebastian Huber1-0/+41
2013-06-12smp: Fix _Thread_Dispatch_decrement_disable_levelSebastian Huber1-1/+7
We must obtain the processor ID after interrupts are disabled since a non-optimizing compiler may store the value on the stack and read it back.
2013-06-12smp: Protect decrement operationSebastian Huber1-4/+4
2013-06-12smp: Add and use _Per_CPU_Lock_acquire()Sebastian Huber2-6/+12
Add and use _Per_CPU_Lock_release().
2013-06-12score: Avoid cyclic include dependencySebastian Huber1-1/+2
2013-06-12score: Add missing includeSebastian Huber1-0/+1
2013-06-12score: Always provide <rtems/score/smplock.h>Sebastian Huber4-8/+12
2013-06-07smp: Set state PER_CPU_STATE_UP on main processorSebastian Huber1-4/+6
2013-06-07score: Add and use _Objects_Put()Sebastian Huber11-41/+74
Add and use _Objects_Put_without_thread_dispatch(). These two functions pair with the _Objects_Get() function. This helps to introduce object specific SMP locks to avoid lock contention.
2013-06-07score: Add _Objects_Put_for_get_isr_disable()Sebastian Huber2-0/+20
Provide SMP support. The ISR disable/enable is not enough to ensure mutual exclusion for SMP configurations.
2013-06-07score: Align _Objects_Get_isr_disable()Sebastian Huber1-2/+1
Align ISR disable/enable sequence in _Objects_Get_isr_disable() with thread dispatch disable/enable sequence in _Objects_Get().
2013-06-07score: Move thread dispatch content to new fileSebastian Huber25-247/+291
Move thread dispatch declarations and inline functions to new header <rtems/score/threaddispatch.h> to make it independent of the Thread_Control structure. This avoids a cyclic dependency in case thread dispatch functions are used for the object implementation.
2013-06-07score: Simplify _CORE_mutex_Seize_interrupt_try*Sebastian Huber3-17/+17
2013-06-07score: Simplify _CORE_semaphore_Seize_isr_disableSebastian Huber1-5/+5
2013-06-07score: Simplify _Thread_Create_idle_helper()Sebastian Huber1-9/+0
The _Thread_Initialize() function has nothing to do with thread dispatching it simply initializes the thread control.
2013-05-31smp: Add ARM supportSebastian Huber6-2/+180
2013-05-31smp: Add PowerPC supportSebastian Huber4-1/+116
2013-05-31smp: New SMP lock APISebastian Huber18-463/+470
Move the SMP lock implementation to the CPU port. An optimal SMP lock implementation is highly architecture dependent. For example the memory models may be fundamentally different. The new SMP lock API has a flaw. It does not provide the ability to use a local context for acquire and release pairs. Such a context is necessary to implement for example the Mellor-Crummey and Scott (MCS) locks. The SMP lock is currently used in _Thread_Disable_dispatch() and _Thread_Enable_dispatch() and makes them to a giant lock acquire and release. Since these functions do not pass state information via a local context there is currently no use case for such a feature.
2013-05-31score: Mark as no returnSebastian Huber1-5/+7
Mark rtems_smp_secondary_cpu_initialize() as no return.
2013-05-31score: Remove idle field of Per_CPU_ControlSebastian Huber3-10/+24
This field is unused except for special case simulator clock drivers. In these places use an alternative. Add and use _Thread_Set_global_exit_status() and _Thread_Get_global_exit_status().
2013-05-29smp: Move secondary CPU initialization requestSebastian Huber1-6/+0
Do not assume that the scheduler selects the main processor for the initialization thread.
2013-05-29smp: Use _CPU_Fatal_halt()Sebastian Huber1-2/+2
2013-05-29smp: Simplify SMP initialization sequenceSebastian Huber8-189/+252
Delete bsp_smp_wait_for(). Other parts of the system work without timeout, e.g. the spinlocks. Using a timeout here does not make the system more robust. Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The Per_CPU_State follows the Score naming conventions. Add _Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to change and observe states. Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer. Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive() functions provided by the CPU port. Use these functions in _Per_CPU_Change_state() and _Per_CPU_Wait_for_state(). Add prototype for _SMP_Send_message(). Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is now performed in rtems_smp_secondary_cpu_initialize(). Issuing the first context switch in the context of the inter-processor interrupt is not possible on systems with a modern interrupt controller. Such an interrupt controler usually requires a handshake protocol with interrupt acknowledge and end of interrupt signals. A direct context switch in an interrupt handler circumvents the interrupt processing epilogue and may leave the system in an inconsistent state. Release lock in rtems_smp_process_interrupt() even if no message was delivered. This prevents deadlock of the system. Simplify and format _SMP_Send_message(), _SMP_Request_other_cores_to_perform_first_context_switch(), _SMP_Request_other_cores_to_dispatch() and _SMP_Request_other_cores_to_shutdown().
2013-05-29smp: Delete bsp_smp_secondary_cpu_initialize()Sebastian Huber2-21/+19
Do not call bsp_smp_secondary_cpu_initialize() in rtems_smp_secondary_cpu_initialize(). This allows more flexibilty in the BSP low-level code. Specify context requirements for a call to rtems_smp_secondary_cpu_initialize().
2013-05-29smp: Delete rtems_smp_send_message()Sebastian Huber1-15/+0
2013-05-29smp: Delete rtems_smp_initialize_per_cpu()Sebastian Huber1-10/+0
2013-05-29smp: Simplify main CPU initializationSebastian Huber2-12/+23
Call _SMP_Handler_initialize() later and move bsp_smp_initialize() into _SMP_Handler_initialize(). Change bsp_smp_initialize() prototype to match integer types of calling context.
2013-05-29smp: Make CPU_ALLOCATE_INTERRUPT_STACK optionalSebastian Huber2-13/+13
2013-05-29smp: Rely on BSS initializationSebastian Huber1-5/+0
The _Per_CPU_Information is part of the BSS segment and must be zero initialized. Some processors may already poll some per-CPU fields and wait for a state change at this point.
2013-05-29smp: Include missing headerSebastian Huber1-0/+2
2013-05-27arm: Add CPU specific idle thread for ARMv7Sebastian Huber4-4/+10
2013-05-27arm: Fix CPSR and SPSR accessSebastian Huber2-8/+8
The GNU assembler translates for example a msr spsr, rN into msr SPSR_fc, rN This would update only a subset of the register and leads to an incomplete exceptions restore sequence resulting in system corruption. Correct is this: msr SPSR_fsxc, rN
2013-05-18score: use reference with strict mutexGedare Bloom1-1/+1
2013-05-16smp: Add maximum_processors field to configSebastian Huber3-10/+2
Delete rtems_configuration_get_smp_maximum_processors(). Delete rtems_configuration_smp_maximum_processors variable. Add maximum_processors field to rtems_configuration_table if RTEMS_SMP is defined. Add rtems_configuration_get_maximum_processors().
2013-05-10arm: Support VFP-D32 and NeonSebastian Huber9-38/+393
2013-05-10arm: Simplify architecture selectionSebastian Huber1-63/+5
2013-05-10score: Add CPU context validationSebastian Huber27-0/+889
2013-05-10arm: Add FUNCTION_THUMB_ENTRY(), etc.Sebastian Huber1-0/+17
Add FUNCTION_THUMB_ENTRY(), FUNCTION_ENTRY() and FUNCTION_END().
2013-05-10Revert bootstrap whitespace changes.Chris Johns14-0/+14
2013-05-07sparc: Fix problem with assembler filesSebastian Huber1-1/+1
2013-05-06sparc.h: Included stdint.hMohammed Khoory1-0/+2
This header uses uint32_t but does not include stdint.h This may cause problems when compiling applications that include BSP headers that include this file (leon.h for example)
2013-05-03arm: Switch to ARM only for Thumb-1Sebastian Huber1-1/+1
The Thumb-2 instruction set as encodings for the relevant instructions.
2013-05-03arm: Fix DEFINE_FUNCTION_ARM() for ARMv7-ARSebastian Huber1-1/+1
2013-05-01score/cpu/.../i386.h: PR2020: Remove soft float referencesJoel Sherrill1-46/+20
i386 soft-float is no longer supported by gcc. Dropping related code in the i386 score/cpu code.
2013-05-01Clear the atomic conditional compilation.WeiY2-4/+1
2013-05-01Using the generic atomic ops to implement UP mode atomic for all ↵WeiY45-0/+661
architectures. SMP atomic port will be later.
2013-05-01Implement a generic atomic ops for all UP mode architectures with ↵WeiY3-0/+279
disable/enable-IRQ function simulated.
2013-04-23mips: Fix warningsSebastian Huber1-0/+1
2013-04-02Fixed return in void functionAndreas Heinig1-1/+1
2013-03-18sparc/cpu.h: Add commentsJoel Sherrill1-0/+3
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