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Current state:
- Basic context initialization and switching code.
- Stubbed console (empty functions).
- Mostly functional linker script (may need tweaks if we ever want to move
away from the large code model (see: CPU_CFLAGS).
- Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for
UEFI-awareness.
In short, the current state with this commit lets us boot, go through the system
initialization functions, and then call user application's Init task too.
Updates #2898.
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An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.
Update #3433.
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Update #3433.
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See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".
Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Save/restore non-volatile registers in _CPU_Context_switch().
Save/restore volatile registers in _ISR_Handler().
Update #3433.
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Update #3433.
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Update #3433.
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Update #3433.
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Move SREG and LREG assembler defines to <rtems/score/asm.h>.
Update #3433.
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Update #3433.
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The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.
Create separate CPU_Interrupt_frame structure.
Update #3433.
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The RISC-V psABI
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
does not mention that this is a frame pointer.
Update #3433.
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Update #3433.
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Do not clear the complete thread context. Initialize only the necessary
members. The Context_Control::is_executing member must be preserved
across _CPU_Context_Initialize() calls.
Update #3433.
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According to the RISC-V psABI
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
the stack alignment is 128 bits (16 bytes).
Update #3433.
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The current ABI says that there is no stack red zone:
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
"Procedures must not rely upon the persistence of stack-allocated data
whose addresses lie below the stack pointer."
Update #3433.
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The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).
Update #2751.
Update #3433.
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Update #3433.
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Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).
Update #3433.
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Use the atomic read and clear operation to disable interrupts.
Do not write the complete mstatus. Instead, set only the MIE bit
depending on the level parameter.
Update #3433.
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Update #3433.
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Fix prototypes.
Update #3433.
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Update #3433.
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Use tabs to match the GCC generated assembler output.
Update #3433.
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Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
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Add CPU port define for the interrupt stack alignment. The alignment
should take the stack ABI and the cache line size into account.
Update #3459.
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Use the standard ARMv7-M systick module for the ARMv7-M CPU counter
instead of DWT counter since the DWT counter is affected by power saving
states.
Use an inline function for _CPU_Counter_difference() for all ARM BSPs.
Update #3456.
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Add rtems_counter_frequency() API function. Use it to initialize the
counter value converter via the new system initialization step
(RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation
and the counter converter. It avoids an unnecessary pull in of the
64-bit integer division from libgcc.
Update #3456.
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The mpc555 define is provided via <bspopts.h>. It must not be used in
cpukit header files.
Update #3425.
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Do not use isprint() from <ctype.h> since it depends on the heavy weight
C locale implementation in Newlib.
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This file is BSP-independent.
This patch is a part of the BSP source reorganization.
Update #3285.
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The definition of _CPU_Trap_slot_template is BSP-independent. A
potential para-virtualization support may use <rtems/score/paravirt.h>.
This patch is a part of the BSP source reorganization.
Update #3285.
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The following code
void f(void)
{
register int i;
}
gives a warning with GCC and -std=c++17
test.cc: In function ‘void f()’:
test.cc:3:15: warning: ISO C++1z does not allow ‘register’ storage class
specifier [-Wregister]
register int i;
^
and clang with -std=c++14
test.cc:3:3: warning: 'register' storage class specifier is deprecated
and incompatible with C++1z [-Wdeprecated-register]
register int i;
^~~~~~~~~
1 warning generated.
Remove the use of the register keyword at least in the public header
files for C++ compatibility.
Close #3397.
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A "make distclean" is not supported. So, it makes no sense to have pure
"make distclean" related stuff in the Makefile.am.
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A "make dist" is not supported. So, it makes no sense to have pure "make
dist" related stuff in the Makefile.am.
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Update #3117.
Update #3182.
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Update #3117.
Update #3182.
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When it's a macro, a function declaration causes a compiler error due to the
macro being expanded.
Partial log showing error:
https://gist.github.com/AmaanC/ab3521141479aa6f61ea25f5d74ebb4d
Closes #3331
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This change, excluding the #error directive, lets us make progress towards
compiling i386 targets with --enable-smp.
The #error directive needs to be there since the CPU_Interrupt_frame is used by
the SMP context switching code, and this placeholder struct, if used, would only
lead to more subtle bugs and errors. With the directive, the SMP context
switching code can be improved separately.
Updates #3331
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Closes #3346.
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Cannot read or write MSR when executing in user mode. This
is used when RTEMS_PARAVIRT is defined.
Provide alternate methods to disable/enable interrupts
Closes #3306.
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