rtems - RTEMS Kernel, file-systems, drivers, BSPs, samples, and testsuite.

	Commit message (Collapse)	Author	Age	Files	Lines
*	score: Add Per_CPU_Control::Interrupt_frame	Sebastian Huber	2016-11-18	1	-1/+13
\| \| \| \|	Update #2809.
*	score: Add Per_CPU_Control::isr_dispatch_disable	Sebastian Huber	2016-11-18	1	-0/+6
\| \| \| \|	Update #2751.
*	score: Fix C/C++ compatibility issue	Sebastian Huber	2016-09-23	1	-4/+6
\| \| \| \| \| \| \|	Only use CPU_Per_CPU_control if it contains at least one filed. In GNU C empty structures have a size of zero. In C++ structures have a non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not used anymore.
*	score: Add PER_CPU_OFFSET_EXECUTING	Sebastian Huber	2014-07-01	1	-0/+10
\| \| \| \| \|	Add PER_CPU_OFFSET_HEIR. Move Per_CPU_Control::executing and Per_CPU_Control::heir for easy offset calculation.
*	score: Clarify CPU port alignment requirements	Sebastian Huber	2014-04-07	1	-2/+33
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*	Change all references of rtems.com to rtems.org.	Chris Johns	2014-03-21	1	-1/+1
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*	score: Per-CPU thread dispatch disable level	Sebastian Huber	2013-08-09	1	-0/+6
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
*	score/cpu: Add CPU_Per_CPU_control	Sebastian Huber	2013-08-09	1	-0/+5
\| \| \| \|	Add CPU port specific per-CPU control.
*	smp: Provide cache optimized Per_CPU_Control	Sebastian Huber	2013-07-31	1	-1/+8
\| \| \| \|	Delete _Per_CPU_Information_p.
*	score: PR1607: Add and use CPU_SIZEOF_POINTER	Sebastian Huber	2012-11-22	1	-0/+59
	Add and use new CPU port define CPU_SIZEOF_POINTER. It must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code. The size of a pointer is part of the application binary interface (ABI) and thus independent of the actual programming language. The compiler will provide defines to determine the current ABI. We use these defines to select the appropriate CPU_SIZEOF_POINTER value. Static assertions in the new file "cpukit/score/src/percpuasm.c" will ensure that the value of CPU_SIZEOF_POINTER is consistent with the current compiler settings. Also the offset values used by assembler code are verfied.