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* Patch rtems-rc-4.5.0-13-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de>.Joel Sherrill2000-04-133-0/+6
| | | | adds .cvsignore.
* Patch from Eric Norum <eric@cls.usask.ca> to implement this:Joel Sherrill2000-01-211-2/+3
| | | | | | | | | | | | | | | | | | | | I'd like to propose a change to RTEMS task variables that I think would make them more useful. I think that it is early enough in their existence to still make changes to their API. 1) Change type from `int' to `void *'. 2) Add extra argument to task_variable_add -- if non-NULL, a pointer to a `destructor' function to be called when the task exits. This function would be called with that task's value of the task variable as its argument. In many cases, the `dtor' function could be `free'. rtems_status_code rtems_task_variable_add ( rtems_id tid, void **ptr, void (*dtor)(void *)); rtems_status_code rtems_task_variable_delete (rtems_id tid, void **ptr); This would be all we'd need to cleanly and efficiently support C++ per-thread exception information without dragging in all that POSIX API stuff.
* POSIX message queues now include complete functionality includingJoel Sherrill2000-01-131-8/+36
| | | | | | | | | | | | | | | | blocking sends when the queue is full. The SuperCore was enhanced to support blocking on send. The existing POSIX API was debugged and numerous test cases were added to psxmsgq01 by Jennifer Averett. SuperCore enhancements and resulting modifications to other APIs were done by Joel. There is one significant point of interpretation for the POSIX API. What happens to threads already blocked on a message queue when the mode of that same message queue is changed from blocking to non-blocking? We decided to unblock all waiting tasks with an EAGAIN error just as if a non-blocking version of the same operation had returned unsatisfied. This case is not discussed in the POSIX standard and other implementations may have chosen differently.
* Added support for simple binary semaphores in addition to the highJoel Sherrill2000-01-052-4/+35
| | | | | | | | | | | | power binary/mutex style semaphores already supported by RTEMS. This was done at the request of Eric Norum <eric@cls.usask.ca> in support of his effort to port EPICS to RTEMS. This change consisted of changing the nesting_allowed boolean into a lock_nesting_behavior enumerated value as well as allowing the core mutex object to optionally support ensuring that the holder of a binary semaphore released it. Finally, a more subtle enhancement was to allow the non-holder to release a priority inheritance/ceiling mutex and still allow the holding task to return to its original priority.
* + Added return priority from message seize.Jennifer Averett2000-01-051-10/+11
| | | | + Changed priority to be based off of min and max int.
* Updated copyright notice.Joel Sherrill1999-11-1730-63/+32
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* Moved task_variable pointer to basic shared part of TCB instead ofJoel Sherrill1999-11-161-0/+15
| | | | | | | RTEMS API extension to avoid problems when the extension is freed. Eventually the task variable switch extension should become part of the core context switch and the Ada tcb self implemented in terms of it.
* Added prototype for _Thread_Reset() and numerous comments.Joel Sherrill1999-11-161-4/+28
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* Committed modifications from ITRON Task and Task Dependendent SynchronizationJoel Sherrill1999-11-101-1/+47
| | | | Working Group. Included are tests.
* This patch adds the basic framework for the ITRON 3.0 API implementationJoel Sherrill1999-11-094-23/+57
| | | | for RTEMS.
* This is another pass at making sure that nothing outside the BSPJoel Sherrill1999-11-051-0/+40
| | | | | | | | | | | | unnecessarily uses any variables defined by the BSP. On this sweep, use of BSP_Configuration and Cpu_table was eliminated. A significant part of this modification was the addition of macros to access fields in the RTEMS configuration structures. This is necessary to strengthen the division between the BSP independent parts of RTEMS and the BSPs themselves. This started after comments and analysis by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
* Added maximum count detection logic.Joel Sherrill1999-11-021-1/+3
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* Added support for message priority as required by POSIX.Joel Sherrill1999-11-021-4/+10
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* Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de> to make fix bugJoel Sherrill1999-10-041-3/+3
| | | | where wrapup left pieces out of the librtemsall.a.
* Applied patch rtems-rc-19990820-6.diff.gz fromJoel Sherrill1999-09-071-0/+10
| | | | | Ralf Corsepius <corsepiu@faw.uni-ulm.de> which converted many Makefile.in's to Makefile.am's. This added a lot of files.
* Patch from Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca> to addJoel Sherrill1999-08-301-1/+6
| | | | | support for return codes from POSIX threads that do an implicit exit by returning from the bottom of the main function.
* This is a large patch from Eric Valette <valette@crf.canon.fr> that wasJoel Sherrill1999-06-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | described in the message following this paragraph. This patch also includes a mcp750 BSP. From valette@crf.canon.fr Mon Jun 14 10:03:08 1999 Date: Tue, 18 May 1999 01:30:14 +0200 (CEST) From: VALETTE Eric <valette@crf.canon.fr> To: joel@oarcorp.com Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr Subject: Questions/Suggestion regarding RTEMS PowerPC code (long) Dear knowledgeable RTEMS powerpc users, As some of you may know, I'm currently finalizing a port of RTEMS on a MCP750 Motorola board. I have done most of it but have some questions to ask before submitting the port. In order to understand some of the changes I have made or would like to make, maybe it is worth describing the MCP750 Motorola board. the MCP750 is a COMPACT PCI powerpc board with : 1) a MPC750 233 MHz processor, 2) a raven bus bridge/PCI controller that implement an OPENPIC compliant interrupt controller, 3) a VIA 82C586 PCI/ISA bridge that offers a PC compliant IO for keyboard, serial line, IDE, and the well known PC 8259 cascaded PIC interrupt architecture model, 4) a DEC 21140 Ethernet controller, 5) the PPCBUG Motorola firmware in flash, 6) A DEC PCI bridge, This architecture is common to most Motorola 60x/7xx board except that : 1) on VME board, the DEC PCI bridge is replaced by a VME chipset, 2) the VIA 82C586 PCI/ISA bridge is replaced by another bridge that is almost fully compatible with the via bridge... So the port should be a rather close basis for many 60x/7xx motorola board... On this board, I already have ported Linux 2.2.3 and use it both as a development and target board. Now the questions/suggestions I have : 1) EXCEPTION CODE ------------------- As far as I know exceptions on PPC are handled like interrupts. I dislike this very much as : a) Except for the decrementer exception (and maybe some other on mpc8xx), exceptions are not recoverable and the handler just need to print the full context and go to the firmware or debugger... b) The interrupt switch is only necessary for the decrementer and external interrupt (at least on 6xx,7xx). c) The full context for exception is never saved and thus cannot be used by debugger... I do understand the most important for interrupts low level code is to save the minimal context enabling to call C code for performance reasons. On non recoverable exception on the other hand, the most important is to save the maximum information concerning proc status in order to analyze the reason of the fault. At least we will need this in order to implement the port of RGDB on PPC ==> I wrote an API for connecting raw exceptions (and thus raw interrupts) for mpc750. It should be valid for most powerpc processors... I hope to find a way to make this coexist with actual code layout. The code is actually located in lib/libcpu/powerpc/mpc750 and is thus optional (provided I write my own version of exec/score/cpu/powerpc/cpu.c ...) See remark about files/directory layout organization in 4) 2) Current Implementation of ISR low level code ----------------------------------------------- I do not understand why the MSR EE flags is cleared again in exec/score/cpu/powerpc/irq_stubs.S #if (PPC_USE_SPRG) mfmsr r5 mfspr r6, sprg2 #else lwz r6,msr_initial(r11) lis r5,~PPC_MSR_DISABLE_MASK@ha ori r5,r5,~PPC_MSR_DISABLE_MASK@l and r6,r6,r5 mfmsr r5 #endif Reading the doc, when a decrementer interrupt or an external interrupt is active, the MSR EE flag is already cleared. BTW if exception/interrupt could occur, it would trash SRR0 and SRR1. In fact the code may be useful to set MSR[RI] that re-enables exception processing. BTW I will need to set other value in MSR to handle interrupts : a) I want the MSR[IR] and MSR[DR] to be set for performance reasons and also because I need DBAT support to have access to PCI memory space as the interrupt controller is in the PCI space. Reading the code, I see others have the same kind of request : /* SCE 980217 * * We need address translation ON when we call our ISR routine mtmsr r5 */ This is just another prof that even the lowest level IRQ code is fundamentally board dependent and not simply processor dependent especially when the processor use external interrupt controller because it has a single interrupt request line... Note that if you look at the PPC code high level interrupt handling code, as the "set_vector" routine that really connects the interrupt is in the BSP/startup/genpvec.c, the fact that IRQ handling is BSP specific is DE-FACTO acknowledged. I know I have already expressed this and understand that this would require some heavy change in the code but believe me you will reach a point where you will not be able to find a compatible while optimum implementation for low level interrupt handling code...) In my case this is already true... So please consider removing low level IRQ handling from exec/score/cpu/* and only let there exception handling code... Exceptions are usually only processor dependent and do not depend on external hardware mechanism to be masked or acknowledged or re-enabled (there are probably exception but ...) I have already done this for pc386 bsp but need to make it again. This time I will even propose an API. 3) R2/R13 manipulation for EABI implementation ---------------------------------------------- I do not understand the handling of r2 and r13 in the EABI case. The specification for r2 says pointer to sdata2, sbss2 section => constant. However I do not see -ffixed-r2 passed to any compilation system in make/custom/* (for info linux does this on PPC). So either this is a default compiler option when choosing powerpc-rtems and thus we do not need to do anything with this register as all the code is compiled with this compiler and linked together OR this register may be used by rtems code and then we do not need any special initialization or handling. The specification for r13 says pointer to the small data area. r13 argumentation is the same except that as far as I know the usage of the small data area requires specific compiler support so that access to variables is compiled via loading the LSB in a register and then using r13 to get full address... It is like a small memory model and it was present in IBM C compilers. => I propose to suppress any specific code for r2 and r13 in the EABI case. 4) Code layout organization (yes again :-)) ------------------------------------------- I think there are a number of design flaws in the way the code is for ppc organized and I will try to point them out. I have been beaten by this again on this new port, and was beaten last year while modifying code for pc386. a) exec/score/cpu/* vs lib/libcpu/cpu/*. I think that too many things are put in exec/score/cpu that have nothing to do with RTEMS internals but are rather related to CPU feature. This include at least : a) registers access routine (e.g GET_MSR_Value), b) interrupt masking/unmasking routines, c) cache_mngt_routine, d) mmu_mngt_routine, e) Routines to connect the raw_exception, raw_interrupt handler, b) lib/libcpu/cpu/powerpc/* With a processor family as exuberant as the powerpc family, and their well known subtle differences (604 vs 750) or unfortunately majors (8xx vs 60x) the directory structure is fine (except maybe the names that are not homogeneous) powerpc ppc421 mpc821 ... I only needed to add mpc750. But the fact that libcpu.a was not produced was a pain and the fact that this organization may duplicates code is also problematic. So, except if the support of automake provides a better solution I would like to propose something like this : powerpc mpc421 mpc821 ... mpc750 shared wrapup with the following rules : a) "shared" would act as a source container for sources that may be shared among processors. Needed files would be compiled inside the processor specific directory using the vpath Makefile mechanism. "shared" may also contain compilation code for routine that are really shared and not worth to inline... (did not found many things so far as registers access routine ARE WORTH INLINING)... In the case something is compiled there, it should create libcpushared.a b) layout under processor specific directory is free provided that 1)the result of the compilation process exports : libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu 2) each processor specific directory creates a library called libcpuspecific.a Note that this organization enables to have a file that is nearly the same than in shared but that must differ because of processor differences... c) "wrapup" should create libcpu.a using libcpushared.a libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu The only thing I have no ideal solution is the way to put shared definitions in "shared" and only processor specific definition in "proc". To give a concrete example, most MSR bit definition are shared among PPC processors and only some differs. if we create a single msr.h in shared it will have ifdef. If in msr.h we include libcpu/msr_c.h we will need to have it in each prowerpc specific directory (even empty). Opinions are welcomed ... Note that a similar mechanism exist in libbsp/i386 that also contains a shared directory that is used by several bsp like pc386 and i386ex and a similar wrapup mechanism... NB: I have done this for mpc750 and other processors could just use similar Makefiles... c) The exec/score/cpu/powerpc directory layout. I think the directory layout should be the same than the libcpu/powerpc. As it is not, there are a lot of ifdefs inside the code... And of course low level interrupt handling code should be removed... Besides that I do not understand why 1) things are compiled in the wrap directory, 2) some includes are moved to rtems/score, I think the "preinstall" mechanism enables to put everything in the current directory (or better in a per processor directory), 5) Interrupt handling API ------------------------- Again :-). But I think that using all the features the PIC offers is a MUST for RT system. I already explained in the prologue of this (long and probably boring) mail that the MCP750 boards offers an OPENPIC compliant architecture and that the VIA 82586 PCI/ISA bridge offers a PC compatible IO and PIC mapping. Here is a logical view of the RAVEN/VIA 82586 interrupt mapping : --------- 0 ------ | OPEN | <-----|8259| | PIC | | | 2 ------ |(RAVEN)| | | <-----|8259| | | | | | | 11 | | | | | | <---- | | | | | | | | | | | | --------- ------ | | ^ ------ | VIA PCI/ISA bridge | x -------- PCI interrupts OPENPIC offers interrupt priorities among PCI interrupts and interrupt selective masking. The 8259 offers the same kind of feature. With actual powerpc interrupt code : 1) there is no way to specify priorities among interrupts handler. This is REALLY a bad thing. For me it is as importnat as having priorities for threads... 2) for my implementation, each ISR should contain the code that acknowledge the RAVEN and 8259 cascade, modify interrupt mask on both chips, and reenable interrupt at processor level, ..., restore then on interrupt return,.... This code is actually similar to code located in some genpvec.c powerpc files, 3) I must update _ISR_Nesting_level because irq.inl use it... 4) the libchip code connects the ISR via set_vector but the libchip handler code does not contain any code to manipulate external interrupt controller hardware in order to acknoledge the interrupt or re-enable them (except for the target hardware of course) So this code is broken unless set_vector adds an additionnal prologue/epilogue before calling/returning from in order to acknoledge/mask the raven and the 8259 PICS... => Anyway already EACH BSP MUST REWRITE PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT SET_VECTOR. I would rather offer an API similar to the one provided in libbsp/i386/shared/irq/irq.h so that : 1) Once the driver supplied methods is called the only things the ISR has to do is to worry about the external hardware that triggered the interrupt. Everything on openpic/VIA/processor would have been done by the low levels (same things as set-vector) 2) The caller will need to supply the on/off/isOn routine that are fundamental to correctly implements debuggers/performance monitoring is a portable way 3) A globally configurable interrupt priorities mechanism... I have nothing against providing a compatible set_vector just to make libchip happy but as I have already explained in other mails (months ago), I really think that the ISR connection should be handled by the BSP and that no code containing irq connection should exist the rtems generic layers... Thus I really dislike libchip on this aspect because in a long term it will force to adopt the less reach API for interrupt handling that exists (set_vector). Additional note : I think the _ISR_Is_in_progress() inline routine should be : 1) Put in a processor specific section, 2) Should not rely on a global variable, As : a) on symmetric MP, there is one interrupt level per CPU, b) On processor that have an ISP (e,g 68040), this variable is useless (MSR bit testing could be used) c) On PPC, instead of using the address of the variable via __CPU_IRQ_info.Nest_level a dedicated SPR could be used. NOTE: most of this is also true for _Thread_Dispatch_disable_level END NOTE -------- Please do not take what I said in the mail as a criticism for anyone who submitted ppc code. Any code present helped me a lot understanding PPC behavior. I just wanted by this mail to : 1) try to better understand the actual code, 2) propose concrete ways of enhancing current code by providing an alternative implementation for MCP750. I will make my best effort to try to brake nothing but this is actually hard due to the file layout organisation. 3) make understandable some changes I will probably make if joel let me do them :-) Any comments/objections are welcomed as usual. -- __ / ` Eric Valette /-- __ o _. Canon CRF (___, / (_(_(__ Rue de la touche lambert 35517 Cesson-Sevigne Cedex FRANCE Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30 E-mail: valette@crf.canon.fr
* Added comments.Joel Sherrill1999-06-111-1/+1
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* Splitting the Thread Handler forced the inclusion of more prototypes.Joel Sherrill1999-05-171-0/+33
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* Unlimited objects patch from Chris Johns <ccj@acm.org>. Email follows:Joel Sherrill1999-03-171-28/+82
| | | | | | | | | | | | | | | | | | | | | | | | | First, the unlimited patch. I have compiled the unlmited patch for the Linux posix BSP only and it seems to work cleanly. I would like a really major application run on this change before commiting as the changes are very core and significant. I am currently building all the tests to run. I have no targets suitable to test on at the moment. I have tested the patch for inline functions and macros. Turning macros on has found some core bugs. I have fixed these but have not run all the tests. Please review the patch for these changes. They are: 1) The conditional compilation for MP support broke the core messages code. You cannot embed a conditional macro in another macro. The Send and Urgent Send calls are macros. 2) User extensions handler initialisation now has two parameters. I have updated the macros to support the extra parameter. The patch also contains the gcc-target-default.cfg fix required to build the kernel. More of a by product than a fix for you.
* Added --disable-multiprocessing flag and modified a lot of files to makeJoel Sherrill1998-11-232-0/+10
| | | | it work.
* Patch from Eric Norum <eric@skatter.usask.ca>:Joel Sherrill1998-11-191-0/+7
| | | | | | | | | | | | | | | 1) Socket timeout field changed from `short' to `long'. This makes longer timeouts possible. With a 1 kHz system clock the old system allowed timeouts only up to a little over 30 seconds! This change is a slightly cleaned-up version of the patch proposed by Ian Lance Taylor. 2) Major changes to BOOTP/DHCP reply handling. Now supports much of RFC2132. These changes were done at the request of, and with the assistance of, Erik Ivanenko. If you're making changes, you might want to change the network supplement Essentially just do a global search and replace of BOOTP with BOOTP/DHCP.
* IDLE task stack size now specified as a field in the CPU Table for allJoel Sherrill1998-09-231-8/+0
| | | | ports.
* Added CPU_ISR_PASSES_FRAME_POINTER so some ports could pass just theJoel Sherrill1998-06-031-0/+7
| | | | | vector number to user ISR's and other ports could pass both the vector number and a pointer to the ISF.
* Per suggestion from Eric Norum, went from one initial extension setJoel Sherrill1998-04-151-7/+0
| | | | | | to multiple. This lets the stack check extension be installed at system initialization time and avoids the BSP having to even know about its existence.
* updated copyright to 1998Joel Sherrill1998-02-1730-31/+31
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* Error reported by Duncan Smith <dds@flavors.com>:Joel Sherrill1998-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | >> >>There is a 30 day error in _TOD_Days_since_last_leap_year[2..3] >> > >> >Thanks. >> >What's the condition to hit this error? >> >Every year 4n+2 and 4n+3 ? >> >(i.e. 1998, 1999, 2002, 2003, ...) >> > >> OK: 96 97 00 01 04 05 ... >> Bad: 98 99 02 03 06 07 ... There is also a problem in newlib 1.7.x reported at the same time: >> I found another, that would strike only on 2/29/2000, or other leapyears. >> Only a problem on 1 day. >> >> Joel: FYI, there is a bug in Newlib localtime.c, localtime or (_tm_time). >> Ours is modified for dst and timezones, but the bug was in original source. >> I have not looked at the latest public source (nor do I know where to find >> it).
* Moved include of rtems/score/cpu.h to make sure TRUE and FALSE were defined.Joel Sherrill1997-12-061-2/+2
| | | | | This simple error resulted in the wrong FP context structure being used for hardware contexts on the m68k. This was a difficult problem to find.
* Fixed typo in the pointer to the license terms.Joel Sherrill1997-10-0830-60/+60
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* Fixed comment.Joel Sherrill1997-10-061-1/+1
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* Added post switch extension.Joel Sherrill1997-07-091-0/+5
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* Patch from Chris John <cjohns@awa.com.au> to add use of a select statementJoel Sherrill1997-04-221-0/+15
| | | | | | in the unix port idle thread task. This should keep the entire application from blocking when any component does a blocking application. Also added TOD_MICROSECONDS_TO_TICKS.
* headers updated to reflect new style copyright notice as partJoel Sherrill1997-04-2230-152/+152
| | | | of switching to the modified GNU GPL.
* corrected spacing.Joel Sherrill1997-04-091-8/+8
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* added SYSTEM_STATE_SHUTDOWNJoel Sherrill1997-04-091-0/+1
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* Modified calls to _Thread_Change_priority to take a third argument. The newJoel Sherrill1997-03-081-1/+2
| | | | | | | | | argument indicates whether the task is to be placed at the head or tail of its priority fifo when it is lowering its own priority. POSIX normally follows the RTEMS API conventions but GNAT expects that all lowering of a task's priority by the task itself will result in being placed at the head of the priority FIFO. Normally, this would only occur as the result of lose of inherited priority.
* Removed definitions which are now in targopts.h. This eliminates theJoel Sherrill1997-01-291-8/+4
| | | | | need for the "sed'ing" of this file. This should be a significant win when addressing non-unix host and non-gnu toolsets.
* added type to macro to eliminate warning for untyped use of a register.Joel Sherrill1997-01-291-1/+1
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* added type definitions for all supported task entry formatsJoel Sherrill1997-01-081-1/+6
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* added cpu time used field to tcbJoel Sherrill1996-10-151-0/+1
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* OBJECTS_NAME_ALIGNMENT definition changed to use sizeof rather thanJoel Sherrill1996-09-181-2/+2
| | | | hardcoded 4 to be compatible with CPUs with 64-bit ints
* MP_PACKET_MINIMUN_HETERO_CONVERSION definition changed to use sizeofJoel Sherrill1996-09-181-1/+2
| | | | rather than hardcoded 4 to be compatible with CPUs with 64-bit ints
* modified declaration of CORE_message_queue_Buffer_control to avoid useJoel Sherrill1996-09-181-11/+4
| | | | of GNU C extension
* changed _TOD_Is_set from a function to a boolean variableJoel Sherrill1996-09-061-0/+7
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* removed count from Thread_queue_ControlMark Johannes1996-08-131-1/+0
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* CORE_mutex_Status: added CORE_MUTEX_STATUS_CEILING_VIOLATED to enumMark Johannes1996-08-081-1/+2
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* _MPCI_Register_packet_processor: Changed prototype of fist parameter name to ↵Mark Johannes1996-08-081-1/+1
| | | | the_class
* switched from "STATIC INLINE" to "RTEMS_INLINE_ROUTINE"Joel Sherrill1996-07-031-5/+3
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* Added code so post context switch extensions can be run on every contextJoel Sherrill1996-06-131-0/+7
| | | | switch. This was needed to support process wide signals.
* added waiting for signal state.Joel Sherrill1996-06-121-19/+21
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